1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Copyright 2014 Soeren Moch <smoch@web.de>
4
5/dts-v1/;
6
7#include "imx6q.dtsi"
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10
11/ {
12	model = "TBS2910 Matrix ARM mini PC";
13	compatible = "tbs,imx6q-tbs2910", "fsl,imx6q";
14
15	chosen {
16		stdout-path = &uart1;
17	};
18
19	memory@10000000 {
20		device_type = "memory";
21		reg = <0x10000000 0x80000000>;
22	};
23
24	fan {
25		compatible = "gpio-fan";
26		pinctrl-names = "default";
27		pinctrl-0 = <&pinctrl_gpio_fan>;
28		gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
29		gpio-fan,speed-map = <0    0
30				      3000 1>;
31	};
32
33	ir_recv {
34		compatible = "gpio-ir-receiver";
35		gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
36		pinctrl-names = "default";
37		pinctrl-0 = <&pinctrl_ir>;
38	};
39
40	leds {
41		compatible = "gpio-leds";
42		pinctrl-names = "default";
43		pinctrl-0 = <&pinctrl_gpio_leds>;
44
45		blue {
46			label = "blue_status_led";
47			gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
48			default-state = "keep";
49		};
50	};
51
52	reg_2p5v: regulator-2p5v {
53		compatible = "regulator-fixed";
54		regulator-name = "2P5V";
55		regulator-min-microvolt = <2500000>;
56		regulator-max-microvolt = <2500000>;
57	};
58
59	reg_3p3v: regulator-3p3v {
60		compatible = "regulator-fixed";
61		regulator-name = "3P3V";
62		regulator-min-microvolt = <3300000>;
63		regulator-max-microvolt = <3300000>;
64	};
65
66	reg_5p0v: regulator-5p0v {
67		compatible = "regulator-fixed";
68		regulator-name = "5P0V";
69		regulator-min-microvolt = <5000000>;
70		regulator-max-microvolt = <5000000>;
71	};
72
73	sound-sgtl5000 {
74		audio-codec = <&sgtl5000>;
75		audio-routing =
76			"MIC_IN", "Mic Jack",
77			"Mic Jack", "Mic Bias",
78			"Headphone Jack", "HP_OUT";
79		compatible = "fsl,imx-audio-sgtl5000";
80		model = "On-board Codec";
81		mux-ext-port = <3>;
82		mux-int-port = <1>;
83		ssi-controller = <&ssi1>;
84	};
85
86	sound-spdif {
87		compatible = "fsl,imx-audio-spdif";
88		model = "On-board SPDIF";
89		spdif-controller = <&spdif>;
90		spdif-out;
91	};
92};
93
94&audmux {
95	status = "okay";
96};
97
98&fec {
99	pinctrl-names = "default";
100	pinctrl-0 = <&pinctrl_enet>;
101	phy-mode = "rgmii-id";
102	phy-handle = <&phy>;
103	status = "okay";
104
105	mdio {
106		#address-cells = <1>;
107		#size-cells = <0>;
108
109		phy: ethernet-phy@4 {
110			reg = <4>;
111			qca,clk-out-frequency = <125000000>;
112			reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
113			reset-assert-us = <10000>;
114		};
115	};
116};
117
118&hdmi {
119	pinctrl-names = "default";
120	pinctrl-0 = <&pinctrl_hdmi>;
121	ddc-i2c-bus = <&i2c2>;
122	status = "okay";
123};
124
125&i2c1 {
126	clock-frequency = <100000>;
127	pinctrl-names = "default";
128	pinctrl-0 = <&pinctrl_i2c1>;
129	status = "okay";
130
131	sgtl5000: sgtl5000@a {
132		clocks = <&clks IMX6QDL_CLK_CKO>;
133		compatible = "fsl,sgtl5000";
134		pinctrl-names = "default";
135		pinctrl-0 = <&pinctrl_sgtl5000>;
136		reg = <0x0a>;
137		VDDA-supply = <&reg_2p5v>;
138		VDDIO-supply = <&reg_3p3v>;
139	};
140};
141
142&i2c2 {
143	clock-frequency = <100000>;
144	pinctrl-names = "default";
145	pinctrl-0 = <&pinctrl_i2c2>;
146	status = "okay";
147};
148
149&i2c3 {
150	clock-frequency = <100000>;
151	pinctrl-names = "default";
152	pinctrl-0 = <&pinctrl_i2c3>;
153	status = "okay";
154
155	rtc: ds1307@68 {
156		compatible = "dallas,ds1307";
157		reg = <0x68>;
158	};
159};
160
161&pcie {
162	pinctrl-names = "default";
163	pinctrl-0 = <&pinctrl_pcie>;
164	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
165	status = "okay";
166};
167
168&sata {
169	fsl,transmit-level-mV = <1104>;
170	fsl,transmit-boost-mdB = <3330>;
171	fsl,transmit-atten-16ths = <16>;
172	fsl,receive-eq-mdB = <3000>;
173	status = "okay";
174};
175
176&snvs_poweroff {
177	status = "okay";
178};
179
180&spdif {
181	pinctrl-names = "default";
182	pinctrl-0 = <&pinctrl_spdif>;
183	status = "okay";
184};
185
186&ssi1 {
187	status = "okay";
188};
189
190&uart1 {
191	pinctrl-names = "default";
192	pinctrl-0 = <&pinctrl_uart1>;
193	status = "okay";
194};
195
196&uart2 {
197	pinctrl-names = "default";
198	pinctrl-0 = <&pinctrl_uart2>;
199	status = "okay";
200};
201
202&usbh1 {
203	vbus-supply = <&reg_5p0v>;
204	status = "okay";
205};
206
207&usbotg {
208	vbus-supply = <&reg_5p0v>;
209	pinctrl-names = "default";
210	pinctrl-0 = <&pinctrl_usbotg>;
211	disable-over-current;
212	status = "okay";
213};
214
215&usdhc2 {
216	pinctrl-names = "default";
217	pinctrl-0 = <&pinctrl_usdhc2>;
218	bus-width = <4>;
219	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
220	vmmc-supply = <&reg_3p3v>;
221	vqmmc-supply = <&reg_3p3v>;
222	voltage-ranges = <3300 3300>;
223	no-1-8-v;
224	status = "okay";
225};
226
227&usdhc3 {
228	pinctrl-names = "default";
229	pinctrl-0 = <&pinctrl_usdhc3>;
230	bus-width = <4>;
231	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
232	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
233	vmmc-supply = <&reg_3p3v>;
234	vqmmc-supply = <&reg_3p3v>;
235	voltage-ranges = <3300 3300>;
236	no-1-8-v;
237	status = "okay";
238};
239
240&usdhc4 {
241	pinctrl-names = "default";
242	pinctrl-0 = <&pinctrl_usdhc4>;
243	bus-width = <8>;
244	vmmc-supply = <&reg_3p3v>;
245	vqmmc-supply = <&reg_3p3v>;
246	voltage-ranges = <3300 3300>;
247	non-removable;
248	no-1-8-v;
249	status = "okay";
250};
251
252&iomuxc {
253	pinctrl_enet: enetgrp {
254		fsl,pins = <
255			MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
256			MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
257			MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b030
258			MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b030
259			MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b030
260			MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b030
261			MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b030
262			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
263			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
264			MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b030
265			MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b030
266			MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b030
267			MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b030
268			MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b030
269			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
270			MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
271			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25    0x1b059
272		>;
273	};
274
275	pinctrl_gpio_fan: gpiofangrp {
276		fsl,pins = <
277			MX6QDL_PAD_EIM_D28__GPIO3_IO28        0x130b1
278		>;
279	};
280
281	pinctrl_gpio_leds: gpioledsgrp {
282		fsl,pins = <
283			MX6QDL_PAD_GPIO_2__GPIO1_IO02         0x130b1
284		>;
285	};
286
287	pinctrl_hdmi: hdmigrp {
288		fsl,pins = <
289			MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
290		>;
291	};
292
293	pinctrl_i2c1: i2c1grp {
294		fsl,pins = <
295			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL        0x4001b8b1
296			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA        0x4001b8b1
297		>;
298	};
299
300	pinctrl_i2c2: i2c2grp {
301		fsl,pins = <
302			MX6QDL_PAD_KEY_COL3__I2C2_SCL         0x4001b8b1
303			MX6QDL_PAD_KEY_ROW3__I2C2_SDA         0x4001b8b1
304		>;
305	};
306
307	pinctrl_i2c3: i2c3grp {
308		fsl,pins = <
309			MX6QDL_PAD_GPIO_3__I2C3_SCL           0x4001b8b1
310			MX6QDL_PAD_GPIO_6__I2C3_SDA           0x4001b8b1
311		>;
312	};
313
314	pinctrl_ir: irgrp {
315		fsl,pins = <
316			MX6QDL_PAD_EIM_D18__GPIO3_IO18        0x17059
317		>;
318	};
319
320	pinctrl_pcie: pciegrp {
321		fsl,pins = <
322			MX6QDL_PAD_GPIO_17__GPIO7_IO12        0x17059
323		>;
324	};
325
326	pinctrl_sgtl5000: sgtl5000grp {
327		fsl,pins = <
328			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD        0x130b0
329			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC        0x130b0
330			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD        0x110b0
331			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS       0x130b0
332			MX6QDL_PAD_GPIO_0__CCM_CLKO1          0x130b0
333		>;
334	};
335
336	pinctrl_spdif: spdifgrp {
337		fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT     0x13091
338		>;
339	};
340
341	pinctrl_uart1: uart1grp {
342		fsl,pins = <
343			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA  0x1b0b1
344			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA  0x1b0b1
345		>;
346	};
347
348	pinctrl_uart2: uart2grp {
349		fsl,pins = <
350			MX6QDL_PAD_EIM_D26__UART2_TX_DATA     0x1b0b1
351			MX6QDL_PAD_EIM_D27__UART2_RX_DATA     0x1b0b1
352		>;
353	};
354
355	pinctrl_usbotg: usbotggrp {
356		fsl,pins = <
357			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID     0x17059
358		>;
359	};
360
361	pinctrl_usdhc2: usdhc2grp {
362		fsl,pins = <
363			MX6QDL_PAD_SD2_CMD__SD2_CMD           0x17059
364			MX6QDL_PAD_SD2_CLK__SD2_CLK           0x10059
365			MX6QDL_PAD_SD2_DAT0__SD2_DATA0        0x17059
366			MX6QDL_PAD_SD2_DAT1__SD2_DATA1        0x17059
367			MX6QDL_PAD_SD2_DAT2__SD2_DATA2        0x17059
368			MX6QDL_PAD_SD2_DAT3__SD2_DATA3        0x17059
369			MX6QDL_PAD_NANDF_D2__GPIO2_IO02       0x17059
370		>;
371	};
372
373	pinctrl_usdhc3: usdhc3grp {
374		fsl,pins = <
375			MX6QDL_PAD_SD3_CMD__SD3_CMD           0x17059
376			MX6QDL_PAD_SD3_CLK__SD3_CLK           0x10059
377			MX6QDL_PAD_SD3_DAT0__SD3_DATA0        0x17059
378			MX6QDL_PAD_SD3_DAT1__SD3_DATA1        0x17059
379			MX6QDL_PAD_SD3_DAT2__SD3_DATA2        0x17059
380			MX6QDL_PAD_SD3_DAT3__SD3_DATA3        0x17059
381			MX6QDL_PAD_NANDF_D0__GPIO2_IO00       0x17059
382			MX6QDL_PAD_NANDF_D1__GPIO2_IO01       0x17059
383		>;
384	};
385
386	pinctrl_usdhc4: usdhc4grp {
387		fsl,pins = <
388			MX6QDL_PAD_SD4_CMD__SD4_CMD           0x17059
389			MX6QDL_PAD_SD4_CLK__SD4_CLK           0x10059
390			MX6QDL_PAD_SD4_DAT0__SD4_DATA0        0x17059
391			MX6QDL_PAD_SD4_DAT1__SD4_DATA1        0x17059
392			MX6QDL_PAD_SD4_DAT2__SD4_DATA2        0x17059
393			MX6QDL_PAD_SD4_DAT3__SD4_DATA3        0x17059
394			MX6QDL_PAD_SD4_DAT4__SD4_DATA4        0x17059
395			MX6QDL_PAD_SD4_DAT5__SD4_DATA5        0x17059
396			MX6QDL_PAD_SD4_DAT6__SD4_DATA6        0x17059
397			MX6QDL_PAD_SD4_DAT7__SD4_DATA7        0x17059
398		>;
399	};
400};
401