1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
4 *
5 * Device Tree binding constants clock controllers of Samsung S3C2443 and later.
6 */
7
8#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H
9#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H
10
11/*
12 * Let each exported clock get a unique index, which is used on DT-enabled
13 * platforms to lookup the clock from a clock specifier. These indices are
14 * therefore considered an ABI and so must not be changed. This implies
15 * that new clocks should be added either in free spaces between clock groups
16 * or at the end.
17 */
18
19/* Core clocks. */
20#define MSYSCLK			1
21#define ESYSCLK			2
22#define ARMDIV			3
23#define ARMCLK			4
24#define HCLK			5
25#define PCLK			6
26#define MPLL			7
27#define EPLL			8
28
29/* Special clocks */
30#define SCLK_HSSPI0		16
31#define SCLK_FIMD		17
32#define SCLK_I2S0		18
33#define SCLK_I2S1		19
34#define SCLK_HSMMC1		20
35#define SCLK_HSMMC_EXT		21
36#define SCLK_CAM		22
37#define SCLK_UART		23
38#define SCLK_USBH		24
39
40/* Muxes */
41#define MUX_HSSPI0		32
42#define MUX_HSSPI1		33
43#define MUX_HSMMC0		34
44#define MUX_HSMMC1		35
45
46/* hclk-gates */
47#define HCLK_DMA0		48
48#define HCLK_DMA1		49
49#define HCLK_DMA2		50
50#define HCLK_DMA3		51
51#define HCLK_DMA4		52
52#define HCLK_DMA5		53
53#define HCLK_DMA6		54
54#define HCLK_DMA7		55
55#define HCLK_CAM		56
56#define HCLK_LCD		57
57#define HCLK_USBH		58
58#define HCLK_USBD		59
59#define HCLK_IROM		60
60#define HCLK_HSMMC0		61
61#define HCLK_HSMMC1		62
62#define HCLK_CFC		63
63#define HCLK_SSMC		64
64#define HCLK_DRAM		65
65#define HCLK_2D			66
66
67/* pclk-gates */
68#define PCLK_UART0		72
69#define PCLK_UART1		73
70#define PCLK_UART2		74
71#define PCLK_UART3		75
72#define PCLK_I2C0		76
73#define PCLK_SDI		77
74#define PCLK_SPI0		78
75#define PCLK_ADC		79
76#define PCLK_AC97		80
77#define PCLK_I2S0		81
78#define PCLK_PWM		82
79#define PCLK_WDT		83
80#define PCLK_RTC		84
81#define PCLK_GPIO		85
82#define PCLK_SPI1		86
83#define PCLK_CHIPID		87
84#define PCLK_I2C1		88
85#define PCLK_I2S1		89
86#define PCLK_PCM		90
87
88/* Total number of clocks. */
89#define NR_CLKS			(PCLK_PCM + 1)
90
91#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */
92