1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 4 * Author: Chanwoo Choi <cw00.choi@samsung.com> 5 */ 6 7#ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H 8#define _DT_BINDINGS_CLOCK_EXYNOS5433_H 9 10/* CMU_TOP */ 11#define CLK_FOUT_ISP_PLL 1 12#define CLK_FOUT_AUD_PLL 2 13 14#define CLK_MOUT_AUD_PLL 10 15#define CLK_MOUT_ISP_PLL 11 16#define CLK_MOUT_AUD_PLL_USER_T 12 17#define CLK_MOUT_MPHY_PLL_USER 13 18#define CLK_MOUT_MFC_PLL_USER 14 19#define CLK_MOUT_BUS_PLL_USER 15 20#define CLK_MOUT_ACLK_HEVC_400 16 21#define CLK_MOUT_ACLK_CAM1_333 17 22#define CLK_MOUT_ACLK_CAM1_552_B 18 23#define CLK_MOUT_ACLK_CAM1_552_A 19 24#define CLK_MOUT_ACLK_ISP_DIS_400 20 25#define CLK_MOUT_ACLK_ISP_400 21 26#define CLK_MOUT_ACLK_BUS0_400 22 27#define CLK_MOUT_ACLK_MSCL_400_B 23 28#define CLK_MOUT_ACLK_MSCL_400_A 24 29#define CLK_MOUT_ACLK_GSCL_333 25 30#define CLK_MOUT_ACLK_G2D_400_B 26 31#define CLK_MOUT_ACLK_G2D_400_A 27 32#define CLK_MOUT_SCLK_JPEG_C 28 33#define CLK_MOUT_SCLK_JPEG_B 29 34#define CLK_MOUT_SCLK_JPEG_A 30 35#define CLK_MOUT_SCLK_MMC2_B 31 36#define CLK_MOUT_SCLK_MMC2_A 32 37#define CLK_MOUT_SCLK_MMC1_B 33 38#define CLK_MOUT_SCLK_MMC1_A 34 39#define CLK_MOUT_SCLK_MMC0_D 35 40#define CLK_MOUT_SCLK_MMC0_C 36 41#define CLK_MOUT_SCLK_MMC0_B 37 42#define CLK_MOUT_SCLK_MMC0_A 38 43#define CLK_MOUT_SCLK_SPI4 39 44#define CLK_MOUT_SCLK_SPI3 40 45#define CLK_MOUT_SCLK_UART2 41 46#define CLK_MOUT_SCLK_UART1 42 47#define CLK_MOUT_SCLK_UART0 43 48#define CLK_MOUT_SCLK_SPI2 44 49#define CLK_MOUT_SCLK_SPI1 45 50#define CLK_MOUT_SCLK_SPI0 46 51#define CLK_MOUT_ACLK_MFC_400_C 47 52#define CLK_MOUT_ACLK_MFC_400_B 48 53#define CLK_MOUT_ACLK_MFC_400_A 49 54#define CLK_MOUT_SCLK_ISP_SENSOR2 50 55#define CLK_MOUT_SCLK_ISP_SENSOR1 51 56#define CLK_MOUT_SCLK_ISP_SENSOR0 52 57#define CLK_MOUT_SCLK_ISP_UART 53 58#define CLK_MOUT_SCLK_ISP_SPI1 54 59#define CLK_MOUT_SCLK_ISP_SPI0 55 60#define CLK_MOUT_SCLK_PCIE_100 56 61#define CLK_MOUT_SCLK_UFSUNIPRO 57 62#define CLK_MOUT_SCLK_USBHOST30 58 63#define CLK_MOUT_SCLK_USBDRD30 59 64#define CLK_MOUT_SCLK_SLIMBUS 60 65#define CLK_MOUT_SCLK_SPDIF 61 66#define CLK_MOUT_SCLK_AUDIO1 62 67#define CLK_MOUT_SCLK_AUDIO0 63 68#define CLK_MOUT_SCLK_HDMI_SPDIF 64 69 70#define CLK_DIV_ACLK_FSYS_200 100 71#define CLK_DIV_ACLK_IMEM_SSSX_266 101 72#define CLK_DIV_ACLK_IMEM_200 102 73#define CLK_DIV_ACLK_IMEM_266 103 74#define CLK_DIV_ACLK_PERIC_66_B 104 75#define CLK_DIV_ACLK_PERIC_66_A 105 76#define CLK_DIV_ACLK_PERIS_66_B 106 77#define CLK_DIV_ACLK_PERIS_66_A 107 78#define CLK_DIV_SCLK_MMC1_B 108 79#define CLK_DIV_SCLK_MMC1_A 109 80#define CLK_DIV_SCLK_MMC0_B 110 81#define CLK_DIV_SCLK_MMC0_A 111 82#define CLK_DIV_SCLK_MMC2_B 112 83#define CLK_DIV_SCLK_MMC2_A 113 84#define CLK_DIV_SCLK_SPI1_B 114 85#define CLK_DIV_SCLK_SPI1_A 115 86#define CLK_DIV_SCLK_SPI0_B 116 87#define CLK_DIV_SCLK_SPI0_A 117 88#define CLK_DIV_SCLK_SPI2_B 118 89#define CLK_DIV_SCLK_SPI2_A 119 90#define CLK_DIV_SCLK_UART2 120 91#define CLK_DIV_SCLK_UART1 121 92#define CLK_DIV_SCLK_UART0 122 93#define CLK_DIV_SCLK_SPI4_B 123 94#define CLK_DIV_SCLK_SPI4_A 124 95#define CLK_DIV_SCLK_SPI3_B 125 96#define CLK_DIV_SCLK_SPI3_A 126 97#define CLK_DIV_SCLK_I2S1 127 98#define CLK_DIV_SCLK_PCM1 128 99#define CLK_DIV_SCLK_AUDIO1 129 100#define CLK_DIV_SCLK_AUDIO0 130 101#define CLK_DIV_ACLK_GSCL_111 131 102#define CLK_DIV_ACLK_GSCL_333 132 103#define CLK_DIV_ACLK_HEVC_400 133 104#define CLK_DIV_ACLK_MFC_400 134 105#define CLK_DIV_ACLK_G2D_266 135 106#define CLK_DIV_ACLK_G2D_400 136 107#define CLK_DIV_ACLK_G3D_400 137 108#define CLK_DIV_ACLK_BUS0_400 138 109#define CLK_DIV_ACLK_BUS1_400 139 110#define CLK_DIV_SCLK_PCIE_100 140 111#define CLK_DIV_SCLK_USBHOST30 141 112#define CLK_DIV_SCLK_UFSUNIPRO 142 113#define CLK_DIV_SCLK_USBDRD30 143 114#define CLK_DIV_SCLK_JPEG 144 115#define CLK_DIV_ACLK_MSCL_400 145 116#define CLK_DIV_ACLK_ISP_DIS_400 146 117#define CLK_DIV_ACLK_ISP_400 147 118#define CLK_DIV_ACLK_CAM0_333 148 119#define CLK_DIV_ACLK_CAM0_400 149 120#define CLK_DIV_ACLK_CAM0_552 150 121#define CLK_DIV_ACLK_CAM1_333 151 122#define CLK_DIV_ACLK_CAM1_400 152 123#define CLK_DIV_ACLK_CAM1_552 153 124#define CLK_DIV_SCLK_ISP_UART 154 125#define CLK_DIV_SCLK_ISP_SPI1_B 155 126#define CLK_DIV_SCLK_ISP_SPI1_A 156 127#define CLK_DIV_SCLK_ISP_SPI0_B 157 128#define CLK_DIV_SCLK_ISP_SPI0_A 158 129#define CLK_DIV_SCLK_ISP_SENSOR2_B 159 130#define CLK_DIV_SCLK_ISP_SENSOR2_A 160 131#define CLK_DIV_SCLK_ISP_SENSOR1_B 161 132#define CLK_DIV_SCLK_ISP_SENSOR1_A 162 133#define CLK_DIV_SCLK_ISP_SENSOR0_B 163 134#define CLK_DIV_SCLK_ISP_SENSOR0_A 164 135 136#define CLK_ACLK_PERIC_66 200 137#define CLK_ACLK_PERIS_66 201 138#define CLK_ACLK_FSYS_200 202 139#define CLK_SCLK_MMC2_FSYS 203 140#define CLK_SCLK_MMC1_FSYS 204 141#define CLK_SCLK_MMC0_FSYS 205 142#define CLK_SCLK_SPI4_PERIC 206 143#define CLK_SCLK_SPI3_PERIC 207 144#define CLK_SCLK_UART2_PERIC 208 145#define CLK_SCLK_UART1_PERIC 209 146#define CLK_SCLK_UART0_PERIC 210 147#define CLK_SCLK_SPI2_PERIC 211 148#define CLK_SCLK_SPI1_PERIC 212 149#define CLK_SCLK_SPI0_PERIC 213 150#define CLK_SCLK_SPDIF_PERIC 214 151#define CLK_SCLK_I2S1_PERIC 215 152#define CLK_SCLK_PCM1_PERIC 216 153#define CLK_SCLK_SLIMBUS 217 154#define CLK_SCLK_AUDIO1 218 155#define CLK_SCLK_AUDIO0 219 156#define CLK_ACLK_G2D_266 220 157#define CLK_ACLK_G2D_400 221 158#define CLK_ACLK_G3D_400 222 159#define CLK_ACLK_IMEM_SSSX_266 223 160#define CLK_ACLK_BUS0_400 224 161#define CLK_ACLK_BUS1_400 225 162#define CLK_ACLK_IMEM_200 226 163#define CLK_ACLK_IMEM_266 227 164#define CLK_SCLK_PCIE_100_FSYS 228 165#define CLK_SCLK_UFSUNIPRO_FSYS 229 166#define CLK_SCLK_USBHOST30_FSYS 230 167#define CLK_SCLK_USBDRD30_FSYS 231 168#define CLK_ACLK_GSCL_111 232 169#define CLK_ACLK_GSCL_333 233 170#define CLK_SCLK_JPEG_MSCL 234 171#define CLK_ACLK_MSCL_400 235 172#define CLK_ACLK_MFC_400 236 173#define CLK_ACLK_HEVC_400 237 174#define CLK_ACLK_ISP_DIS_400 238 175#define CLK_ACLK_ISP_400 239 176#define CLK_ACLK_CAM0_333 240 177#define CLK_ACLK_CAM0_400 241 178#define CLK_ACLK_CAM0_552 242 179#define CLK_ACLK_CAM1_333 243 180#define CLK_ACLK_CAM1_400 244 181#define CLK_ACLK_CAM1_552 245 182#define CLK_SCLK_ISP_SENSOR2 246 183#define CLK_SCLK_ISP_SENSOR1 247 184#define CLK_SCLK_ISP_SENSOR0 248 185#define CLK_SCLK_ISP_MCTADC_CAM1 249 186#define CLK_SCLK_ISP_UART_CAM1 250 187#define CLK_SCLK_ISP_SPI1_CAM1 251 188#define CLK_SCLK_ISP_SPI0_CAM1 252 189#define CLK_SCLK_HDMI_SPDIF_DISP 253 190 191#define TOP_NR_CLK 254 192 193/* CMU_CPIF */ 194#define CLK_FOUT_MPHY_PLL 1 195 196#define CLK_MOUT_MPHY_PLL 2 197 198#define CLK_DIV_SCLK_MPHY 10 199 200#define CLK_SCLK_MPHY_PLL 11 201#define CLK_SCLK_UFS_MPHY 11 202 203#define CPIF_NR_CLK 12 204 205/* CMU_MIF */ 206#define CLK_FOUT_MEM0_PLL 1 207#define CLK_FOUT_MEM1_PLL 2 208#define CLK_FOUT_BUS_PLL 3 209#define CLK_FOUT_MFC_PLL 4 210#define CLK_DOUT_MFC_PLL 5 211#define CLK_DOUT_BUS_PLL 6 212#define CLK_DOUT_MEM1_PLL 7 213#define CLK_DOUT_MEM0_PLL 8 214 215#define CLK_MOUT_MFC_PLL_DIV2 10 216#define CLK_MOUT_BUS_PLL_DIV2 11 217#define CLK_MOUT_MEM1_PLL_DIV2 12 218#define CLK_MOUT_MEM0_PLL_DIV2 13 219#define CLK_MOUT_MFC_PLL 14 220#define CLK_MOUT_BUS_PLL 15 221#define CLK_MOUT_MEM1_PLL 16 222#define CLK_MOUT_MEM0_PLL 17 223#define CLK_MOUT_CLK2X_PHY_C 18 224#define CLK_MOUT_CLK2X_PHY_B 19 225#define CLK_MOUT_CLK2X_PHY_A 20 226#define CLK_MOUT_CLKM_PHY_C 21 227#define CLK_MOUT_CLKM_PHY_B 22 228#define CLK_MOUT_CLKM_PHY_A 23 229#define CLK_MOUT_ACLK_MIFNM_200 24 230#define CLK_MOUT_ACLK_MIFNM_400 25 231#define CLK_MOUT_ACLK_DISP_333_B 26 232#define CLK_MOUT_ACLK_DISP_333_A 27 233#define CLK_MOUT_SCLK_DECON_VCLK_C 28 234#define CLK_MOUT_SCLK_DECON_VCLK_B 29 235#define CLK_MOUT_SCLK_DECON_VCLK_A 30 236#define CLK_MOUT_SCLK_DECON_ECLK_C 31 237#define CLK_MOUT_SCLK_DECON_ECLK_B 32 238#define CLK_MOUT_SCLK_DECON_ECLK_A 33 239#define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34 240#define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35 241#define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36 242#define CLK_MOUT_SCLK_DSD_C 37 243#define CLK_MOUT_SCLK_DSD_B 38 244#define CLK_MOUT_SCLK_DSD_A 39 245#define CLK_MOUT_SCLK_DSIM0_C 40 246#define CLK_MOUT_SCLK_DSIM0_B 41 247#define CLK_MOUT_SCLK_DSIM0_A 42 248#define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46 249#define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47 250#define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48 251#define CLK_MOUT_SCLK_DSIM1_C 49 252#define CLK_MOUT_SCLK_DSIM1_B 50 253#define CLK_MOUT_SCLK_DSIM1_A 51 254 255#define CLK_DIV_SCLK_HPM_MIF 55 256#define CLK_DIV_ACLK_DREX1 56 257#define CLK_DIV_ACLK_DREX0 57 258#define CLK_DIV_CLK2XPHY 58 259#define CLK_DIV_ACLK_MIF_266 59 260#define CLK_DIV_ACLK_MIFND_133 60 261#define CLK_DIV_ACLK_MIF_133 61 262#define CLK_DIV_ACLK_MIFNM_200 62 263#define CLK_DIV_ACLK_MIF_200 63 264#define CLK_DIV_ACLK_MIF_400 64 265#define CLK_DIV_ACLK_BUS2_400 65 266#define CLK_DIV_ACLK_DISP_333 66 267#define CLK_DIV_ACLK_CPIF_200 67 268#define CLK_DIV_SCLK_DSIM1 68 269#define CLK_DIV_SCLK_DECON_TV_VCLK 69 270#define CLK_DIV_SCLK_DSIM0 70 271#define CLK_DIV_SCLK_DSD 71 272#define CLK_DIV_SCLK_DECON_TV_ECLK 72 273#define CLK_DIV_SCLK_DECON_VCLK 73 274#define CLK_DIV_SCLK_DECON_ECLK 74 275#define CLK_DIV_MIF_PRE 75 276 277#define CLK_CLK2X_PHY1 80 278#define CLK_CLK2X_PHY0 81 279#define CLK_CLKM_PHY1 82 280#define CLK_CLKM_PHY0 83 281#define CLK_RCLK_DREX1 84 282#define CLK_RCLK_DREX0 85 283#define CLK_ACLK_DREX1_TZ 86 284#define CLK_ACLK_DREX0_TZ 87 285#define CLK_ACLK_DREX1_PEREV 88 286#define CLK_ACLK_DREX0_PEREV 89 287#define CLK_ACLK_DREX1_MEMIF 90 288#define CLK_ACLK_DREX0_MEMIF 91 289#define CLK_ACLK_DREX1_SCH 92 290#define CLK_ACLK_DREX0_SCH 93 291#define CLK_ACLK_DREX1_BUSIF 94 292#define CLK_ACLK_DREX0_BUSIF 95 293#define CLK_ACLK_DREX1_BUSIF_RD 96 294#define CLK_ACLK_DREX0_BUSIF_RD 97 295#define CLK_ACLK_DREX1 98 296#define CLK_ACLK_DREX0 99 297#define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100 298#define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101 299#define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102 300#define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103 301#define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104 302#define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105 303#define CLK_ACLK_ASYNCAXIS_CP1 106 304#define CLK_ACLK_ASYNCAXIM_CP1 107 305#define CLK_ACLK_ASYNCAXIS_CP0 108 306#define CLK_ACLK_ASYNCAXIM_CP0 109 307#define CLK_ACLK_ASYNCAXIS_DREX1_3 110 308#define CLK_ACLK_ASYNCAXIM_DREX1_3 111 309#define CLK_ACLK_ASYNCAXIS_DREX1_1 112 310#define CLK_ACLK_ASYNCAXIM_DREX1_1 113 311#define CLK_ACLK_ASYNCAXIS_DREX1_0 114 312#define CLK_ACLK_ASYNCAXIM_DREX1_0 115 313#define CLK_ACLK_ASYNCAXIS_DREX0_3 116 314#define CLK_ACLK_ASYNCAXIM_DREX0_3 117 315#define CLK_ACLK_ASYNCAXIS_DREX0_1 118 316#define CLK_ACLK_ASYNCAXIM_DREX0_1 119 317#define CLK_ACLK_ASYNCAXIS_DREX0_0 120 318#define CLK_ACLK_ASYNCAXIM_DREX0_0 121 319#define CLK_ACLK_AHB2APB_MIF2P 122 320#define CLK_ACLK_AHB2APB_MIF1P 123 321#define CLK_ACLK_AHB2APB_MIF0P 124 322#define CLK_ACLK_IXIU_CCI 125 323#define CLK_ACLK_XIU_MIFSFRX 126 324#define CLK_ACLK_MIFNP_133 127 325#define CLK_ACLK_MIFNM_200 128 326#define CLK_ACLK_MIFND_133 129 327#define CLK_ACLK_MIFND_400 130 328#define CLK_ACLK_CCI 131 329#define CLK_ACLK_MIFND_266 132 330#define CLK_ACLK_PPMU_DREX1S3 133 331#define CLK_ACLK_PPMU_DREX1S1 134 332#define CLK_ACLK_PPMU_DREX1S0 135 333#define CLK_ACLK_PPMU_DREX0S3 136 334#define CLK_ACLK_PPMU_DREX0S1 137 335#define CLK_ACLK_PPMU_DREX0S0 138 336#define CLK_ACLK_BTS_APOLLO 139 337#define CLK_ACLK_BTS_ATLAS 140 338#define CLK_ACLK_ACE_SEL_APOLL 141 339#define CLK_ACLK_ACE_SEL_ATLAS 142 340#define CLK_ACLK_AXIDS_CCI_MIFSFRX 143 341#define CLK_ACLK_AXIUS_ATLAS_CCI 144 342#define CLK_ACLK_AXISYNCDNS_CCI 145 343#define CLK_ACLK_AXISYNCDN_CCI 146 344#define CLK_ACLK_AXISYNCDN_NOC_D 147 345#define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148 346#define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149 347#define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150 348#define CLK_ACLK_BUS2_400 151 349#define CLK_ACLK_DISP_333 152 350#define CLK_ACLK_CPIF_200 153 351#define CLK_PCLK_PPMU_DREX1S3 154 352#define CLK_PCLK_PPMU_DREX1S1 155 353#define CLK_PCLK_PPMU_DREX1S0 156 354#define CLK_PCLK_PPMU_DREX0S3 157 355#define CLK_PCLK_PPMU_DREX0S1 158 356#define CLK_PCLK_PPMU_DREX0S0 159 357#define CLK_PCLK_BTS_APOLLO 160 358#define CLK_PCLK_BTS_ATLAS 161 359#define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162 360#define CLK_PCLK_ASYNCAXI_CP1 163 361#define CLK_PCLK_ASYNCAXI_CP0 164 362#define CLK_PCLK_ASYNCAXI_DREX1_3 165 363#define CLK_PCLK_ASYNCAXI_DREX1_1 166 364#define CLK_PCLK_ASYNCAXI_DREX1_0 167 365#define CLK_PCLK_ASYNCAXI_DREX0_3 168 366#define CLK_PCLK_ASYNCAXI_DREX0_1 169 367#define CLK_PCLK_ASYNCAXI_DREX0_0 170 368#define CLK_PCLK_MIFSRVND_133 171 369#define CLK_PCLK_PMU_MIF 172 370#define CLK_PCLK_SYSREG_MIF 173 371#define CLK_PCLK_GPIO_ALIVE 174 372#define CLK_PCLK_ABB 175 373#define CLK_PCLK_PMU_APBIF 176 374#define CLK_PCLK_DDR_PHY1 177 375#define CLK_PCLK_DREX1 178 376#define CLK_PCLK_DDR_PHY0 179 377#define CLK_PCLK_DREX0 180 378#define CLK_PCLK_DREX0_TZ 181 379#define CLK_PCLK_DREX1_TZ 182 380#define CLK_PCLK_MONOTONIC_CNT 183 381#define CLK_PCLK_RTC 184 382#define CLK_SCLK_DSIM1_DISP 185 383#define CLK_SCLK_DECON_TV_VCLK_DISP 186 384#define CLK_SCLK_FREQ_DET_BUS_PLL 187 385#define CLK_SCLK_FREQ_DET_MFC_PLL 188 386#define CLK_SCLK_FREQ_DET_MEM0_PLL 189 387#define CLK_SCLK_FREQ_DET_MEM1_PLL 190 388#define CLK_SCLK_DSIM0_DISP 191 389#define CLK_SCLK_DSD_DISP 192 390#define CLK_SCLK_DECON_TV_ECLK_DISP 193 391#define CLK_SCLK_DECON_VCLK_DISP 194 392#define CLK_SCLK_DECON_ECLK_DISP 195 393#define CLK_SCLK_HPM_MIF 196 394#define CLK_SCLK_MFC_PLL 197 395#define CLK_SCLK_BUS_PLL 198 396#define CLK_SCLK_BUS_PLL_APOLLO 199 397#define CLK_SCLK_BUS_PLL_ATLAS 200 398 399#define MIF_NR_CLK 201 400 401/* CMU_PERIC */ 402#define CLK_PCLK_SPI2 1 403#define CLK_PCLK_SPI1 2 404#define CLK_PCLK_SPI0 3 405#define CLK_PCLK_UART2 4 406#define CLK_PCLK_UART1 5 407#define CLK_PCLK_UART0 6 408#define CLK_PCLK_HSI2C3 7 409#define CLK_PCLK_HSI2C2 8 410#define CLK_PCLK_HSI2C1 9 411#define CLK_PCLK_HSI2C0 10 412#define CLK_PCLK_I2C7 11 413#define CLK_PCLK_I2C6 12 414#define CLK_PCLK_I2C5 13 415#define CLK_PCLK_I2C4 14 416#define CLK_PCLK_I2C3 15 417#define CLK_PCLK_I2C2 16 418#define CLK_PCLK_I2C1 17 419#define CLK_PCLK_I2C0 18 420#define CLK_PCLK_SPI4 19 421#define CLK_PCLK_SPI3 20 422#define CLK_PCLK_HSI2C11 21 423#define CLK_PCLK_HSI2C10 22 424#define CLK_PCLK_HSI2C9 23 425#define CLK_PCLK_HSI2C8 24 426#define CLK_PCLK_HSI2C7 25 427#define CLK_PCLK_HSI2C6 26 428#define CLK_PCLK_HSI2C5 27 429#define CLK_PCLK_HSI2C4 28 430#define CLK_SCLK_SPI4 29 431#define CLK_SCLK_SPI3 30 432#define CLK_SCLK_SPI2 31 433#define CLK_SCLK_SPI1 32 434#define CLK_SCLK_SPI0 33 435#define CLK_SCLK_UART2 34 436#define CLK_SCLK_UART1 35 437#define CLK_SCLK_UART0 36 438#define CLK_ACLK_AHB2APB_PERIC2P 37 439#define CLK_ACLK_AHB2APB_PERIC1P 38 440#define CLK_ACLK_AHB2APB_PERIC0P 39 441#define CLK_ACLK_PERICNP_66 40 442#define CLK_PCLK_SCI 41 443#define CLK_PCLK_GPIO_FINGER 42 444#define CLK_PCLK_GPIO_ESE 43 445#define CLK_PCLK_PWM 44 446#define CLK_PCLK_SPDIF 45 447#define CLK_PCLK_PCM1 46 448#define CLK_PCLK_I2S1 47 449#define CLK_PCLK_ADCIF 48 450#define CLK_PCLK_GPIO_TOUCH 49 451#define CLK_PCLK_GPIO_NFC 50 452#define CLK_PCLK_GPIO_PERIC 51 453#define CLK_PCLK_PMU_PERIC 52 454#define CLK_PCLK_SYSREG_PERIC 53 455#define CLK_SCLK_IOCLK_SPI4 54 456#define CLK_SCLK_IOCLK_SPI3 55 457#define CLK_SCLK_SCI 56 458#define CLK_SCLK_SC_IN 57 459#define CLK_SCLK_PWM 58 460#define CLK_SCLK_IOCLK_SPI2 59 461#define CLK_SCLK_IOCLK_SPI1 60 462#define CLK_SCLK_IOCLK_SPI0 61 463#define CLK_SCLK_IOCLK_I2S1_BCLK 62 464#define CLK_SCLK_SPDIF 63 465#define CLK_SCLK_PCM1 64 466#define CLK_SCLK_I2S1 65 467 468#define CLK_DIV_SCLK_SCI 70 469#define CLK_DIV_SCLK_SC_IN 71 470 471#define PERIC_NR_CLK 72 472 473/* CMU_PERIS */ 474#define CLK_PCLK_HPM_APBIF 1 475#define CLK_PCLK_TMU1_APBIF 2 476#define CLK_PCLK_TMU0_APBIF 3 477#define CLK_PCLK_PMU_PERIS 4 478#define CLK_PCLK_SYSREG_PERIS 5 479#define CLK_PCLK_CMU_TOP_APBIF 6 480#define CLK_PCLK_WDT_APOLLO 7 481#define CLK_PCLK_WDT_ATLAS 8 482#define CLK_PCLK_MCT 9 483#define CLK_PCLK_HDMI_CEC 10 484#define CLK_ACLK_AHB2APB_PERIS1P 11 485#define CLK_ACLK_AHB2APB_PERIS0P 12 486#define CLK_ACLK_PERISNP_66 13 487#define CLK_PCLK_TZPC12 14 488#define CLK_PCLK_TZPC11 15 489#define CLK_PCLK_TZPC10 16 490#define CLK_PCLK_TZPC9 17 491#define CLK_PCLK_TZPC8 18 492#define CLK_PCLK_TZPC7 19 493#define CLK_PCLK_TZPC6 20 494#define CLK_PCLK_TZPC5 21 495#define CLK_PCLK_TZPC4 22 496#define CLK_PCLK_TZPC3 23 497#define CLK_PCLK_TZPC2 24 498#define CLK_PCLK_TZPC1 25 499#define CLK_PCLK_TZPC0 26 500#define CLK_PCLK_SECKEY_APBIF 27 501#define CLK_PCLK_CHIPID_APBIF 28 502#define CLK_PCLK_TOPRTC 29 503#define CLK_PCLK_CUSTOM_EFUSE_APBIF 30 504#define CLK_PCLK_ANTIRBK_CNT_APBIF 31 505#define CLK_PCLK_OTP_CON_APBIF 32 506#define CLK_SCLK_ASV_TB 33 507#define CLK_SCLK_TMU1 34 508#define CLK_SCLK_TMU0 35 509#define CLK_SCLK_SECKEY 36 510#define CLK_SCLK_CHIPID 37 511#define CLK_SCLK_TOPRTC 38 512#define CLK_SCLK_CUSTOM_EFUSE 39 513#define CLK_SCLK_ANTIRBK_CNT 40 514#define CLK_SCLK_OTP_CON 41 515 516#define PERIS_NR_CLK 42 517 518/* CMU_FSYS */ 519#define CLK_MOUT_ACLK_FSYS_200_USER 1 520#define CLK_MOUT_SCLK_MMC2_USER 2 521#define CLK_MOUT_SCLK_MMC1_USER 3 522#define CLK_MOUT_SCLK_MMC0_USER 4 523#define CLK_MOUT_SCLK_UFS_MPHY_USER 5 524#define CLK_MOUT_SCLK_PCIE_100_USER 6 525#define CLK_MOUT_SCLK_UFSUNIPRO_USER 7 526#define CLK_MOUT_SCLK_USBHOST30_USER 8 527#define CLK_MOUT_SCLK_USBDRD30_USER 9 528#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER 10 529#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER 11 530#define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER 12 531#define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER 13 532#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER 14 533#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER 15 534#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER 16 535#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER 17 536#define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18 537#define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER 19 538#define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER 20 539#define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER 21 540#define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER 22 541#define CLK_MOUT_SCLK_MPHY 23 542 543#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY 25 544#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY 26 545#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY 27 546#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY 28 547#define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY 29 548#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY 30 549#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY 31 550#define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY 32 551#define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY 33 552#define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY 34 553#define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35 554#define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY 36 555#define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY 37 556 557#define CLK_ACLK_PCIE 50 558#define CLK_ACLK_PDMA1 51 559#define CLK_ACLK_TSI 52 560#define CLK_ACLK_MMC2 53 561#define CLK_ACLK_MMC1 54 562#define CLK_ACLK_MMC0 55 563#define CLK_ACLK_UFS 56 564#define CLK_ACLK_USBHOST20 57 565#define CLK_ACLK_USBHOST30 58 566#define CLK_ACLK_USBDRD30 59 567#define CLK_ACLK_PDMA0 60 568#define CLK_SCLK_MMC2 61 569#define CLK_SCLK_MMC1 62 570#define CLK_SCLK_MMC0 63 571#define CLK_PDMA1 64 572#define CLK_PDMA0 65 573#define CLK_ACLK_XIU_FSYSPX 66 574#define CLK_ACLK_AHB_USBLINKH1 67 575#define CLK_ACLK_SMMU_PDMA1 68 576#define CLK_ACLK_BTS_PCIE 69 577#define CLK_ACLK_AXIUS_PDMA1 70 578#define CLK_ACLK_SMMU_PDMA0 71 579#define CLK_ACLK_BTS_UFS 72 580#define CLK_ACLK_BTS_USBHOST30 73 581#define CLK_ACLK_BTS_USBDRD30 74 582#define CLK_ACLK_AXIUS_PDMA0 75 583#define CLK_ACLK_AXIUS_USBHS 76 584#define CLK_ACLK_AXIUS_FSYSSX 77 585#define CLK_ACLK_AHB2APB_FSYSP 78 586#define CLK_ACLK_AHB2AXI_USBHS 79 587#define CLK_ACLK_AHB_USBLINKH0 80 588#define CLK_ACLK_AHB_USBHS 81 589#define CLK_ACLK_AHB_FSYSH 82 590#define CLK_ACLK_XIU_FSYSX 83 591#define CLK_ACLK_XIU_FSYSSX 84 592#define CLK_ACLK_FSYSNP_200 85 593#define CLK_ACLK_FSYSND_200 86 594#define CLK_PCLK_PCIE_CTRL 87 595#define CLK_PCLK_SMMU_PDMA1 88 596#define CLK_PCLK_PCIE_PHY 89 597#define CLK_PCLK_BTS_PCIE 90 598#define CLK_PCLK_SMMU_PDMA0 91 599#define CLK_PCLK_BTS_UFS 92 600#define CLK_PCLK_BTS_USBHOST30 93 601#define CLK_PCLK_BTS_USBDRD30 94 602#define CLK_PCLK_GPIO_FSYS 95 603#define CLK_PCLK_PMU_FSYS 96 604#define CLK_PCLK_SYSREG_FSYS 97 605#define CLK_SCLK_PCIE_100 98 606#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK 99 607#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK 100 608#define CLK_PHYCLK_UFS_RX1_SYMBOL 101 609#define CLK_PHYCLK_UFS_RX0_SYMBOL 102 610#define CLK_PHYCLK_UFS_TX1_SYMBOL 103 611#define CLK_PHYCLK_UFS_TX0_SYMBOL 104 612#define CLK_PHYCLK_USBHOST20_PHY_HSIC1 105 613#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI 106 614#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK 107 615#define CLK_PHYCLK_USBHOST20_PHY_FREECLK 108 616#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 109 617#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK 110 618#define CLK_SCLK_MPHY 111 619#define CLK_SCLK_UFSUNIPRO 112 620#define CLK_SCLK_USBHOST30 113 621#define CLK_SCLK_USBDRD30 114 622#define CLK_PCIE 115 623 624#define FSYS_NR_CLK 116 625 626/* CMU_G2D */ 627#define CLK_MUX_ACLK_G2D_266_USER 1 628#define CLK_MUX_ACLK_G2D_400_USER 2 629 630#define CLK_DIV_PCLK_G2D 3 631 632#define CLK_ACLK_SMMU_MDMA1 4 633#define CLK_ACLK_BTS_MDMA1 5 634#define CLK_ACLK_BTS_G2D 6 635#define CLK_ACLK_ALB_G2D 7 636#define CLK_ACLK_AXIUS_G2DX 8 637#define CLK_ACLK_ASYNCAXI_SYSX 9 638#define CLK_ACLK_AHB2APB_G2D1P 10 639#define CLK_ACLK_AHB2APB_G2D0P 11 640#define CLK_ACLK_XIU_G2DX 12 641#define CLK_ACLK_G2DNP_133 13 642#define CLK_ACLK_G2DND_400 14 643#define CLK_ACLK_MDMA1 15 644#define CLK_ACLK_G2D 16 645#define CLK_ACLK_SMMU_G2D 17 646#define CLK_PCLK_SMMU_MDMA1 18 647#define CLK_PCLK_BTS_MDMA1 19 648#define CLK_PCLK_BTS_G2D 20 649#define CLK_PCLK_ALB_G2D 21 650#define CLK_PCLK_ASYNCAXI_SYSX 22 651#define CLK_PCLK_PMU_G2D 23 652#define CLK_PCLK_SYSREG_G2D 24 653#define CLK_PCLK_G2D 25 654#define CLK_PCLK_SMMU_G2D 26 655 656#define G2D_NR_CLK 27 657 658/* CMU_DISP */ 659#define CLK_FOUT_DISP_PLL 1 660 661#define CLK_MOUT_DISP_PLL 2 662#define CLK_MOUT_SCLK_DSIM1_USER 3 663#define CLK_MOUT_SCLK_DSIM0_USER 4 664#define CLK_MOUT_SCLK_DSD_USER 5 665#define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6 666#define CLK_MOUT_SCLK_DECON_VCLK_USER 7 667#define CLK_MOUT_SCLK_DECON_ECLK_USER 8 668#define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9 669#define CLK_MOUT_ACLK_DISP_333_USER 10 670#define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11 671#define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12 672#define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13 673#define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14 674#define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15 675#define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16 676#define CLK_MOUT_SCLK_DSIM0 17 677#define CLK_MOUT_SCLK_DECON_TV_ECLK 18 678#define CLK_MOUT_SCLK_DECON_VCLK 19 679#define CLK_MOUT_SCLK_DECON_ECLK 20 680#define CLK_MOUT_SCLK_DSIM1_B_DISP 21 681#define CLK_MOUT_SCLK_DSIM1_A_DISP 22 682#define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23 683#define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24 684#define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25 685 686#define CLK_DIV_SCLK_DSIM1_DISP 30 687#define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31 688#define CLK_DIV_SCLK_DSIM0_DISP 32 689#define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33 690#define CLK_DIV_SCLK_DECON_VCLK_DISP 34 691#define CLK_DIV_SCLK_DECON_ECLK_DISP 35 692#define CLK_DIV_PCLK_DISP 36 693 694#define CLK_ACLK_DECON_TV 40 695#define CLK_ACLK_DECON 41 696#define CLK_ACLK_SMMU_TV1X 42 697#define CLK_ACLK_SMMU_TV0X 43 698#define CLK_ACLK_SMMU_DECON1X 44 699#define CLK_ACLK_SMMU_DECON0X 45 700#define CLK_ACLK_BTS_DECON_TV_M3 46 701#define CLK_ACLK_BTS_DECON_TV_M2 47 702#define CLK_ACLK_BTS_DECON_TV_M1 48 703#define CLK_ACLK_BTS_DECON_TV_M0 49 704#define CLK_ACLK_BTS_DECON_NM4 50 705#define CLK_ACLK_BTS_DECON_NM3 51 706#define CLK_ACLK_BTS_DECON_NM2 52 707#define CLK_ACLK_BTS_DECON_NM1 53 708#define CLK_ACLK_BTS_DECON_NM0 54 709#define CLK_ACLK_AHB2APB_DISPSFR2P 55 710#define CLK_ACLK_AHB2APB_DISPSFR1P 56 711#define CLK_ACLK_AHB2APB_DISPSFR0P 57 712#define CLK_ACLK_AHB_DISPH 58 713#define CLK_ACLK_XIU_TV1X 59 714#define CLK_ACLK_XIU_TV0X 60 715#define CLK_ACLK_XIU_DECON1X 61 716#define CLK_ACLK_XIU_DECON0X 62 717#define CLK_ACLK_XIU_DISP1X 63 718#define CLK_ACLK_XIU_DISPNP_100 64 719#define CLK_ACLK_DISP1ND_333 65 720#define CLK_ACLK_DISP0ND_333 66 721#define CLK_PCLK_SMMU_TV1X 67 722#define CLK_PCLK_SMMU_TV0X 68 723#define CLK_PCLK_SMMU_DECON1X 69 724#define CLK_PCLK_SMMU_DECON0X 70 725#define CLK_PCLK_BTS_DECON_TV_M3 71 726#define CLK_PCLK_BTS_DECON_TV_M2 72 727#define CLK_PCLK_BTS_DECON_TV_M1 73 728#define CLK_PCLK_BTS_DECON_TV_M0 74 729#define CLK_PCLK_BTS_DECONM4 75 730#define CLK_PCLK_BTS_DECONM3 76 731#define CLK_PCLK_BTS_DECONM2 77 732#define CLK_PCLK_BTS_DECONM1 78 733#define CLK_PCLK_BTS_DECONM0 79 734#define CLK_PCLK_MIC1 80 735#define CLK_PCLK_PMU_DISP 81 736#define CLK_PCLK_SYSREG_DISP 82 737#define CLK_PCLK_HDMIPHY 83 738#define CLK_PCLK_HDMI 84 739#define CLK_PCLK_MIC0 85 740#define CLK_PCLK_DSIM1 86 741#define CLK_PCLK_DSIM0 87 742#define CLK_PCLK_DECON_TV 88 743#define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89 744#define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90 745#define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91 746#define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92 747#define CLK_SCLK_DSIM1 93 748#define CLK_SCLK_DECON_TV_VCLK 94 749#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95 750#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96 751#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97 752#define CLK_PHYCLK_HDMI_PIXEL 98 753#define CLK_SCLK_RGB_VCLK_TO_SMIES 99 754#define CLK_SCLK_FREQ_DET_DISP_PLL 100 755#define CLK_SCLK_RGB_VCLK_TO_DSIM0 101 756#define CLK_SCLK_RGB_VCLK_TO_MIC0 102 757#define CLK_SCLK_DSD 103 758#define CLK_SCLK_HDMI_SPDIF 104 759#define CLK_SCLK_DSIM0 105 760#define CLK_SCLK_DECON_TV_ECLK 106 761#define CLK_SCLK_DECON_VCLK 107 762#define CLK_SCLK_DECON_ECLK 108 763#define CLK_SCLK_RGB_VCLK 109 764#define CLK_SCLK_RGB_TV_VCLK 110 765 766#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY 111 767#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY 112 768 769#define CLK_PCLK_DECON 113 770 771#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114 772#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115 773 774#define DISP_NR_CLK 116 775 776/* CMU_AUD */ 777#define CLK_MOUT_AUD_PLL_USER 1 778#define CLK_MOUT_SCLK_AUD_PCM 2 779#define CLK_MOUT_SCLK_AUD_I2S 3 780 781#define CLK_DIV_ATCLK_AUD 4 782#define CLK_DIV_PCLK_DBG_AUD 5 783#define CLK_DIV_ACLK_AUD 6 784#define CLK_DIV_AUD_CA5 7 785#define CLK_DIV_SCLK_AUD_SLIMBUS 8 786#define CLK_DIV_SCLK_AUD_UART 9 787#define CLK_DIV_SCLK_AUD_PCM 10 788#define CLK_DIV_SCLK_AUD_I2S 11 789 790#define CLK_ACLK_INTR_CTRL 12 791#define CLK_ACLK_AXIDS2_LPASSP 13 792#define CLK_ACLK_AXIDS1_LPASSP 14 793#define CLK_ACLK_AXI2APB1_LPASSP 15 794#define CLK_ACLK_AXI2APH_LPASSP 16 795#define CLK_ACLK_SMMU_LPASSX 17 796#define CLK_ACLK_AXIDS0_LPASSP 18 797#define CLK_ACLK_AXI2APB0_LPASSP 19 798#define CLK_ACLK_XIU_LPASSX 20 799#define CLK_ACLK_AUDNP_133 21 800#define CLK_ACLK_AUDND_133 22 801#define CLK_ACLK_SRAMC 23 802#define CLK_ACLK_DMAC 24 803#define CLK_PCLK_WDT1 25 804#define CLK_PCLK_WDT0 26 805#define CLK_PCLK_SFR1 27 806#define CLK_PCLK_SMMU_LPASSX 28 807#define CLK_PCLK_GPIO_AUD 29 808#define CLK_PCLK_PMU_AUD 30 809#define CLK_PCLK_SYSREG_AUD 31 810#define CLK_PCLK_AUD_SLIMBUS 32 811#define CLK_PCLK_AUD_UART 33 812#define CLK_PCLK_AUD_PCM 34 813#define CLK_PCLK_AUD_I2S 35 814#define CLK_PCLK_TIMER 36 815#define CLK_PCLK_SFR0_CTRL 37 816#define CLK_ATCLK_AUD 38 817#define CLK_PCLK_DBG_AUD 39 818#define CLK_SCLK_AUD_CA5 40 819#define CLK_SCLK_JTAG_TCK 41 820#define CLK_SCLK_SLIMBUS_CLKIN 42 821#define CLK_SCLK_AUD_SLIMBUS 43 822#define CLK_SCLK_AUD_UART 44 823#define CLK_SCLK_AUD_PCM 45 824#define CLK_SCLK_I2S_BCLK 46 825#define CLK_SCLK_AUD_I2S 47 826 827#define AUD_NR_CLK 48 828 829/* CMU_BUS{0|1|2} */ 830#define CLK_DIV_PCLK_BUS_133 1 831 832#define CLK_ACLK_AHB2APB_BUSP 2 833#define CLK_ACLK_BUSNP_133 3 834#define CLK_ACLK_BUSND_400 4 835#define CLK_PCLK_BUSSRVND_133 5 836#define CLK_PCLK_PMU_BUS 6 837#define CLK_PCLK_SYSREG_BUS 7 838 839#define CLK_MOUT_ACLK_BUS2_400_USER 8 /* Only CMU_BUS2 */ 840#define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */ 841#define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */ 842 843#define BUSx_NR_CLK 11 844 845/* CMU_G3D */ 846#define CLK_FOUT_G3D_PLL 1 847 848#define CLK_MOUT_ACLK_G3D_400 2 849#define CLK_MOUT_G3D_PLL 3 850 851#define CLK_DIV_SCLK_HPM_G3D 4 852#define CLK_DIV_PCLK_G3D 5 853#define CLK_DIV_ACLK_G3D 6 854#define CLK_ACLK_BTS_G3D1 7 855#define CLK_ACLK_BTS_G3D0 8 856#define CLK_ACLK_ASYNCAPBS_G3D 9 857#define CLK_ACLK_ASYNCAPBM_G3D 10 858#define CLK_ACLK_AHB2APB_G3DP 11 859#define CLK_ACLK_G3DNP_150 12 860#define CLK_ACLK_G3DND_600 13 861#define CLK_ACLK_G3D 14 862#define CLK_PCLK_BTS_G3D1 15 863#define CLK_PCLK_BTS_G3D0 16 864#define CLK_PCLK_PMU_G3D 17 865#define CLK_PCLK_SYSREG_G3D 18 866#define CLK_SCLK_HPM_G3D 19 867 868#define G3D_NR_CLK 20 869 870/* CMU_GSCL */ 871#define CLK_MOUT_ACLK_GSCL_111_USER 1 872#define CLK_MOUT_ACLK_GSCL_333_USER 2 873 874#define CLK_ACLK_BTS_GSCL2 3 875#define CLK_ACLK_BTS_GSCL1 4 876#define CLK_ACLK_BTS_GSCL0 5 877#define CLK_ACLK_AHB2APB_GSCLP 6 878#define CLK_ACLK_XIU_GSCLX 7 879#define CLK_ACLK_GSCLNP_111 8 880#define CLK_ACLK_GSCLRTND_333 9 881#define CLK_ACLK_GSCLBEND_333 10 882#define CLK_ACLK_GSD 11 883#define CLK_ACLK_GSCL2 12 884#define CLK_ACLK_GSCL1 13 885#define CLK_ACLK_GSCL0 14 886#define CLK_ACLK_SMMU_GSCL0 15 887#define CLK_ACLK_SMMU_GSCL1 16 888#define CLK_ACLK_SMMU_GSCL2 17 889#define CLK_PCLK_BTS_GSCL2 18 890#define CLK_PCLK_BTS_GSCL1 19 891#define CLK_PCLK_BTS_GSCL0 20 892#define CLK_PCLK_PMU_GSCL 21 893#define CLK_PCLK_SYSREG_GSCL 22 894#define CLK_PCLK_GSCL2 23 895#define CLK_PCLK_GSCL1 24 896#define CLK_PCLK_GSCL0 25 897#define CLK_PCLK_SMMU_GSCL0 26 898#define CLK_PCLK_SMMU_GSCL1 27 899#define CLK_PCLK_SMMU_GSCL2 28 900 901#define GSCL_NR_CLK 29 902 903/* CMU_APOLLO */ 904#define CLK_FOUT_APOLLO_PLL 1 905 906#define CLK_MOUT_APOLLO_PLL 2 907#define CLK_MOUT_BUS_PLL_APOLLO_USER 3 908#define CLK_MOUT_APOLLO 4 909 910#define CLK_DIV_CNTCLK_APOLLO 5 911#define CLK_DIV_PCLK_DBG_APOLLO 6 912#define CLK_DIV_ATCLK_APOLLO 7 913#define CLK_DIV_PCLK_APOLLO 8 914#define CLK_DIV_ACLK_APOLLO 9 915#define CLK_DIV_APOLLO2 10 916#define CLK_DIV_APOLLO1 11 917#define CLK_DIV_SCLK_HPM_APOLLO 12 918#define CLK_DIV_APOLLO_PLL 13 919 920#define CLK_ACLK_ATBDS_APOLLO_3 14 921#define CLK_ACLK_ATBDS_APOLLO_2 15 922#define CLK_ACLK_ATBDS_APOLLO_1 16 923#define CLK_ACLK_ATBDS_APOLLO_0 17 924#define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS 18 925#define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS 19 926#define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS 20 927#define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS 21 928#define CLK_ACLK_ASYNCACES_APOLLO_CCI 22 929#define CLK_ACLK_AHB2APB_APOLLOP 23 930#define CLK_ACLK_APOLLONP_200 24 931#define CLK_PCLK_ASAPBMST_CSSYS_APOLLO 25 932#define CLK_PCLK_PMU_APOLLO 26 933#define CLK_PCLK_SYSREG_APOLLO 27 934#define CLK_CNTCLK_APOLLO 28 935#define CLK_SCLK_HPM_APOLLO 29 936#define CLK_SCLK_APOLLO 30 937 938#define APOLLO_NR_CLK 31 939 940/* CMU_ATLAS */ 941#define CLK_FOUT_ATLAS_PLL 1 942 943#define CLK_MOUT_ATLAS_PLL 2 944#define CLK_MOUT_BUS_PLL_ATLAS_USER 3 945#define CLK_MOUT_ATLAS 4 946 947#define CLK_DIV_CNTCLK_ATLAS 5 948#define CLK_DIV_PCLK_DBG_ATLAS 6 949#define CLK_DIV_ATCLK_ATLASO 7 950#define CLK_DIV_PCLK_ATLAS 8 951#define CLK_DIV_ACLK_ATLAS 9 952#define CLK_DIV_ATLAS2 10 953#define CLK_DIV_ATLAS1 11 954#define CLK_DIV_SCLK_HPM_ATLAS 12 955#define CLK_DIV_ATLAS_PLL 13 956 957#define CLK_ACLK_ATB_AUD_CSSYS 14 958#define CLK_ACLK_ATB_APOLLO3_CSSYS 15 959#define CLK_ACLK_ATB_APOLLO2_CSSYS 16 960#define CLK_ACLK_ATB_APOLLO1_CSSYS 17 961#define CLK_ACLK_ATB_APOLLO0_CSSYS 18 962#define CLK_ACLK_ASYNCAHBS_CSSYS_SSS 19 963#define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX 20 964#define CLK_ACLK_ASYNCACES_ATLAS_CCI 21 965#define CLK_ACLK_AHB2APB_ATLASP 22 966#define CLK_ACLK_ATLASNP_200 23 967#define CLK_PCLK_ASYNCAPB_AUD_CSSYS 24 968#define CLK_PCLK_ASYNCAPB_ISP_CSSYS 25 969#define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS 26 970#define CLK_PCLK_PMU_ATLAS 27 971#define CLK_PCLK_SYSREG_ATLAS 28 972#define CLK_PCLK_SECJTAG 29 973#define CLK_CNTCLK_ATLAS 30 974#define CLK_SCLK_FREQ_DET_ATLAS_PLL 31 975#define CLK_SCLK_HPM_ATLAS 32 976#define CLK_TRACECLK 33 977#define CLK_CTMCLK 34 978#define CLK_HCLK_CSSYS 35 979#define CLK_PCLK_DBG_CSSYS 36 980#define CLK_PCLK_DBG 37 981#define CLK_ATCLK 38 982#define CLK_SCLK_ATLAS 39 983 984#define ATLAS_NR_CLK 40 985 986/* CMU_MSCL */ 987#define CLK_MOUT_SCLK_JPEG_USER 1 988#define CLK_MOUT_ACLK_MSCL_400_USER 2 989#define CLK_MOUT_SCLK_JPEG 3 990 991#define CLK_DIV_PCLK_MSCL 4 992 993#define CLK_ACLK_BTS_JPEG 5 994#define CLK_ACLK_BTS_M2MSCALER1 6 995#define CLK_ACLK_BTS_M2MSCALER0 7 996#define CLK_ACLK_AHB2APB_MSCL0P 8 997#define CLK_ACLK_XIU_MSCLX 9 998#define CLK_ACLK_MSCLNP_100 10 999#define CLK_ACLK_MSCLND_400 11 1000#define CLK_ACLK_JPEG 12 1001#define CLK_ACLK_M2MSCALER1 13 1002#define CLK_ACLK_M2MSCALER0 14 1003#define CLK_ACLK_SMMU_M2MSCALER0 15 1004#define CLK_ACLK_SMMU_M2MSCALER1 16 1005#define CLK_ACLK_SMMU_JPEG 17 1006#define CLK_PCLK_BTS_JPEG 18 1007#define CLK_PCLK_BTS_M2MSCALER1 19 1008#define CLK_PCLK_BTS_M2MSCALER0 20 1009#define CLK_PCLK_PMU_MSCL 21 1010#define CLK_PCLK_SYSREG_MSCL 22 1011#define CLK_PCLK_JPEG 23 1012#define CLK_PCLK_M2MSCALER1 24 1013#define CLK_PCLK_M2MSCALER0 25 1014#define CLK_PCLK_SMMU_M2MSCALER0 26 1015#define CLK_PCLK_SMMU_M2MSCALER1 27 1016#define CLK_PCLK_SMMU_JPEG 28 1017#define CLK_SCLK_JPEG 29 1018 1019#define MSCL_NR_CLK 30 1020 1021/* CMU_MFC */ 1022#define CLK_MOUT_ACLK_MFC_400_USER 1 1023 1024#define CLK_DIV_PCLK_MFC 2 1025 1026#define CLK_ACLK_BTS_MFC_1 3 1027#define CLK_ACLK_BTS_MFC_0 4 1028#define CLK_ACLK_AHB2APB_MFCP 5 1029#define CLK_ACLK_XIU_MFCX 6 1030#define CLK_ACLK_MFCNP_100 7 1031#define CLK_ACLK_MFCND_400 8 1032#define CLK_ACLK_MFC 9 1033#define CLK_ACLK_SMMU_MFC_1 10 1034#define CLK_ACLK_SMMU_MFC_0 11 1035#define CLK_PCLK_BTS_MFC_1 12 1036#define CLK_PCLK_BTS_MFC_0 13 1037#define CLK_PCLK_PMU_MFC 14 1038#define CLK_PCLK_SYSREG_MFC 15 1039#define CLK_PCLK_MFC 16 1040#define CLK_PCLK_SMMU_MFC_1 17 1041#define CLK_PCLK_SMMU_MFC_0 18 1042 1043#define MFC_NR_CLK 19 1044 1045/* CMU_HEVC */ 1046#define CLK_MOUT_ACLK_HEVC_400_USER 1 1047 1048#define CLK_DIV_PCLK_HEVC 2 1049 1050#define CLK_ACLK_BTS_HEVC_1 3 1051#define CLK_ACLK_BTS_HEVC_0 4 1052#define CLK_ACLK_AHB2APB_HEVCP 5 1053#define CLK_ACLK_XIU_HEVCX 6 1054#define CLK_ACLK_HEVCNP_100 7 1055#define CLK_ACLK_HEVCND_400 8 1056#define CLK_ACLK_HEVC 9 1057#define CLK_ACLK_SMMU_HEVC_1 10 1058#define CLK_ACLK_SMMU_HEVC_0 11 1059#define CLK_PCLK_BTS_HEVC_1 12 1060#define CLK_PCLK_BTS_HEVC_0 13 1061#define CLK_PCLK_PMU_HEVC 14 1062#define CLK_PCLK_SYSREG_HEVC 15 1063#define CLK_PCLK_HEVC 16 1064#define CLK_PCLK_SMMU_HEVC_1 17 1065#define CLK_PCLK_SMMU_HEVC_0 18 1066 1067#define HEVC_NR_CLK 19 1068 1069/* CMU_ISP */ 1070#define CLK_MOUT_ACLK_ISP_DIS_400_USER 1 1071#define CLK_MOUT_ACLK_ISP_400_USER 2 1072 1073#define CLK_DIV_PCLK_ISP_DIS 3 1074#define CLK_DIV_PCLK_ISP 4 1075#define CLK_DIV_ACLK_ISP_D_200 5 1076#define CLK_DIV_ACLK_ISP_C_200 6 1077 1078#define CLK_ACLK_ISP_D_GLUE 7 1079#define CLK_ACLK_SCALERP 8 1080#define CLK_ACLK_3DNR 9 1081#define CLK_ACLK_DIS 10 1082#define CLK_ACLK_SCALERC 11 1083#define CLK_ACLK_DRC 12 1084#define CLK_ACLK_ISP 13 1085#define CLK_ACLK_AXIUS_SCALERP 14 1086#define CLK_ACLK_AXIUS_SCALERC 15 1087#define CLK_ACLK_AXIUS_DRC 16 1088#define CLK_ACLK_ASYNCAHBM_ISP2P 17 1089#define CLK_ACLK_ASYNCAHBM_ISP1P 18 1090#define CLK_ACLK_ASYNCAXIS_DIS1 19 1091#define CLK_ACLK_ASYNCAXIS_DIS0 20 1092#define CLK_ACLK_ASYNCAXIM_DIS1 21 1093#define CLK_ACLK_ASYNCAXIM_DIS0 22 1094#define CLK_ACLK_ASYNCAXIM_ISP2P 23 1095#define CLK_ACLK_ASYNCAXIM_ISP1P 24 1096#define CLK_ACLK_AHB2APB_ISP2P 25 1097#define CLK_ACLK_AHB2APB_ISP1P 26 1098#define CLK_ACLK_AXI2APB_ISP2P 27 1099#define CLK_ACLK_AXI2APB_ISP1P 28 1100#define CLK_ACLK_XIU_ISPEX1 29 1101#define CLK_ACLK_XIU_ISPEX0 30 1102#define CLK_ACLK_ISPND_400 31 1103#define CLK_ACLK_SMMU_SCALERP 32 1104#define CLK_ACLK_SMMU_3DNR 33 1105#define CLK_ACLK_SMMU_DIS1 34 1106#define CLK_ACLK_SMMU_DIS0 35 1107#define CLK_ACLK_SMMU_SCALERC 36 1108#define CLK_ACLK_SMMU_DRC 37 1109#define CLK_ACLK_SMMU_ISP 38 1110#define CLK_ACLK_BTS_SCALERP 39 1111#define CLK_ACLK_BTS_3DR 40 1112#define CLK_ACLK_BTS_DIS1 41 1113#define CLK_ACLK_BTS_DIS0 42 1114#define CLK_ACLK_BTS_SCALERC 43 1115#define CLK_ACLK_BTS_DRC 44 1116#define CLK_ACLK_BTS_ISP 45 1117#define CLK_PCLK_SMMU_SCALERP 46 1118#define CLK_PCLK_SMMU_3DNR 47 1119#define CLK_PCLK_SMMU_DIS1 48 1120#define CLK_PCLK_SMMU_DIS0 49 1121#define CLK_PCLK_SMMU_SCALERC 50 1122#define CLK_PCLK_SMMU_DRC 51 1123#define CLK_PCLK_SMMU_ISP 52 1124#define CLK_PCLK_BTS_SCALERP 53 1125#define CLK_PCLK_BTS_3DNR 54 1126#define CLK_PCLK_BTS_DIS1 55 1127#define CLK_PCLK_BTS_DIS0 56 1128#define CLK_PCLK_BTS_SCALERC 57 1129#define CLK_PCLK_BTS_DRC 58 1130#define CLK_PCLK_BTS_ISP 59 1131#define CLK_PCLK_ASYNCAXI_DIS1 60 1132#define CLK_PCLK_ASYNCAXI_DIS0 61 1133#define CLK_PCLK_PMU_ISP 62 1134#define CLK_PCLK_SYSREG_ISP 63 1135#define CLK_PCLK_CMU_ISP_LOCAL 64 1136#define CLK_PCLK_SCALERP 65 1137#define CLK_PCLK_3DNR 66 1138#define CLK_PCLK_DIS_CORE 67 1139#define CLK_PCLK_DIS 68 1140#define CLK_PCLK_SCALERC 69 1141#define CLK_PCLK_DRC 70 1142#define CLK_PCLK_ISP 71 1143#define CLK_SCLK_PIXELASYNCS_DIS 72 1144#define CLK_SCLK_PIXELASYNCM_DIS 73 1145#define CLK_SCLK_PIXELASYNCS_SCALERP 74 1146#define CLK_SCLK_PIXELASYNCM_ISPD 75 1147#define CLK_SCLK_PIXELASYNCS_ISPC 76 1148#define CLK_SCLK_PIXELASYNCM_ISPC 77 1149 1150#define ISP_NR_CLK 78 1151 1152/* CMU_CAM0 */ 1153#define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY 1 1154#define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY 2 1155 1156#define CLK_MOUT_ACLK_CAM0_333_USER 3 1157#define CLK_MOUT_ACLK_CAM0_400_USER 4 1158#define CLK_MOUT_ACLK_CAM0_552_USER 5 1159#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER 6 1160#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER 7 1161#define CLK_MOUT_ACLK_LITE_D_B 8 1162#define CLK_MOUT_ACLK_LITE_D_A 9 1163#define CLK_MOUT_ACLK_LITE_B_B 10 1164#define CLK_MOUT_ACLK_LITE_B_A 11 1165#define CLK_MOUT_ACLK_LITE_A_B 12 1166#define CLK_MOUT_ACLK_LITE_A_A 13 1167#define CLK_MOUT_ACLK_CAM0_400 14 1168#define CLK_MOUT_ACLK_CSIS1_B 15 1169#define CLK_MOUT_ACLK_CSIS1_A 16 1170#define CLK_MOUT_ACLK_CSIS0_B 17 1171#define CLK_MOUT_ACLK_CSIS0_A 18 1172#define CLK_MOUT_ACLK_3AA1_B 19 1173#define CLK_MOUT_ACLK_3AA1_A 20 1174#define CLK_MOUT_ACLK_3AA0_B 21 1175#define CLK_MOUT_ACLK_3AA0_A 22 1176#define CLK_MOUT_SCLK_LITE_FREECNT_C 23 1177#define CLK_MOUT_SCLK_LITE_FREECNT_B 24 1178#define CLK_MOUT_SCLK_LITE_FREECNT_A 25 1179#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B 26 1180#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A 27 1181#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B 28 1182#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A 29 1183 1184#define CLK_DIV_PCLK_CAM0_50 30 1185#define CLK_DIV_ACLK_CAM0_200 31 1186#define CLK_DIV_ACLK_CAM0_BUS_400 32 1187#define CLK_DIV_PCLK_LITE_D 33 1188#define CLK_DIV_ACLK_LITE_D 34 1189#define CLK_DIV_PCLK_LITE_B 35 1190#define CLK_DIV_ACLK_LITE_B 36 1191#define CLK_DIV_PCLK_LITE_A 37 1192#define CLK_DIV_ACLK_LITE_A 38 1193#define CLK_DIV_ACLK_CSIS1 39 1194#define CLK_DIV_ACLK_CSIS0 40 1195#define CLK_DIV_PCLK_3AA1 41 1196#define CLK_DIV_ACLK_3AA1 42 1197#define CLK_DIV_PCLK_3AA0 43 1198#define CLK_DIV_ACLK_3AA0 44 1199#define CLK_DIV_SCLK_PIXELASYNC_LITE_C 45 1200#define CLK_DIV_PCLK_PIXELASYNC_LITE_C 46 1201#define CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT 47 1202 1203#define CLK_ACLK_CSIS1 50 1204#define CLK_ACLK_CSIS0 51 1205#define CLK_ACLK_3AA1 52 1206#define CLK_ACLK_3AA0 53 1207#define CLK_ACLK_LITE_D 54 1208#define CLK_ACLK_LITE_B 55 1209#define CLK_ACLK_LITE_A 56 1210#define CLK_ACLK_AHBSYNCDN 57 1211#define CLK_ACLK_AXIUS_LITE_D 58 1212#define CLK_ACLK_AXIUS_LITE_B 59 1213#define CLK_ACLK_AXIUS_LITE_A 60 1214#define CLK_ACLK_ASYNCAPBM_3AA1 61 1215#define CLK_ACLK_ASYNCAPBS_3AA1 62 1216#define CLK_ACLK_ASYNCAPBM_3AA0 63 1217#define CLK_ACLK_ASYNCAPBS_3AA0 64 1218#define CLK_ACLK_ASYNCAPBM_LITE_D 65 1219#define CLK_ACLK_ASYNCAPBS_LITE_D 66 1220#define CLK_ACLK_ASYNCAPBM_LITE_B 67 1221#define CLK_ACLK_ASYNCAPBS_LITE_B 68 1222#define CLK_ACLK_ASYNCAPBM_LITE_A 69 1223#define CLK_ACLK_ASYNCAPBS_LITE_A 70 1224#define CLK_ACLK_ASYNCAXIM_ISP0P 71 1225#define CLK_ACLK_ASYNCAXIM_3AA1 72 1226#define CLK_ACLK_ASYNCAXIS_3AA1 73 1227#define CLK_ACLK_ASYNCAXIM_3AA0 74 1228#define CLK_ACLK_ASYNCAXIS_3AA0 75 1229#define CLK_ACLK_ASYNCAXIM_LITE_D 76 1230#define CLK_ACLK_ASYNCAXIS_LITE_D 77 1231#define CLK_ACLK_ASYNCAXIM_LITE_B 78 1232#define CLK_ACLK_ASYNCAXIS_LITE_B 79 1233#define CLK_ACLK_ASYNCAXIM_LITE_A 80 1234#define CLK_ACLK_ASYNCAXIS_LITE_A 81 1235#define CLK_ACLK_AHB2APB_ISPSFRP 82 1236#define CLK_ACLK_AXI2APB_ISP0P 83 1237#define CLK_ACLK_AXI2AHB_ISP0P 84 1238#define CLK_ACLK_XIU_IS0X 85 1239#define CLK_ACLK_XIU_ISP0EX 86 1240#define CLK_ACLK_CAM0NP_276 87 1241#define CLK_ACLK_CAM0ND_400 88 1242#define CLK_ACLK_SMMU_3AA1 89 1243#define CLK_ACLK_SMMU_3AA0 90 1244#define CLK_ACLK_SMMU_LITE_D 91 1245#define CLK_ACLK_SMMU_LITE_B 92 1246#define CLK_ACLK_SMMU_LITE_A 93 1247#define CLK_ACLK_BTS_3AA1 94 1248#define CLK_ACLK_BTS_3AA0 95 1249#define CLK_ACLK_BTS_LITE_D 96 1250#define CLK_ACLK_BTS_LITE_B 97 1251#define CLK_ACLK_BTS_LITE_A 98 1252#define CLK_PCLK_SMMU_3AA1 99 1253#define CLK_PCLK_SMMU_3AA0 100 1254#define CLK_PCLK_SMMU_LITE_D 101 1255#define CLK_PCLK_SMMU_LITE_B 102 1256#define CLK_PCLK_SMMU_LITE_A 103 1257#define CLK_PCLK_BTS_3AA1 104 1258#define CLK_PCLK_BTS_3AA0 105 1259#define CLK_PCLK_BTS_LITE_D 106 1260#define CLK_PCLK_BTS_LITE_B 107 1261#define CLK_PCLK_BTS_LITE_A 108 1262#define CLK_PCLK_ASYNCAXI_CAM1 109 1263#define CLK_PCLK_ASYNCAXI_3AA1 110 1264#define CLK_PCLK_ASYNCAXI_3AA0 111 1265#define CLK_PCLK_ASYNCAXI_LITE_D 112 1266#define CLK_PCLK_ASYNCAXI_LITE_B 113 1267#define CLK_PCLK_ASYNCAXI_LITE_A 114 1268#define CLK_PCLK_PMU_CAM0 115 1269#define CLK_PCLK_SYSREG_CAM0 116 1270#define CLK_PCLK_CMU_CAM0_LOCAL 117 1271#define CLK_PCLK_CSIS1 118 1272#define CLK_PCLK_CSIS0 119 1273#define CLK_PCLK_3AA1 120 1274#define CLK_PCLK_3AA0 121 1275#define CLK_PCLK_LITE_D 122 1276#define CLK_PCLK_LITE_B 123 1277#define CLK_PCLK_LITE_A 124 1278#define CLK_PHYCLK_RXBYTECLKHS0_S4 125 1279#define CLK_PHYCLK_RXBYTECLKHS0_S2A 126 1280#define CLK_SCLK_LITE_FREECNT 127 1281#define CLK_SCLK_PIXELASYNCM_3AA1 128 1282#define CLK_SCLK_PIXELASYNCM_3AA0 129 1283#define CLK_SCLK_PIXELASYNCS_3AA0 130 1284#define CLK_SCLK_PIXELASYNCM_LITE_C 131 1285#define CLK_SCLK_PIXELASYNCM_LITE_C_INIT 132 1286#define CLK_SCLK_PIXELASYNCS_LITE_C_INIT 133 1287 1288#define CAM0_NR_CLK 134 1289 1290/* CMU_CAM1 */ 1291#define CLK_PHYCLK_RXBYTEECLKHS0_S2B 1 1292 1293#define CLK_MOUT_SCLK_ISP_UART_USER 2 1294#define CLK_MOUT_SCLK_ISP_SPI1_USER 3 1295#define CLK_MOUT_SCLK_ISP_SPI0_USER 4 1296#define CLK_MOUT_ACLK_CAM1_333_USER 5 1297#define CLK_MOUT_ACLK_CAM1_400_USER 6 1298#define CLK_MOUT_ACLK_CAM1_552_USER 7 1299#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER 8 1300#define CLK_MOUT_ACLK_CSIS2_B 9 1301#define CLK_MOUT_ACLK_CSIS2_A 10 1302#define CLK_MOUT_ACLK_FD_B 11 1303#define CLK_MOUT_ACLK_FD_A 12 1304#define CLK_MOUT_ACLK_LITE_C_B 13 1305#define CLK_MOUT_ACLK_LITE_C_A 14 1306 1307#define CLK_DIV_SCLK_ISP_MPWM 15 1308#define CLK_DIV_PCLK_CAM1_83 16 1309#define CLK_DIV_PCLK_CAM1_166 17 1310#define CLK_DIV_PCLK_DBG_CAM1 18 1311#define CLK_DIV_ATCLK_CAM1 19 1312#define CLK_DIV_ACLK_CSIS2 20 1313#define CLK_DIV_PCLK_FD 21 1314#define CLK_DIV_ACLK_FD 22 1315#define CLK_DIV_PCLK_LITE_C 23 1316#define CLK_DIV_ACLK_LITE_C 24 1317 1318#define CLK_ACLK_ISP_GIC 25 1319#define CLK_ACLK_FD 26 1320#define CLK_ACLK_LITE_C 27 1321#define CLK_ACLK_CSIS2 28 1322#define CLK_ACLK_ASYNCAPBM_FD 29 1323#define CLK_ACLK_ASYNCAPBS_FD 30 1324#define CLK_ACLK_ASYNCAPBM_LITE_C 31 1325#define CLK_ACLK_ASYNCAPBS_LITE_C 32 1326#define CLK_ACLK_ASYNCAHBS_SFRISP2H2 33 1327#define CLK_ACLK_ASYNCAHBS_SFRISP2H1 34 1328#define CLK_ACLK_ASYNCAXIM_CA5 35 1329#define CLK_ACLK_ASYNCAXIS_CA5 36 1330#define CLK_ACLK_ASYNCAXIS_ISPX2 37 1331#define CLK_ACLK_ASYNCAXIS_ISPX1 38 1332#define CLK_ACLK_ASYNCAXIS_ISPX0 39 1333#define CLK_ACLK_ASYNCAXIM_ISPEX 40 1334#define CLK_ACLK_ASYNCAXIM_ISP3P 41 1335#define CLK_ACLK_ASYNCAXIS_ISP3P 42 1336#define CLK_ACLK_ASYNCAXIM_FD 43 1337#define CLK_ACLK_ASYNCAXIS_FD 44 1338#define CLK_ACLK_ASYNCAXIM_LITE_C 45 1339#define CLK_ACLK_ASYNCAXIS_LITE_C 46 1340#define CLK_ACLK_AHB2APB_ISP5P 47 1341#define CLK_ACLK_AHB2APB_ISP3P 48 1342#define CLK_ACLK_AXI2APB_ISP3P 49 1343#define CLK_ACLK_AHB_SFRISP2H 50 1344#define CLK_ACLK_AXI_ISP_HX_R 51 1345#define CLK_ACLK_AXI_ISP_CX_R 52 1346#define CLK_ACLK_AXI_ISP_HX 53 1347#define CLK_ACLK_AXI_ISP_CX 54 1348#define CLK_ACLK_XIU_ISPX 55 1349#define CLK_ACLK_XIU_ISPEX 56 1350#define CLK_ACLK_CAM1NP_333 57 1351#define CLK_ACLK_CAM1ND_400 58 1352#define CLK_ACLK_SMMU_ISPCPU 59 1353#define CLK_ACLK_SMMU_FD 60 1354#define CLK_ACLK_SMMU_LITE_C 61 1355#define CLK_ACLK_BTS_ISP3P 62 1356#define CLK_ACLK_BTS_FD 63 1357#define CLK_ACLK_BTS_LITE_C 64 1358#define CLK_ACLK_AHBDN_SFRISP2H 65 1359#define CLK_ACLK_AHBDN_ISP5P 66 1360#define CLK_ACLK_AXIUS_ISP3P 67 1361#define CLK_ACLK_AXIUS_FD 68 1362#define CLK_ACLK_AXIUS_LITE_C 69 1363#define CLK_PCLK_SMMU_ISPCPU 70 1364#define CLK_PCLK_SMMU_FD 71 1365#define CLK_PCLK_SMMU_LITE_C 72 1366#define CLK_PCLK_BTS_ISP3P 73 1367#define CLK_PCLK_BTS_FD 74 1368#define CLK_PCLK_BTS_LITE_C 75 1369#define CLK_PCLK_ASYNCAXIM_CA5 76 1370#define CLK_PCLK_ASYNCAXIM_ISPEX 77 1371#define CLK_PCLK_ASYNCAXIM_ISP3P 78 1372#define CLK_PCLK_ASYNCAXIM_FD 79 1373#define CLK_PCLK_ASYNCAXIM_LITE_C 80 1374#define CLK_PCLK_PMU_CAM1 81 1375#define CLK_PCLK_SYSREG_CAM1 82 1376#define CLK_PCLK_CMU_CAM1_LOCAL 83 1377#define CLK_PCLK_ISP_MCTADC 84 1378#define CLK_PCLK_ISP_WDT 85 1379#define CLK_PCLK_ISP_PWM 86 1380#define CLK_PCLK_ISP_UART 87 1381#define CLK_PCLK_ISP_MCUCTL 88 1382#define CLK_PCLK_ISP_SPI1 89 1383#define CLK_PCLK_ISP_SPI0 90 1384#define CLK_PCLK_ISP_I2C2 91 1385#define CLK_PCLK_ISP_I2C1 92 1386#define CLK_PCLK_ISP_I2C0 93 1387#define CLK_PCLK_ISP_MPWM 94 1388#define CLK_PCLK_FD 95 1389#define CLK_PCLK_LITE_C 96 1390#define CLK_PCLK_CSIS2 97 1391#define CLK_SCLK_ISP_I2C2 98 1392#define CLK_SCLK_ISP_I2C1 99 1393#define CLK_SCLK_ISP_I2C0 100 1394#define CLK_SCLK_ISP_PWM 101 1395#define CLK_PHYCLK_RXBYTECLKHS0_S2B 102 1396#define CLK_SCLK_LITE_C_FREECNT 103 1397#define CLK_SCLK_PIXELASYNCM_FD 104 1398#define CLK_SCLK_ISP_MCTADC 105 1399#define CLK_SCLK_ISP_UART 106 1400#define CLK_SCLK_ISP_SPI1 107 1401#define CLK_SCLK_ISP_SPI0 108 1402#define CLK_SCLK_ISP_MPWM 109 1403#define CLK_PCLK_DBG_ISP 110 1404#define CLK_ATCLK_ISP 111 1405#define CLK_SCLK_ISP_CA5 112 1406 1407#define CAM1_NR_CLK 113 1408 1409/* CMU_IMEM */ 1410#define CLK_ACLK_SLIMSSS 2 1411#define CLK_PCLK_SLIMSSS 35 1412 1413#define IMEM_NR_CLK 36 1414 1415#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ 1416