1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * Copyright (c) 2014-2016 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * William Jolitz. 8 * 9 * Portions of this software were developed by Andrew Turner 10 * under sponsorship from the FreeBSD Foundation 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)cpu.h 5.4 (Berkeley) 5/9/91 37 * from: FreeBSD: src/sys/i386/include/cpu.h,v 1.62 2001/06/29 38 * $FreeBSD$ 39 */ 40 41#ifndef _MACHINE_CPU_H_ 42#define _MACHINE_CPU_H_ 43 44#include <machine/atomic.h> 45#include <machine/frame.h> 46#include <machine/armreg.h> 47 48#define TRAPF_PC(tfp) ((tfp)->tf_lr) 49#define TRAPF_USERMODE(tfp) (((tfp)->tf_spsr & PSR_M_MASK) == PSR_M_EL0t) 50 51#define cpu_getstack(td) ((td)->td_frame->tf_sp) 52#define cpu_setstack(td, sp) ((td)->td_frame->tf_sp = (sp)) 53#define cpu_spinwait() __asm __volatile("yield" ::: "memory") 54#define cpu_lock_delay() DELAY(1) 55 56/* Extract CPU affinity levels 0-3 */ 57#define CPU_AFF0(mpidr) (u_int)(((mpidr) >> 0) & 0xff) 58#define CPU_AFF1(mpidr) (u_int)(((mpidr) >> 8) & 0xff) 59#define CPU_AFF2(mpidr) (u_int)(((mpidr) >> 16) & 0xff) 60#define CPU_AFF3(mpidr) (u_int)(((mpidr) >> 32) & 0xff) 61#define CPU_AFF0_MASK 0xffUL 62#define CPU_AFF1_MASK 0xff00UL 63#define CPU_AFF2_MASK 0xff0000UL 64#define CPU_AFF3_MASK 0xff00000000UL 65#define CPU_AFF_MASK (CPU_AFF0_MASK | CPU_AFF1_MASK | \ 66 CPU_AFF2_MASK| CPU_AFF3_MASK) /* Mask affinity fields in MPIDR_EL1 */ 67 68#ifdef _KERNEL 69 70#define CPU_IMPL_ARM 0x41 71#define CPU_IMPL_BROADCOM 0x42 72#define CPU_IMPL_CAVIUM 0x43 73#define CPU_IMPL_DEC 0x44 74#define CPU_IMPL_INFINEON 0x49 75#define CPU_IMPL_FREESCALE 0x4D 76#define CPU_IMPL_NVIDIA 0x4E 77#define CPU_IMPL_APM 0x50 78#define CPU_IMPL_QUALCOMM 0x51 79#define CPU_IMPL_MARVELL 0x56 80#define CPU_IMPL_INTEL 0x69 81 82/* ARM Part numbers */ 83#define CPU_PART_FOUNDATION 0xD00 84#define CPU_PART_CORTEX_A53 0xD03 85#define CPU_PART_CORTEX_A35 0xD04 86#define CPU_PART_CORTEX_A55 0xD05 87#define CPU_PART_CORTEX_A65 0xD06 88#define CPU_PART_CORTEX_A57 0xD07 89#define CPU_PART_CORTEX_A72 0xD08 90#define CPU_PART_CORTEX_A73 0xD09 91#define CPU_PART_CORTEX_A75 0xD0A 92#define CPU_PART_CORTEX_A76 0xD0B 93#define CPU_PART_NEOVERSE_N1 0xD0C 94#define CPU_PART_CORTEX_A77 0xD0D 95#define CPU_PART_CORTEX_A76AE 0xD0E 96 97/* Cavium Part numbers */ 98#define CPU_PART_THUNDERX 0x0A1 99#define CPU_PART_THUNDERX_81XX 0x0A2 100#define CPU_PART_THUNDERX_83XX 0x0A3 101#define CPU_PART_THUNDERX2 0x0AF 102 103#define CPU_REV_THUNDERX_1_0 0x00 104#define CPU_REV_THUNDERX_1_1 0x01 105 106#define CPU_REV_THUNDERX2_0 0x00 107 108/* APM / Ampere Part Number */ 109#define CPU_PART_EMAG8180 0x000 110 111#define CPU_IMPL(midr) (((midr) >> 24) & 0xff) 112#define CPU_PART(midr) (((midr) >> 4) & 0xfff) 113#define CPU_VAR(midr) (((midr) >> 20) & 0xf) 114#define CPU_REV(midr) (((midr) >> 0) & 0xf) 115 116#define CPU_IMPL_TO_MIDR(val) (((val) & 0xff) << 24) 117#define CPU_PART_TO_MIDR(val) (((val) & 0xfff) << 4) 118#define CPU_VAR_TO_MIDR(val) (((val) & 0xf) << 20) 119#define CPU_REV_TO_MIDR(val) (((val) & 0xf) << 0) 120 121#define CPU_IMPL_MASK (0xff << 24) 122#define CPU_PART_MASK (0xfff << 4) 123#define CPU_VAR_MASK (0xf << 20) 124#define CPU_REV_MASK (0xf << 0) 125 126#define CPU_ID_RAW(impl, part, var, rev) \ 127 (CPU_IMPL_TO_MIDR((impl)) | \ 128 CPU_PART_TO_MIDR((part)) | CPU_VAR_TO_MIDR((var)) | \ 129 CPU_REV_TO_MIDR((rev))) 130 131#define CPU_MATCH(mask, impl, part, var, rev) \ 132 (((mask) & PCPU_GET(midr)) == \ 133 ((mask) & CPU_ID_RAW((impl), (part), (var), (rev)))) 134 135#define CPU_MATCH_RAW(mask, devid) \ 136 (((mask) & PCPU_GET(midr)) == ((mask) & (devid))) 137 138/* 139 * Chip-specific errata. This defines are intended to be 140 * booleans used within if statements. When an appropriate 141 * kernel option is disabled, these defines must be defined 142 * as 0 to allow the compiler to remove a dead code thus 143 * produce better optimized kernel image. 144 */ 145/* 146 * Vendor: Cavium 147 * Chip: ThunderX 148 * Revision(s): Pass 1.0, Pass 1.1 149 */ 150#ifdef THUNDERX_PASS_1_1_ERRATA 151#define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 \ 152 (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \ 153 CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_0) || \ 154 CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \ 155 CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_1)) 156#else 157#define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 0 158#endif 159 160extern char btext[]; 161extern char etext[]; 162 163extern uint64_t __cpu_affinity[]; 164 165void cpu_halt(void) __dead2; 166void cpu_reset(void) __dead2; 167void fork_trampoline(void); 168void identify_cache(uint64_t); 169void identify_cpu(u_int); 170void install_cpu_errata(void); 171void swi_vm(void *v); 172 173/* Functions to read the sanitised view of the special registers */ 174void update_special_regs(u_int); 175bool extract_user_id_field(u_int, u_int, uint8_t *); 176bool get_kernel_reg(u_int, uint64_t *); 177 178#define CPU_AFFINITY(cpu) __cpu_affinity[(cpu)] 179#define CPU_CURRENT_SOCKET \ 180 (CPU_AFF2(CPU_AFFINITY(PCPU_GET(cpuid)))) 181 182static __inline uint64_t 183get_cyclecount(void) 184{ 185 uint64_t ret; 186 187 ret = READ_SPECIALREG(cntvct_el0); 188 189 return (ret); 190} 191 192#define ADDRESS_TRANSLATE_FUNC(stage) \ 193static inline uint64_t \ 194arm64_address_translate_ ##stage (uint64_t addr) \ 195{ \ 196 uint64_t ret; \ 197 \ 198 __asm __volatile( \ 199 "at " __STRING(stage) ", %1 \n" \ 200 "mrs %0, par_el1" : "=r"(ret) : "r"(addr)); \ 201 \ 202 return (ret); \ 203} 204 205ADDRESS_TRANSLATE_FUNC(s1e0r) 206ADDRESS_TRANSLATE_FUNC(s1e0w) 207ADDRESS_TRANSLATE_FUNC(s1e1r) 208ADDRESS_TRANSLATE_FUNC(s1e1w) 209 210#endif 211 212#endif /* !_MACHINE_CPU_H_ */ 213