1/*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * Copyright (c) 2015 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Andrew Turner under 7 * sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33#ifndef _MACHINE_ARMREG_H_ 34#define _MACHINE_ARMREG_H_ 35 36#define INSN_SIZE 4 37 38#define MRS_MASK 0xfff00000 39#define MRS_VALUE 0xd5300000 40#define MRS_SPECIAL(insn) ((insn) & 0x000fffe0) 41#define MRS_REGISTER(insn) ((insn) & 0x0000001f) 42#define MRS_Op0_SHIFT 19 43#define MRS_Op0_MASK 0x00080000 44#define MRS_Op1_SHIFT 16 45#define MRS_Op1_MASK 0x00070000 46#define MRS_CRn_SHIFT 12 47#define MRS_CRn_MASK 0x0000f000 48#define MRS_CRm_SHIFT 8 49#define MRS_CRm_MASK 0x00000f00 50#define MRS_Op2_SHIFT 5 51#define MRS_Op2_MASK 0x000000e0 52#define MRS_Rt_SHIFT 0 53#define MRS_Rt_MASK 0x0000001f 54#define MRS_REG(op0, op1, crn, crm, op2) \ 55 (((op0) << MRS_Op0_SHIFT) | ((op1) << MRS_Op1_SHIFT) | \ 56 ((crn) << MRS_CRn_SHIFT) | ((crm) << MRS_CRm_SHIFT) | \ 57 ((op2) << MRS_Op2_SHIFT)) 58 59#define READ_SPECIALREG(reg) \ 60({ uint64_t _val; \ 61 __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (_val)); \ 62 _val; \ 63}) 64#define WRITE_SPECIALREG(reg, _val) \ 65 __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)_val)) 66 67#define UL(x) UINT64_C(x) 68 69/* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */ 70#define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ 71#define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ 72#define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ 73#define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */ 74#define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/ 75 76/* CNTP_CTL_EL0 - Counter-timer Physical Timer Control register */ 77#define CNTP_CTL_ENABLE (1 << 0) 78#define CNTP_CTL_IMASK (1 << 1) 79#define CNTP_CTL_ISTATUS (1 << 2) 80 81/* CPACR_EL1 */ 82#define CPACR_FPEN_MASK (0x3 << 20) 83#define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */ 84#define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */ 85#define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */ 86#define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */ 87#define CPACR_TTA (0x1 << 28) 88 89/* CTR_EL0 - Cache Type Register */ 90#define CTR_RES1 (1 << 31) 91#define CTR_TminLine_SHIFT 32 92#define CTR_TminLine_MASK (UL(0x3f) << CTR_TminLine_SHIFT) 93#define CTR_TminLine_VAL(reg) ((reg) & CTR_TminLine_MASK) 94#define CTR_DIC_SHIFT 29 95#define CTR_DIC_MASK (0x1 << CTR_DIC_SHIFT) 96#define CTR_DIC_VAL(reg) ((reg) & CTR_DIC_MASK) 97#define CTR_IDC_SHIFT 28 98#define CTR_IDC_MASK (0x1 << CTR_IDC_SHIFT) 99#define CTR_IDC_VAL(reg) ((reg) & CTR_IDC_MASK) 100#define CTR_CWG_SHIFT 24 101#define CTR_CWG_MASK (0xf << CTR_CWG_SHIFT) 102#define CTR_CWG_VAL(reg) ((reg) & CTR_CWG_MASK) 103#define CTR_CWG_SIZE(reg) (4 << (CTR_CWG_VAL(reg) >> CTR_CWG_SHIFT)) 104#define CTR_ERG_SHIFT 20 105#define CTR_ERG_MASK (0xf << CTR_ERG_SHIFT) 106#define CTR_ERG_VAL(reg) ((reg) & CTR_ERG_MASK) 107#define CTR_ERG_SIZE(reg) (4 << (CTR_ERG_VAL(reg) >> CTR_ERG_SHIFT)) 108#define CTR_DLINE_SHIFT 16 109#define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) 110#define CTR_DLINE_VAL(reg) ((reg) & CTR_DLINE_MASK) 111#define CTR_DLINE_SIZE(reg) (4 << (CTR_DLINE_VAL(reg) >> CTR_DLINE_SHIFT)) 112#define CTR_L1IP_SHIFT 14 113#define CTR_L1IP_MASK (0x3 << CTR_L1IP_SHIFT) 114#define CTR_L1IP_VAL(reg) ((reg) & CTR_L1IP_MASK) 115#define CTR_L1IP_VPIPT (0 << CTR_L1IP_SHIFT) 116#define CTR_L1IP_AIVIVT (1 << CTR_L1IP_SHIFT) 117#define CTR_L1IP_VIPT (2 << CTR_L1IP_SHIFT) 118#define CTR_L1IP_PIPT (3 << CTR_L1IP_SHIFT) 119#define CTR_ILINE_SHIFT 0 120#define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) 121#define CTR_ILINE_VAL(reg) ((reg) & CTR_ILINE_MASK) 122#define CTR_ILINE_SIZE(reg) (4 << (CTR_ILINE_VAL(reg) >> CTR_ILINE_SHIFT)) 123 124/* DAIF - Interrupt Mask Bits */ 125#define DAIF_D_MASKED (1 << 9) 126#define DAIF_A_MASKED (1 << 8) 127#define DAIF_I_MASKED (1 << 7) 128#define DAIF_F_MASKED (1 << 6) 129 130/* DCZID_EL0 - Data Cache Zero ID register */ 131#define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */ 132#define DCZID_BS_SHIFT 0 133#define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT) 134#define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT) 135 136/* ESR_ELx */ 137#define ESR_ELx_ISS_MASK 0x01ffffff 138#define ISS_INSN_FnV (0x01 << 10) 139#define ISS_INSN_EA (0x01 << 9) 140#define ISS_INSN_S1PTW (0x01 << 7) 141#define ISS_INSN_IFSC_MASK (0x1f << 0) 142 143#define ISS_MSR_DIR_SHIFT 0 144#define ISS_MSR_DIR (0x01 << ISS_MSR_DIR_SHIFT) 145#define ISS_MSR_Rt_SHIFT 5 146#define ISS_MSR_Rt_MASK (0x1f << ISS_MSR_Rt_SHIFT) 147#define ISS_MSR_Rt(x) (((x) & ISS_MSR_Rt_MASK) >> ISS_MSR_Rt_SHIFT) 148#define ISS_MSR_CRm_SHIFT 1 149#define ISS_MSR_CRm_MASK (0xf << ISS_MSR_CRm_SHIFT) 150#define ISS_MSR_CRm(x) (((x) & ISS_MSR_CRm_MASK) >> ISS_MSR_CRm_SHIFT) 151#define ISS_MSR_CRn_SHIFT 10 152#define ISS_MSR_CRn_MASK (0xf << ISS_MSR_CRn_SHIFT) 153#define ISS_MSR_CRn(x) (((x) & ISS_MSR_CRn_MASK) >> ISS_MSR_CRn_SHIFT) 154#define ISS_MSR_OP1_SHIFT 14 155#define ISS_MSR_OP1_MASK (0x7 << ISS_MSR_OP1_SHIFT) 156#define ISS_MSR_OP1(x) (((x) & ISS_MSR_OP1_MASK) >> ISS_MSR_OP1_SHIFT) 157#define ISS_MSR_OP2_SHIFT 17 158#define ISS_MSR_OP2_MASK (0x7 << ISS_MSR_OP2_SHIFT) 159#define ISS_MSR_OP2(x) (((x) & ISS_MSR_OP2_MASK) >> ISS_MSR_OP2_SHIFT) 160#define ISS_MSR_OP0_SHIFT 20 161#define ISS_MSR_OP0_MASK (0x3 << ISS_MSR_OP0_SHIFT) 162#define ISS_MSR_OP0(x) (((x) & ISS_MSR_OP0_MASK) >> ISS_MSR_OP0_SHIFT) 163#define ISS_MSR_REG_MASK \ 164 (ISS_MSR_OP0_MASK | ISS_MSR_OP2_MASK | ISS_MSR_OP1_MASK | \ 165 ISS_MSR_CRn_MASK | ISS_MSR_CRm_MASK) 166 167#define ISS_DATA_ISV_SHIFT 24 168#define ISS_DATA_ISV (0x01 << ISS_DATA_ISV_SHIFT) 169#define ISS_DATA_SAS_SHIFT 22 170#define ISS_DATA_SAS_MASK (0x03 << ISS_DATA_SAS_SHIFT) 171#define ISS_DATA_SSE_SHIFT 21 172#define ISS_DATA_SSE (0x01 << ISS_DATA_SSE_SHIFT) 173#define ISS_DATA_SRT_SHIFT 16 174#define ISS_DATA_SRT_MASK (0x1f << ISS_DATA_SRT_SHIFT) 175#define ISS_DATA_SF (0x01 << 15) 176#define ISS_DATA_AR (0x01 << 14) 177#define ISS_DATA_FnV (0x01 << 10) 178#define ISS_DATA_EA (0x01 << 9) 179#define ISS_DATA_CM (0x01 << 8) 180#define ISS_DATA_S1PTW (0x01 << 7) 181#define ISS_DATA_WnR_SHIFT 6 182#define ISS_DATA_WnR (0x01 << ISS_DATA_WnR_SHIFT) 183#define ISS_DATA_DFSC_MASK (0x3f << 0) 184#define ISS_DATA_DFSC_ASF_L0 (0x00 << 0) 185#define ISS_DATA_DFSC_ASF_L1 (0x01 << 0) 186#define ISS_DATA_DFSC_ASF_L2 (0x02 << 0) 187#define ISS_DATA_DFSC_ASF_L3 (0x03 << 0) 188#define ISS_DATA_DFSC_TF_L0 (0x04 << 0) 189#define ISS_DATA_DFSC_TF_L1 (0x05 << 0) 190#define ISS_DATA_DFSC_TF_L2 (0x06 << 0) 191#define ISS_DATA_DFSC_TF_L3 (0x07 << 0) 192#define ISS_DATA_DFSC_AFF_L1 (0x09 << 0) 193#define ISS_DATA_DFSC_AFF_L2 (0x0a << 0) 194#define ISS_DATA_DFSC_AFF_L3 (0x0b << 0) 195#define ISS_DATA_DFSC_PF_L1 (0x0d << 0) 196#define ISS_DATA_DFSC_PF_L2 (0x0e << 0) 197#define ISS_DATA_DFSC_PF_L3 (0x0f << 0) 198#define ISS_DATA_DFSC_EXT (0x10 << 0) 199#define ISS_DATA_DFSC_EXT_L0 (0x14 << 0) 200#define ISS_DATA_DFSC_EXT_L1 (0x15 << 0) 201#define ISS_DATA_DFSC_EXT_L2 (0x16 << 0) 202#define ISS_DATA_DFSC_EXT_L3 (0x17 << 0) 203#define ISS_DATA_DFSC_ECC (0x18 << 0) 204#define ISS_DATA_DFSC_ECC_L0 (0x1c << 0) 205#define ISS_DATA_DFSC_ECC_L1 (0x1d << 0) 206#define ISS_DATA_DFSC_ECC_L2 (0x1e << 0) 207#define ISS_DATA_DFSC_ECC_L3 (0x1f << 0) 208#define ISS_DATA_DFSC_ALIGN (0x21 << 0) 209#define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0) 210#define ESR_ELx_IL (0x01 << 25) 211#define ESR_ELx_EC_SHIFT 26 212#define ESR_ELx_EC_MASK (0x3f << 26) 213#define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 214#define EXCP_UNKNOWN 0x00 /* Unkwn exception */ 215#define EXCP_TRAP_WFI_WFE 0x01 /* Trapped WFI or WFE */ 216#define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */ 217#define EXCP_ILL_STATE 0x0e /* Illegal execution state */ 218#define EXCP_SVC32 0x11 /* SVC trap for AArch32 */ 219#define EXCP_SVC64 0x15 /* SVC trap for AArch64 */ 220#define EXCP_HVC 0x16 /* HVC trap */ 221#define EXCP_MSR 0x18 /* MSR/MRS trap */ 222#define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */ 223#define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */ 224#define EXCP_PC_ALIGN 0x22 /* PC alignment fault */ 225#define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */ 226#define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */ 227#define EXCP_SP_ALIGN 0x26 /* SP slignment fault */ 228#define EXCP_TRAP_FP 0x2c /* Trapped FP exception */ 229#define EXCP_SERROR 0x2f /* SError interrupt */ 230#define EXCP_BRKPT_EL0 0x30 /* Hardware breakpoint, from same EL */ 231#define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */ 232#define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */ 233#define EXCP_WATCHPT_EL0 0x34 /* Watchpoint, from lower EL */ 234#define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */ 235#define EXCP_BRK 0x3c /* Breakpoint */ 236 237/* ICC_CTLR_EL1 */ 238#define ICC_CTLR_EL1_EOIMODE (1U << 1) 239 240/* ICC_IAR1_EL1 */ 241#define ICC_IAR1_EL1_SPUR (0x03ff) 242 243/* ICC_IGRPEN0_EL1 */ 244#define ICC_IGRPEN0_EL1_EN (1U << 0) 245 246/* ICC_PMR_EL1 */ 247#define ICC_PMR_EL1_PRIO_MASK (0xFFUL) 248 249/* ICC_SGI1R_EL1 */ 250#define ICC_SGI1R_EL1_TL_MASK 0xffffUL 251#define ICC_SGI1R_EL1_AFF1_SHIFT 16 252#define ICC_SGI1R_EL1_SGIID_SHIFT 24 253#define ICC_SGI1R_EL1_AFF2_SHIFT 32 254#define ICC_SGI1R_EL1_AFF3_SHIFT 48 255#define ICC_SGI1R_EL1_SGIID_MASK 0xfUL 256#define ICC_SGI1R_EL1_IRM (0x1UL << 40) 257 258/* ICC_SRE_EL1 */ 259#define ICC_SRE_EL1_SRE (1U << 0) 260 261/* ID_AA64DFR0_EL1 */ 262#define ID_AA64DFR0_EL1 MRS_REG(3, 0, 0, 5, 0) 263#define ID_AA64DFR0_DebugVer_SHIFT 0 264#define ID_AA64DFR0_DebugVer_MASK (UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT) 265#define ID_AA64DFR0_DebugVer_VAL(x) ((x) & ID_AA64DFR0_DebugVer_MASK) 266#define ID_AA64DFR0_DebugVer_8 (UL(0x6) << ID_AA64DFR0_DebugVer_SHIFT) 267#define ID_AA64DFR0_DebugVer_8_VHE (UL(0x7) << ID_AA64DFR0_DebugVer_SHIFT) 268#define ID_AA64DFR0_DebugVer_8_2 (UL(0x8) << ID_AA64DFR0_DebugVer_SHIFT) 269#define ID_AA64DFR0_TraceVer_SHIFT 4 270#define ID_AA64DFR0_TraceVer_MASK (UL(0xf) << ID_AA64DFR0_TraceVer_SHIFT) 271#define ID_AA64DFR0_TraceVer_VAL(x) ((x) & ID_AA64DFR0_TraceVer_MASK) 272#define ID_AA64DFR0_TraceVer_NONE (UL(0x0) << ID_AA64DFR0_TraceVer_SHIFT) 273#define ID_AA64DFR0_TraceVer_IMPL (UL(0x1) << ID_AA64DFR0_TraceVer_SHIFT) 274#define ID_AA64DFR0_PMUVer_SHIFT 8 275#define ID_AA64DFR0_PMUVer_MASK (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT) 276#define ID_AA64DFR0_PMUVer_VAL(x) ((x) & ID_AA64DFR0_PMUVer_MASK) 277#define ID_AA64DFR0_PMUVer_NONE (UL(0x0) << ID_AA64DFR0_PMUVer_SHIFT) 278#define ID_AA64DFR0_PMUVer_3 (UL(0x1) << ID_AA64DFR0_PMUVer_SHIFT) 279#define ID_AA64DFR0_PMUVer_3_1 (UL(0x4) << ID_AA64DFR0_PMUVer_SHIFT) 280#define ID_AA64DFR0_PMUVer_IMPL (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT) 281#define ID_AA64DFR0_BRPs_SHIFT 12 282#define ID_AA64DFR0_BRPs_MASK (UL(0xf) << ID_AA64DFR0_BRPs_SHIFT) 283#define ID_AA64DFR0_BRPs_VAL(x) \ 284 ((((x) >> ID_AA64DFR0_BRPs_SHIFT) & 0xf) + 1) 285#define ID_AA64DFR0_WRPs_SHIFT 20 286#define ID_AA64DFR0_WRPs_MASK (UL(0xf) << ID_AA64DFR0_WRPs_SHIFT) 287#define ID_AA64DFR0_WRPs_VAL(x) \ 288 ((((x) >> ID_AA64DFR0_WRPs_SHIFT) & 0xf) + 1) 289#define ID_AA64DFR0_CTX_CMPs_SHIFT 28 290#define ID_AA64DFR0_CTX_CMPs_MASK (UL(0xf) << ID_AA64DFR0_CTX_CMPs_SHIFT) 291#define ID_AA64DFR0_CTX_CMPs_VAL(x) \ 292 ((((x) >> ID_AA64DFR0_CTX_CMPs_SHIFT) & 0xf) + 1) 293#define ID_AA64DFR0_PMSVer_SHIFT 32 294#define ID_AA64DFR0_PMSVer_MASK (UL(0xf) << ID_AA64DFR0_PMSVer_SHIFT) 295#define ID_AA64DFR0_PMSVer_VAL(x) ((x) & ID_AA64DFR0_PMSVer_MASK) 296#define ID_AA64DFR0_PMSVer_NONE (UL(0x0) << ID_AA64DFR0_PMSVer_SHIFT) 297#define ID_AA64DFR0_PMSVer_V1 (UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT) 298 299/* ID_AA64ISAR0_EL1 */ 300#define ID_AA64ISAR0_EL1 MRS_REG(3, 0, 0, 6, 0) 301#define ID_AA64ISAR0_AES_SHIFT 4 302#define ID_AA64ISAR0_AES_MASK (UL(0xf) << ID_AA64ISAR0_AES_SHIFT) 303#define ID_AA64ISAR0_AES_VAL(x) ((x) & ID_AA64ISAR0_AES_MASK) 304#define ID_AA64ISAR0_AES_NONE (UL(0x0) << ID_AA64ISAR0_AES_SHIFT) 305#define ID_AA64ISAR0_AES_BASE (UL(0x1) << ID_AA64ISAR0_AES_SHIFT) 306#define ID_AA64ISAR0_AES_PMULL (UL(0x2) << ID_AA64ISAR0_AES_SHIFT) 307#define ID_AA64ISAR0_SHA1_SHIFT 8 308#define ID_AA64ISAR0_SHA1_MASK (UL(0xf) << ID_AA64ISAR0_SHA1_SHIFT) 309#define ID_AA64ISAR0_SHA1_VAL(x) ((x) & ID_AA64ISAR0_SHA1_MASK) 310#define ID_AA64ISAR0_SHA1_NONE (UL(0x0) << ID_AA64ISAR0_SHA1_SHIFT) 311#define ID_AA64ISAR0_SHA1_BASE (UL(0x1) << ID_AA64ISAR0_SHA1_SHIFT) 312#define ID_AA64ISAR0_SHA2_SHIFT 12 313#define ID_AA64ISAR0_SHA2_MASK (UL(0xf) << ID_AA64ISAR0_SHA2_SHIFT) 314#define ID_AA64ISAR0_SHA2_VAL(x) ((x) & ID_AA64ISAR0_SHA2_MASK) 315#define ID_AA64ISAR0_SHA2_NONE (UL(0x0) << ID_AA64ISAR0_SHA2_SHIFT) 316#define ID_AA64ISAR0_SHA2_BASE (UL(0x1) << ID_AA64ISAR0_SHA2_SHIFT) 317#define ID_AA64ISAR0_SHA2_512 (UL(0x2) << ID_AA64ISAR0_SHA2_SHIFT) 318#define ID_AA64ISAR0_CRC32_SHIFT 16 319#define ID_AA64ISAR0_CRC32_MASK (UL(0xf) << ID_AA64ISAR0_CRC32_SHIFT) 320#define ID_AA64ISAR0_CRC32_VAL(x) ((x) & ID_AA64ISAR0_CRC32_MASK) 321#define ID_AA64ISAR0_CRC32_NONE (UL(0x0) << ID_AA64ISAR0_CRC32_SHIFT) 322#define ID_AA64ISAR0_CRC32_BASE (UL(0x1) << ID_AA64ISAR0_CRC32_SHIFT) 323#define ID_AA64ISAR0_Atomic_SHIFT 20 324#define ID_AA64ISAR0_Atomic_MASK (UL(0xf) << ID_AA64ISAR0_Atomic_SHIFT) 325#define ID_AA64ISAR0_Atomic_VAL(x) ((x) & ID_AA64ISAR0_Atomic_MASK) 326#define ID_AA64ISAR0_Atomic_NONE (UL(0x0) << ID_AA64ISAR0_Atomic_SHIFT) 327#define ID_AA64ISAR0_Atomic_IMPL (UL(0x2) << ID_AA64ISAR0_Atomic_SHIFT) 328#define ID_AA64ISAR0_RDM_SHIFT 28 329#define ID_AA64ISAR0_RDM_MASK (UL(0xf) << ID_AA64ISAR0_RDM_SHIFT) 330#define ID_AA64ISAR0_RDM_VAL(x) ((x) & ID_AA64ISAR0_RDM_MASK) 331#define ID_AA64ISAR0_RDM_NONE (UL(0x0) << ID_AA64ISAR0_RDM_SHIFT) 332#define ID_AA64ISAR0_RDM_IMPL (UL(0x1) << ID_AA64ISAR0_RDM_SHIFT) 333#define ID_AA64ISAR0_SHA3_SHIFT 32 334#define ID_AA64ISAR0_SHA3_MASK (UL(0xf) << ID_AA64ISAR0_SHA3_SHIFT) 335#define ID_AA64ISAR0_SHA3_VAL(x) ((x) & ID_AA64ISAR0_SHA3_MASK) 336#define ID_AA64ISAR0_SHA3_NONE (UL(0x0) << ID_AA64ISAR0_SHA3_SHIFT) 337#define ID_AA64ISAR0_SHA3_IMPL (UL(0x1) << ID_AA64ISAR0_SHA3_SHIFT) 338#define ID_AA64ISAR0_SM3_SHIFT 36 339#define ID_AA64ISAR0_SM3_MASK (UL(0xf) << ID_AA64ISAR0_SM3_SHIFT) 340#define ID_AA64ISAR0_SM3_VAL(x) ((x) & ID_AA64ISAR0_SM3_MASK) 341#define ID_AA64ISAR0_SM3_NONE (UL(0x0) << ID_AA64ISAR0_SM3_SHIFT) 342#define ID_AA64ISAR0_SM3_IMPL (UL(0x1) << ID_AA64ISAR0_SM3_SHIFT) 343#define ID_AA64ISAR0_SM4_SHIFT 40 344#define ID_AA64ISAR0_SM4_MASK (UL(0xf) << ID_AA64ISAR0_SM4_SHIFT) 345#define ID_AA64ISAR0_SM4_VAL(x) ((x) & ID_AA64ISAR0_SM4_MASK) 346#define ID_AA64ISAR0_SM4_NONE (UL(0x0) << ID_AA64ISAR0_SM4_SHIFT) 347#define ID_AA64ISAR0_SM4_IMPL (UL(0x1) << ID_AA64ISAR0_SM4_SHIFT) 348#define ID_AA64ISAR0_DP_SHIFT 44 349#define ID_AA64ISAR0_DP_MASK (UL(0xf) << ID_AA64ISAR0_DP_SHIFT) 350#define ID_AA64ISAR0_DP_VAL(x) ((x) & ID_AA64ISAR0_DP_MASK) 351#define ID_AA64ISAR0_DP_NONE (UL(0x0) << ID_AA64ISAR0_DP_SHIFT) 352#define ID_AA64ISAR0_DP_IMPL (UL(0x1) << ID_AA64ISAR0_DP_SHIFT) 353#define ID_AA64ISAR0_FHM_SHIFT 48 354#define ID_AA64ISAR0_FHM_MASK (UL(0xf) << ID_AA64ISAR0_FHM_SHIFT) 355#define ID_AA64ISAR0_FHM_VAL(x) ((x) & ID_AA64ISAR0_FHM_MASK) 356#define ID_AA64ISAR0_FHM_NONE (UL(0x0) << ID_AA64ISAR0_FHM_SHIFT) 357#define ID_AA64ISAR0_FHM_IMPL (UL(0x1) << ID_AA64ISAR0_FHM_SHIFT) 358#define ID_AA64ISAR0_TS_SHIFT 52 359#define ID_AA64ISAR0_TS_MASK (UL(0xf) << ID_AA64ISAR0_TS_SHIFT) 360#define ID_AA64ISAR0_TS_VAL(x) ((x) & ID_AA64ISAR0_TS_MASK) 361#define ID_AA64ISAR0_TS_NONE (UL(0x0) << ID_AA64ISAR0_TS_SHIFT) 362#define ID_AA64ISAR0_TS_CondM_8_4 (UL(0x1) << ID_AA64ISAR0_TS_SHIFT) 363#define ID_AA64ISAR0_TS_CondM_8_5 (UL(0x2) << ID_AA64ISAR0_TS_SHIFT) 364#define ID_AA64ISAR0_TLB_SHIFT 56 365#define ID_AA64ISAR0_TLB_MASK (UL(0xf) << ID_AA64ISAR0_TLB_SHIFT) 366#define ID_AA64ISAR0_TLB_VAL(x) ((x) & ID_AA64ISAR0_TLB_MASK) 367#define ID_AA64ISAR0_TLB_NONE (UL(0x0) << ID_AA64ISAR0_TLB_SHIFT) 368#define ID_AA64ISAR0_TLB_TLBIOS (UL(0x1) << ID_AA64ISAR0_TLB_SHIFT) 369#define ID_AA64ISAR0_TLB_TLBIOSR (UL(0x2) << ID_AA64ISAR0_TLB_SHIFT) 370#define ID_AA64ISAR0_RNDR_SHIFT 60 371#define ID_AA64ISAR0_RNDR_MASK (UL(0xf) << ID_AA64ISAR0_RNDR_SHIFT) 372#define ID_AA64ISAR0_RNDR_VAL(x) ((x) & ID_AA64ISAR0_RNDR_MASK) 373#define ID_AA64ISAR0_RNDR_NONE (UL(0x0) << ID_AA64ISAR0_RNDR_SHIFT) 374#define ID_AA64ISAR0_RNDR_IMPL (UL(0x1) << ID_AA64ISAR0_RNDR_SHIFT) 375 376/* ID_AA64ISAR1_EL1 */ 377#define ID_AA64ISAR1_EL1 MRS_REG(3, 0, 0, 6, 1) 378#define ID_AA64ISAR1_DPB_SHIFT 0 379#define ID_AA64ISAR1_DPB_MASK (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT) 380#define ID_AA64ISAR1_DPB_VAL(x) ((x) & ID_AA64ISAR1_DPB_MASK) 381#define ID_AA64ISAR1_DPB_NONE (UL(0x0) << ID_AA64ISAR1_DPB_SHIFT) 382#define ID_AA64ISAR1_DPB_DCCVAP (UL(0x1) << ID_AA64ISAR1_DPB_SHIFT) 383#define ID_AA64ISAR1_DPB_DCCVADP (UL(0x2) << ID_AA64ISAR1_DPB_SHIFT) 384#define ID_AA64ISAR1_APA_SHIFT 4 385#define ID_AA64ISAR1_APA_MASK (UL(0xf) << ID_AA64ISAR1_APA_SHIFT) 386#define ID_AA64ISAR1_APA_VAL(x) ((x) & ID_AA64ISAR1_APA_MASK) 387#define ID_AA64ISAR1_APA_NONE (UL(0x0) << ID_AA64ISAR1_APA_SHIFT) 388#define ID_AA64ISAR1_APA_IMPL (UL(0x1) << ID_AA64ISAR1_APA_SHIFT) 389#define ID_AA64ISAR1_API_SHIFT 8 390#define ID_AA64ISAR1_API_MASK (UL(0xf) << ID_AA64ISAR1_API_SHIFT) 391#define ID_AA64ISAR1_API_VAL(x) ((x) & ID_AA64ISAR1_API_MASK) 392#define ID_AA64ISAR1_API_NONE (UL(0x0) << ID_AA64ISAR1_API_SHIFT) 393#define ID_AA64ISAR1_API_IMPL (UL(0x1) << ID_AA64ISAR1_API_SHIFT) 394#define ID_AA64ISAR1_JSCVT_SHIFT 12 395#define ID_AA64ISAR1_JSCVT_MASK (UL(0xf) << ID_AA64ISAR1_JSCVT_SHIFT) 396#define ID_AA64ISAR1_JSCVT_VAL(x) ((x) & ID_AA64ISAR1_JSCVT_MASK) 397#define ID_AA64ISAR1_JSCVT_NONE (UL(0x0) << ID_AA64ISAR1_JSCVT_SHIFT) 398#define ID_AA64ISAR1_JSCVT_IMPL (UL(0x1) << ID_AA64ISAR1_JSCVT_SHIFT) 399#define ID_AA64ISAR1_FCMA_SHIFT 16 400#define ID_AA64ISAR1_FCMA_MASK (UL(0xf) << ID_AA64ISAR1_FCMA_SHIFT) 401#define ID_AA64ISAR1_FCMA_VAL(x) ((x) & ID_AA64ISAR1_FCMA_MASK) 402#define ID_AA64ISAR1_FCMA_NONE (UL(0x0) << ID_AA64ISAR1_FCMA_SHIFT) 403#define ID_AA64ISAR1_FCMA_IMPL (UL(0x1) << ID_AA64ISAR1_FCMA_SHIFT) 404#define ID_AA64ISAR1_LRCPC_SHIFT 20 405#define ID_AA64ISAR1_LRCPC_MASK (UL(0xf) << ID_AA64ISAR1_LRCPC_SHIFT) 406#define ID_AA64ISAR1_LRCPC_VAL(x) ((x) & ID_AA64ISAR1_LRCPC_MASK) 407#define ID_AA64ISAR1_LRCPC_NONE (UL(0x0) << ID_AA64ISAR1_LRCPC_SHIFT) 408#define ID_AA64ISAR1_LRCPC_RCPC_8_3 (UL(0x1) << ID_AA64ISAR1_LRCPC_SHIFT) 409#define ID_AA64ISAR1_LRCPC_RCPC_8_4 (UL(0x2) << ID_AA64ISAR1_LRCPC_SHIFT) 410#define ID_AA64ISAR1_GPA_SHIFT 24 411#define ID_AA64ISAR1_GPA_MASK (UL(0xf) << ID_AA64ISAR1_GPA_SHIFT) 412#define ID_AA64ISAR1_GPA_VAL(x) ((x) & ID_AA64ISAR1_GPA_MASK) 413#define ID_AA64ISAR1_GPA_NONE (UL(0x0) << ID_AA64ISAR1_GPA_SHIFT) 414#define ID_AA64ISAR1_GPA_IMPL (UL(0x1) << ID_AA64ISAR1_GPA_SHIFT) 415#define ID_AA64ISAR1_GPI_SHIFT 28 416#define ID_AA64ISAR1_GPI_MASK (UL(0xf) << ID_AA64ISAR1_GPI_SHIFT) 417#define ID_AA64ISAR1_GPI_VAL(x) ((x) & ID_AA64ISAR1_GPI_MASK) 418#define ID_AA64ISAR1_GPI_NONE (UL(0x0) << ID_AA64ISAR1_GPI_SHIFT) 419#define ID_AA64ISAR1_GPI_IMPL (UL(0x1) << ID_AA64ISAR1_GPI_SHIFT) 420#define ID_AA64ISAR1_FRINTTS_SHIFT 32 421#define ID_AA64ISAR1_FRINTTS_MASK (UL(0xf) << ID_AA64ISAR1_FRINTTS_SHIFT) 422#define ID_AA64ISAR1_FRINTTS_VAL(x) ((x) & ID_AA64ISAR1_FRINTTS_MASK) 423#define ID_AA64ISAR1_FRINTTS_NONE (UL(0x0) << ID_AA64ISAR1_FRINTTS_SHIFT) 424#define ID_AA64ISAR1_FRINTTS_IMPL (UL(0x1) << ID_AA64ISAR1_FRINTTS_SHIFT) 425#define ID_AA64ISAR1_SB_SHIFT 36 426#define ID_AA64ISAR1_SB_MASK (UL(0xf) << ID_AA64ISAR1_SB_SHIFT) 427#define ID_AA64ISAR1_SB_VAL(x) ((x) & ID_AA64ISAR1_SB_MASK) 428#define ID_AA64ISAR1_SB_NONE (UL(0x0) << ID_AA64ISAR1_SB_SHIFT) 429#define ID_AA64ISAR1_SB_IMPL (UL(0x1) << ID_AA64ISAR1_SB_SHIFT) 430#define ID_AA64ISAR1_SPECRES_SHIFT 40 431#define ID_AA64ISAR1_SPECRES_MASK (UL(0xf) << ID_AA64ISAR1_SPECRES_SHIFT) 432#define ID_AA64ISAR1_SPECRES_VAL(x) ((x) & ID_AA64ISAR1_SPECRES_MASK) 433#define ID_AA64ISAR1_SPECRES_NONE (UL(0x0) << ID_AA64ISAR1_SPECRES_SHIFT) 434#define ID_AA64ISAR1_SPECRES_IMPL (UL(0x1) << ID_AA64ISAR1_SPECRES_SHIFT) 435#define ID_AA64ISAR1_BF16_SHIFT 44 436#define ID_AA64ISAR1_BF16_MASK (UL(0xf) << ID_AA64ISAR1_BF16_SHIFT) 437#define ID_AA64ISAR1_BF16_VAL(x) ((x) & ID_AA64ISAR1_BF16_MASK) 438#define ID_AA64ISAR1_BF16_NONE (UL(0x0) << ID_AA64ISAR1_BF16_SHIFT) 439#define ID_AA64ISAR1_BF16_IMPL (UL(0x1) << ID_AA64ISAR1_BF16_SHIFT) 440#define ID_AA64ISAR1_DGH_SHIFT 48 441#define ID_AA64ISAR1_DGH_MASK (UL(0xf) << ID_AA64ISAR1_DGH_SHIFT) 442#define ID_AA64ISAR1_DGH_VAL(x) ((x) & ID_AA64ISAR1_DGH_MASK) 443#define ID_AA64ISAR1_DGH_NONE (UL(0x0) << ID_AA64ISAR1_DGH_SHIFT) 444#define ID_AA64ISAR1_DGH_IMPL (UL(0x1) << ID_AA64ISAR1_DGH_SHIFT) 445#define ID_AA64ISAR1_I8MM_SHIFT 52 446#define ID_AA64ISAR1_I8MM_MASK (UL(0xf) << ID_AA64ISAR1_I8MM_SHIFT) 447#define ID_AA64ISAR1_I8MM_VAL(x) ((x) & ID_AA64ISAR1_I8MM_MASK) 448#define ID_AA64ISAR1_I8MM_NONE (UL(0x0) << ID_AA64ISAR1_I8MM_SHIFT) 449#define ID_AA64ISAR1_I8MM_IMPL (UL(0x1) << ID_AA64ISAR1_I8MM_SHIFT) 450 451/* ID_AA64MMFR0_EL1 */ 452#define ID_AA64MMFR0_EL1 MRS_REG(3, 0, 0, 7, 0) 453#define ID_AA64MMFR0_PARange_SHIFT 0 454#define ID_AA64MMFR0_PARange_MASK (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT) 455#define ID_AA64MMFR0_PARange_VAL(x) ((x) & ID_AA64MMFR0_PARange_MASK) 456#define ID_AA64MMFR0_PARange_4G (UL(0x0) << ID_AA64MMFR0_PARange_SHIFT) 457#define ID_AA64MMFR0_PARange_64G (UL(0x1) << ID_AA64MMFR0_PARange_SHIFT) 458#define ID_AA64MMFR0_PARange_1T (UL(0x2) << ID_AA64MMFR0_PARange_SHIFT) 459#define ID_AA64MMFR0_PARange_4T (UL(0x3) << ID_AA64MMFR0_PARange_SHIFT) 460#define ID_AA64MMFR0_PARange_16T (UL(0x4) << ID_AA64MMFR0_PARange_SHIFT) 461#define ID_AA64MMFR0_PARange_256T (UL(0x5) << ID_AA64MMFR0_PARange_SHIFT) 462#define ID_AA64MMFR0_PARange_4P (UL(0x6) << ID_AA64MMFR0_PARange_SHIFT) 463#define ID_AA64MMFR0_ASIDBits_SHIFT 4 464#define ID_AA64MMFR0_ASIDBits_MASK (UL(0xf) << ID_AA64MMFR0_ASIDBits_SHIFT) 465#define ID_AA64MMFR0_ASIDBits_VAL(x) ((x) & ID_AA64MMFR0_ASIDBits_MASK) 466#define ID_AA64MMFR0_ASIDBits_8 (UL(0x0) << ID_AA64MMFR0_ASIDBits_SHIFT) 467#define ID_AA64MMFR0_ASIDBits_16 (UL(0x2) << ID_AA64MMFR0_ASIDBits_SHIFT) 468#define ID_AA64MMFR0_BigEnd_SHIFT 8 469#define ID_AA64MMFR0_BigEnd_MASK (UL(0xf) << ID_AA64MMFR0_BigEnd_SHIFT) 470#define ID_AA64MMFR0_BigEnd_VAL(x) ((x) & ID_AA64MMFR0_BigEnd_MASK) 471#define ID_AA64MMFR0_BigEnd_FIXED (UL(0x0) << ID_AA64MMFR0_BigEnd_SHIFT) 472#define ID_AA64MMFR0_BigEnd_MIXED (UL(0x1) << ID_AA64MMFR0_BigEnd_SHIFT) 473#define ID_AA64MMFR0_SNSMem_SHIFT 12 474#define ID_AA64MMFR0_SNSMem_MASK (UL(0xf) << ID_AA64MMFR0_SNSMem_SHIFT) 475#define ID_AA64MMFR0_SNSMem_VAL(x) ((x) & ID_AA64MMFR0_SNSMem_MASK) 476#define ID_AA64MMFR0_SNSMem_NONE (UL(0x0) << ID_AA64MMFR0_SNSMem_SHIFT) 477#define ID_AA64MMFR0_SNSMem_DISTINCT (UL(0x1) << ID_AA64MMFR0_SNSMem_SHIFT) 478#define ID_AA64MMFR0_BigEndEL0_SHIFT 16 479#define ID_AA64MMFR0_BigEndEL0_MASK (UL(0xf) << ID_AA64MMFR0_BigEndEL0_SHIFT) 480#define ID_AA64MMFR0_BigEndEL0_VAL(x) ((x) & ID_AA64MMFR0_BigEndEL0_MASK) 481#define ID_AA64MMFR0_BigEndEL0_FIXED (UL(0x0) << ID_AA64MMFR0_BigEndEL0_SHIFT) 482#define ID_AA64MMFR0_BigEndEL0_MIXED (UL(0x1) << ID_AA64MMFR0_BigEndEL0_SHIFT) 483#define ID_AA64MMFR0_TGran16_SHIFT 20 484#define ID_AA64MMFR0_TGran16_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_SHIFT) 485#define ID_AA64MMFR0_TGran16_VAL(x) ((x) & ID_AA64MMFR0_TGran16_MASK) 486#define ID_AA64MMFR0_TGran16_NONE (UL(0x0) << ID_AA64MMFR0_TGran16_SHIFT) 487#define ID_AA64MMFR0_TGran16_IMPL (UL(0x1) << ID_AA64MMFR0_TGran16_SHIFT) 488#define ID_AA64MMFR0_TGran64_SHIFT 24 489#define ID_AA64MMFR0_TGran64_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT) 490#define ID_AA64MMFR0_TGran64_VAL(x) ((x) & ID_AA64MMFR0_TGran64_MASK) 491#define ID_AA64MMFR0_TGran64_IMPL (UL(0x0) << ID_AA64MMFR0_TGran64_SHIFT) 492#define ID_AA64MMFR0_TGran64_NONE (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT) 493#define ID_AA64MMFR0_TGran4_SHIFT 28 494#define ID_AA64MMFR0_TGran4_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT) 495#define ID_AA64MMFR0_TGran4_VAL(x) ((x) & ID_AA64MMFR0_TGran4_MASK) 496#define ID_AA64MMFR0_TGran4_IMPL (UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT) 497#define ID_AA64MMFR0_TGran4_NONE (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT) 498 499/* ID_AA64MMFR1_EL1 */ 500#define ID_AA64MMFR1_EL1 MRS_REG(3, 0, 0, 7, 1) 501#define ID_AA64MMFR1_HAFDBS_SHIFT 0 502#define ID_AA64MMFR1_HAFDBS_MASK (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT) 503#define ID_AA64MMFR1_HAFDBS_VAL(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) 504#define ID_AA64MMFR1_HAFDBS_NONE (UL(0x0) << ID_AA64MMFR1_HAFDBS_SHIFT) 505#define ID_AA64MMFR1_HAFDBS_AF (UL(0x1) << ID_AA64MMFR1_HAFDBS_SHIFT) 506#define ID_AA64MMFR1_HAFDBS_AF_DBS (UL(0x2) << ID_AA64MMFR1_HAFDBS_SHIFT) 507#define ID_AA64MMFR1_VMIDBits_SHIFT 4 508#define ID_AA64MMFR1_VMIDBits_MASK (UL(0xf) << ID_AA64MMFR1_VMIDBits_SHIFT) 509#define ID_AA64MMFR1_VMIDBits_VAL(x) ((x) & ID_AA64MMFR1_VMIDBits_MASK) 510#define ID_AA64MMFR1_VMIDBits_8 (UL(0x0) << ID_AA64MMFR1_VMIDBits_SHIFT) 511#define ID_AA64MMFR1_VMIDBits_16 (UL(0x2) << ID_AA64MMFR1_VMIDBits_SHIFT) 512#define ID_AA64MMFR1_VH_SHIFT 8 513#define ID_AA64MMFR1_VH_MASK (UL(0xf) << ID_AA64MMFR1_VH_SHIFT) 514#define ID_AA64MMFR1_VH_VAL(x) ((x) & ID_AA64MMFR1_VH_MASK) 515#define ID_AA64MMFR1_VH_NONE (UL(0x0) << ID_AA64MMFR1_VH_SHIFT) 516#define ID_AA64MMFR1_VH_IMPL (UL(0x1) << ID_AA64MMFR1_VH_SHIFT) 517#define ID_AA64MMFR1_HPDS_SHIFT 12 518#define ID_AA64MMFR1_HPDS_MASK (UL(0xf) << ID_AA64MMFR1_HPDS_SHIFT) 519#define ID_AA64MMFR1_HPDS_VAL(x) ((x) & ID_AA64MMFR1_HPDS_MASK) 520#define ID_AA64MMFR1_HPDS_NONE (UL(0x0) << ID_AA64MMFR1_HPDS_SHIFT) 521#define ID_AA64MMFR1_HPDS_HPD (UL(0x1) << ID_AA64MMFR1_HPDS_SHIFT) 522#define ID_AA64MMFR1_HPDS_TTPBHA (UL(0x2) << ID_AA64MMFR1_HPDS_SHIFT) 523#define ID_AA64MMFR1_LO_SHIFT 16 524#define ID_AA64MMFR1_LO_MASK (UL(0xf) << ID_AA64MMFR1_LO_SHIFT) 525#define ID_AA64MMFR1_LO_VAL(x) ((x) & ID_AA64MMFR1_LO_MASK) 526#define ID_AA64MMFR1_LO_NONE (UL(0x0) << ID_AA64MMFR1_LO_SHIFT) 527#define ID_AA64MMFR1_LO_IMPL (UL(0x1) << ID_AA64MMFR1_LO_SHIFT) 528#define ID_AA64MMFR1_PAN_SHIFT 20 529#define ID_AA64MMFR1_PAN_MASK (UL(0xf) << ID_AA64MMFR1_PAN_SHIFT) 530#define ID_AA64MMFR1_PAN_VAL(x) ((x) & ID_AA64MMFR1_PAN_MASK) 531#define ID_AA64MMFR1_PAN_NONE (UL(0x0) << ID_AA64MMFR1_PAN_SHIFT) 532#define ID_AA64MMFR1_PAN_IMPL (UL(0x1) << ID_AA64MMFR1_PAN_SHIFT) 533#define ID_AA64MMFR1_PAN_ATS1E1 (UL(0x2) << ID_AA64MMFR1_PAN_SHIFT) 534#define ID_AA64MMFR1_SpecSEI_SHIFT 24 535#define ID_AA64MMFR1_SpecSEI_MASK (UL(0xf) << ID_AA64MMFR1_SpecSEI_SHIFT) 536#define ID_AA64MMFR1_SpecSEI_VAL(x) ((x) & ID_AA64MMFR1_SpecSEI_MASK) 537#define ID_AA64MMFR1_SpecSEI_NONE (UL(0x0) << ID_AA64MMFR1_SpecSEI_SHIFT) 538#define ID_AA64MMFR1_SpecSEI_IMPL (UL(0x1) << ID_AA64MMFR1_SpecSEI_SHIFT) 539#define ID_AA64MMFR1_XNX_SHIFT 28 540#define ID_AA64MMFR1_XNX_MASK (UL(0xf) << ID_AA64MMFR1_XNX_SHIFT) 541#define ID_AA64MMFR1_XNX_VAL(x) ((x) & ID_AA64MMFR1_XNX_MASK) 542#define ID_AA64MMFR1_XNX_NONE (UL(0x0) << ID_AA64MMFR1_XNX_SHIFT) 543#define ID_AA64MMFR1_XNX_IMPL (UL(0x1) << ID_AA64MMFR1_XNX_SHIFT) 544 545/* ID_AA64MMFR2_EL1 */ 546#define ID_AA64MMFR2_EL1 MRS_REG(3, 0, 0, 7, 2) 547#define ID_AA64MMFR2_CnP_SHIFT 0 548#define ID_AA64MMFR2_CnP_MASK (UL(0xf) << ID_AA64MMFR2_CnP_SHIFT) 549#define ID_AA64MMFR2_CnP_VAL(x) ((x) & ID_AA64MMFR2_CnP_MASK) 550#define ID_AA64MMFR2_CnP_NONE (UL(0x0) << ID_AA64MMFR2_CnP_SHIFT) 551#define ID_AA64MMFR2_CnP_IMPL (UL(0x1) << ID_AA64MMFR2_CnP_SHIFT) 552#define ID_AA64MMFR2_UAO_SHIFT 4 553#define ID_AA64MMFR2_UAO_MASK (UL(0xf) << ID_AA64MMFR2_UAO_SHIFT) 554#define ID_AA64MMFR2_UAO_VAL(x) ((x) & ID_AA64MMFR2_UAO_MASK) 555#define ID_AA64MMFR2_UAO_NONE (UL(0x0) << ID_AA64MMFR2_UAO_SHIFT) 556#define ID_AA64MMFR2_UAO_IMPL (UL(0x1) << ID_AA64MMFR2_UAO_SHIFT) 557#define ID_AA64MMFR2_LSM_SHIFT 8 558#define ID_AA64MMFR2_LSM_MASK (UL(0xf) << ID_AA64MMFR2_LSM_SHIFT) 559#define ID_AA64MMFR2_LSM_VAL(x) ((x) & ID_AA64MMFR2_LSM_MASK) 560#define ID_AA64MMFR2_LSM_NONE (UL(0x0) << ID_AA64MMFR2_LSM_SHIFT) 561#define ID_AA64MMFR2_LSM_IMPL (UL(0x1) << ID_AA64MMFR2_LSM_SHIFT) 562#define ID_AA64MMFR2_IESB_SHIFT 12 563#define ID_AA64MMFR2_IESB_MASK (UL(0xf) << ID_AA64MMFR2_IESB_SHIFT) 564#define ID_AA64MMFR2_IESB_VAL(x) ((x) & ID_AA64MMFR2_IESB_MASK) 565#define ID_AA64MMFR2_IESB_NONE (UL(0x0) << ID_AA64MMFR2_IESB_SHIFT) 566#define ID_AA64MMFR2_IESB_IMPL (UL(0x1) << ID_AA64MMFR2_IESB_SHIFT) 567#define ID_AA64MMFR2_VARange_SHIFT 16 568#define ID_AA64MMFR2_VARange_MASK (UL(0xf) << ID_AA64MMFR2_VARange_SHIFT) 569#define ID_AA64MMFR2_VARange_VAL(x) ((x) & ID_AA64MMFR2_VARange_MASK) 570#define ID_AA64MMFR2_VARange_48 (UL(0x0) << ID_AA64MMFR2_VARange_SHIFT) 571#define ID_AA64MMFR2_VARange_52 (UL(0x1) << ID_AA64MMFR2_VARange_SHIFT) 572#define ID_AA64MMFR2_CCIDX_SHIFT 20 573#define ID_AA64MMFR2_CCIDX_MASK (UL(0xf) << ID_AA64MMFR2_CCIDX_SHIFT) 574#define ID_AA64MMFR2_CCIDX_VAL(x) ((x) & ID_AA64MMFR2_CCIDX_MASK) 575#define ID_AA64MMFR2_CCIDX_32 (UL(0x0) << ID_AA64MMFR2_CCIDX_SHIFT) 576#define ID_AA64MMFR2_CCIDX_64 (UL(0x1) << ID_AA64MMFR2_CCIDX_SHIFT) 577#define ID_AA64MMFR2_NV_SHIFT 24 578#define ID_AA64MMFR2_NV_MASK (UL(0xf) << ID_AA64MMFR2_NV_SHIFT) 579#define ID_AA64MMFR2_NV_VAL(x) ((x) & ID_AA64MMFR2_NV_MASK) 580#define ID_AA64MMFR2_NV_NONE (UL(0x0) << ID_AA64MMFR2_NV_SHIFT) 581#define ID_AA64MMFR2_NV_IMPL (UL(0x1) << ID_AA64MMFR2_NV_SHIFT) 582#define ID_AA64MMFR2_ST_SHIFT 28 583#define ID_AA64MMFR2_ST_MASK (UL(0xf) << ID_AA64MMFR2_ST_SHIFT) 584#define ID_AA64MMFR2_ST_VAL(x) ((x) & ID_AA64MMFR2_ST_MASK) 585#define ID_AA64MMFR2_ST_NONE (UL(0x0) << ID_AA64MMFR2_ST_SHIFT) 586#define ID_AA64MMFR2_ST_IMPL (UL(0x1) << ID_AA64MMFR2_ST_SHIFT) 587#define ID_AA64MMFR2_AT_SHIFT 32 588#define ID_AA64MMFR2_AT_MASK (UL(0xf) << ID_AA64MMFR2_AT_SHIFT) 589#define ID_AA64MMFR2_AT_VAL(x) ((x) & ID_AA64MMFR2_AT_MASK) 590#define ID_AA64MMFR2_AT_NONE (UL(0x0) << ID_AA64MMFR2_AT_SHIFT) 591#define ID_AA64MMFR2_AT_IMPL (UL(0x1) << ID_AA64MMFR2_AT_SHIFT) 592#define ID_AA64MMFR2_IDS_SHIFT 36 593#define ID_AA64MMFR2_IDS_MASK (UL(0xf) << ID_AA64MMFR2_IDS_SHIFT) 594#define ID_AA64MMFR2_IDS_VAL(x) ((x) & ID_AA64MMFR2_IDS_MASK) 595#define ID_AA64MMFR2_IDS_NONE (UL(0x0) << ID_AA64MMFR2_IDS_SHIFT) 596#define ID_AA64MMFR2_IDS_IMPL (UL(0x1) << ID_AA64MMFR2_IDS_SHIFT) 597#define ID_AA64MMFR2_FWB_SHIFT 40 598#define ID_AA64MMFR2_FWB_MASK (UL(0xf) << ID_AA64MMFR2_FWB_SHIFT) 599#define ID_AA64MMFR2_FWB_VAL(x) ((x) & ID_AA64MMFR2_FWB_MASK) 600#define ID_AA64MMFR2_FWB_NONE (UL(0x0) << ID_AA64MMFR2_FWB_SHIFT) 601#define ID_AA64MMFR2_FWB_IMPL (UL(0x1) << ID_AA64MMFR2_FWB_SHIFT) 602#define ID_AA64MMFR2_TTL_SHIFT 48 603#define ID_AA64MMFR2_TTL_MASK (UL(0xf) << ID_AA64MMFR2_TTL_SHIFT) 604#define ID_AA64MMFR2_TTL_VAL(x) ((x) & ID_AA64MMFR2_TTL_MASK) 605#define ID_AA64MMFR2_TTL_NONE (UL(0x0) << ID_AA64MMFR2_TTL_SHIFT) 606#define ID_AA64MMFR2_TTL_IMPL (UL(0x1) << ID_AA64MMFR2_TTL_SHIFT) 607#define ID_AA64MMFR2_BBM_SHIFT 52 608#define ID_AA64MMFR2_BBM_MASK (UL(0xf) << ID_AA64MMFR2_BBM_SHIFT) 609#define ID_AA64MMFR2_BBM_VAL(x) ((x) & ID_AA64MMFR2_BBM_MASK) 610#define ID_AA64MMFR2_BBM_LEVEL0 (UL(0x0) << ID_AA64MMFR2_BBM_SHIFT) 611#define ID_AA64MMFR2_BBM_LEVEL1 (UL(0x1) << ID_AA64MMFR2_BBM_SHIFT) 612#define ID_AA64MMFR2_BBM_LEVEL2 (UL(0x2) << ID_AA64MMFR2_BBM_SHIFT) 613#define ID_AA64MMFR2_EVT_SHIFT 56 614#define ID_AA64MMFR2_EVT_MASK (UL(0xf) << ID_AA64MMFR2_EVT_SHIFT) 615#define ID_AA64MMFR2_EVT_VAL(x) ((x) & ID_AA64MMFR2_EVT_MASK) 616#define ID_AA64MMFR2_EVT_NONE (UL(0x0) << ID_AA64MMFR2_EVT_SHIFT) 617#define ID_AA64MMFR2_EVT_8_2 (UL(0x1) << ID_AA64MMFR2_EVT_SHIFT) 618#define ID_AA64MMFR2_EVT_8_5 (UL(0x2) << ID_AA64MMFR2_EVT_SHIFT) 619#define ID_AA64MMFR2_E0PD_SHIFT 60 620#define ID_AA64MMFR2_E0PD_MASK (UL(0xf) << ID_AA64MMFR2_E0PD_SHIFT) 621#define ID_AA64MMFR2_E0PD_VAL(x) ((x) & ID_AA64MMFR2_E0PD_MASK) 622#define ID_AA64MMFR2_E0PD_NONE (UL(0x0) << ID_AA64MMFR2_E0PD_SHIFT) 623#define ID_AA64MMFR2_E0PD_IMPL (UL(0x1) << ID_AA64MMFR2_E0PD_SHIFT) 624 625/* ID_AA64PFR0_EL1 */ 626#define ID_AA64PFR0_EL1 MRS_REG(3, 0, 0, 4, 0) 627#define ID_AA64PFR0_EL0_SHIFT 0 628#define ID_AA64PFR0_EL0_MASK (UL(0xf) << ID_AA64PFR0_EL0_SHIFT) 629#define ID_AA64PFR0_EL0_VAL(x) ((x) & ID_AA64PFR0_EL0_MASK) 630#define ID_AA64PFR0_EL0_64 (UL(0x1) << ID_AA64PFR0_EL0_SHIFT) 631#define ID_AA64PFR0_EL0_64_32 (UL(0x2) << ID_AA64PFR0_EL0_SHIFT) 632#define ID_AA64PFR0_EL1_SHIFT 4 633#define ID_AA64PFR0_EL1_MASK (UL(0xf) << ID_AA64PFR0_EL1_SHIFT) 634#define ID_AA64PFR0_EL1_VAL(x) ((x) & ID_AA64PFR0_EL1_MASK) 635#define ID_AA64PFR0_EL1_64 (UL(0x1) << ID_AA64PFR0_EL1_SHIFT) 636#define ID_AA64PFR0_EL1_64_32 (UL(0x2) << ID_AA64PFR0_EL1_SHIFT) 637#define ID_AA64PFR0_EL2_SHIFT 8 638#define ID_AA64PFR0_EL2_MASK (UL(0xf) << ID_AA64PFR0_EL2_SHIFT) 639#define ID_AA64PFR0_EL2_VAL(x) ((x) & ID_AA64PFR0_EL2_MASK) 640#define ID_AA64PFR0_EL2_NONE (UL(0x0) << ID_AA64PFR0_EL2_SHIFT) 641#define ID_AA64PFR0_EL2_64 (UL(0x1) << ID_AA64PFR0_EL2_SHIFT) 642#define ID_AA64PFR0_EL2_64_32 (UL(0x2) << ID_AA64PFR0_EL2_SHIFT) 643#define ID_AA64PFR0_EL3_SHIFT 12 644#define ID_AA64PFR0_EL3_MASK (UL(0xf) << ID_AA64PFR0_EL3_SHIFT) 645#define ID_AA64PFR0_EL3_VAL(x) ((x) & ID_AA64PFR0_EL3_MASK) 646#define ID_AA64PFR0_EL3_NONE (UL(0x0) << ID_AA64PFR0_EL3_SHIFT) 647#define ID_AA64PFR0_EL3_64 (UL(0x1) << ID_AA64PFR0_EL3_SHIFT) 648#define ID_AA64PFR0_EL3_64_32 (UL(0x2) << ID_AA64PFR0_EL3_SHIFT) 649#define ID_AA64PFR0_FP_SHIFT 16 650#define ID_AA64PFR0_FP_MASK (UL(0xf) << ID_AA64PFR0_FP_SHIFT) 651#define ID_AA64PFR0_FP_VAL(x) ((x) & ID_AA64PFR0_FP_MASK) 652#define ID_AA64PFR0_FP_IMPL (UL(0x0) << ID_AA64PFR0_FP_SHIFT) 653#define ID_AA64PFR0_FP_HP (UL(0x1) << ID_AA64PFR0_FP_SHIFT) 654#define ID_AA64PFR0_FP_NONE (UL(0xf) << ID_AA64PFR0_FP_SHIFT) 655#define ID_AA64PFR0_AdvSIMD_SHIFT 20 656#define ID_AA64PFR0_AdvSIMD_MASK (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT) 657#define ID_AA64PFR0_AdvSIMD_VAL(x) ((x) & ID_AA64PFR0_AdvSIMD_MASK) 658#define ID_AA64PFR0_AdvSIMD_IMPL (UL(0x0) << ID_AA64PFR0_AdvSIMD_SHIFT) 659#define ID_AA64PFR0_AdvSIMD_HP (UL(0x1) << ID_AA64PFR0_AdvSIMD_SHIFT) 660#define ID_AA64PFR0_AdvSIMD_NONE (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT) 661#define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ 662#define ID_AA64PFR0_GIC_SHIFT 24 663#define ID_AA64PFR0_GIC_MASK (UL(0xf) << ID_AA64PFR0_GIC_SHIFT) 664#define ID_AA64PFR0_GIC_VAL(x) ((x) & ID_AA64PFR0_GIC_MASK) 665#define ID_AA64PFR0_GIC_CPUIF_NONE (UL(0x0) << ID_AA64PFR0_GIC_SHIFT) 666#define ID_AA64PFR0_GIC_CPUIF_EN (UL(0x1) << ID_AA64PFR0_GIC_SHIFT) 667#define ID_AA64PFR0_RAS_SHIFT 28 668#define ID_AA64PFR0_RAS_MASK (UL(0xf) << ID_AA64PFR0_RAS_SHIFT) 669#define ID_AA64PFR0_RAS_VAL(x) ((x) & ID_AA64PFR0_RAS_MASK) 670#define ID_AA64PFR0_RAS_NONE (UL(0x0) << ID_AA64PFR0_RAS_SHIFT) 671#define ID_AA64PFR0_RAS_V1 (UL(0x1) << ID_AA64PFR0_RAS_SHIFT) 672#define ID_AA64PFR0_SVE_SHIFT 32 673#define ID_AA64PFR0_SVE_MASK (UL(0xf) << ID_AA64PFR0_SVE_SHIFT) 674#define ID_AA64PFR0_SVE_VAL(x) ((x) & ID_AA64PFR0_SVE_MASK) 675#define ID_AA64PFR0_SVE_NONE (UL(0x0) << ID_AA64PFR0_SVE_SHIFT) 676#define ID_AA64PFR0_SVE_IMPL (UL(0x1) << ID_AA64PFR0_SVE_SHIFT) 677#define ID_AA64PFR0_SEL2_SHIFT 36 678#define ID_AA64PFR0_SEL2_MASK (UL(0xf) << ID_AA64PFR0_SEL2_SHIFT) 679#define ID_AA64PFR0_SEL2_VAL(x) ((x) & ID_AA64PFR0_SEL2_MASK) 680#define ID_AA64PFR0_SEL2_NONE (UL(0x0) << ID_AA64PFR0_SEL2_SHIFT) 681#define ID_AA64PFR0_SEL2_IMPL (UL(0x1) << ID_AA64PFR0_SEL2_SHIFT) 682#define ID_AA64PFR0_MPAM_SHIFT 40 683#define ID_AA64PFR0_MPAM_MASK (UL(0xf) << ID_AA64PFR0_MPAM_SHIFT) 684#define ID_AA64PFR0_MPAM_VAL(x) ((x) & ID_AA64PFR0_MPAM_MASK) 685#define ID_AA64PFR0_MPAM_NONE (UL(0x0) << ID_AA64PFR0_MPAM_SHIFT) 686#define ID_AA64PFR0_MPAM_IMPL (UL(0x1) << ID_AA64PFR0_MPAM_SHIFT) 687#define ID_AA64PFR0_AMU_SHIFT 44 688#define ID_AA64PFR0_AMU_MASK (UL(0xf) << ID_AA64PFR0_AMU_SHIFT) 689#define ID_AA64PFR0_AMU_VAL(x) ((x) & ID_AA64PFR0_AMU_MASK) 690#define ID_AA64PFR0_AMU_NONE (UL(0x0) << ID_AA64PFR0_AMU_SHIFT) 691#define ID_AA64PFR0_AMU_V1 (UL(0x1) << ID_AA64PFR0_AMU_SHIFT) 692#define ID_AA64PFR0_DIT_SHIFT 48 693#define ID_AA64PFR0_DIT_MASK (UL(0xf) << ID_AA64PFR0_DIT_SHIFT) 694#define ID_AA64PFR0_DIT_VAL(x) ((x) & ID_AA64PFR0_DIT_MASK) 695#define ID_AA64PFR0_DIT_NONE (UL(0x0) << ID_AA64PFR0_DIT_SHIFT) 696#define ID_AA64PFR0_DIT_PSTATE (UL(0x1) << ID_AA64PFR0_DIT_SHIFT) 697#define ID_AA64PFR0_CSV2_SHIFT 56 698#define ID_AA64PFR0_CSV2_MASK (UL(0xf) << ID_AA64PFR0_CSV2_SHIFT) 699#define ID_AA64PFR0_CSV2_VAL(x) ((x) & ID_AA64PFR0_CSV2_MASK) 700#define ID_AA64PFR0_CSV2_NONE (UL(0x0) << ID_AA64PFR0_CSV2_SHIFT) 701#define ID_AA64PFR0_CSV2_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV2_SHIFT) 702#define ID_AA64PFR0_CSV2_SCXTNUM (UL(0x2) << ID_AA64PFR0_CSV2_SHIFT) 703#define ID_AA64PFR0_CSV3_SHIFT 60 704#define ID_AA64PFR0_CSV3_MASK (UL(0xf) << ID_AA64PFR0_CSV3_SHIFT) 705#define ID_AA64PFR0_CSV3_VAL(x) ((x) & ID_AA64PFR0_CSV3_MASK) 706#define ID_AA64PFR0_CSV3_NONE (UL(0x0) << ID_AA64PFR0_CSV3_SHIFT) 707#define ID_AA64PFR0_CSV3_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV3_SHIFT) 708 709/* ID_AA64PFR1_EL1 */ 710#define ID_AA64PFR1_EL1 MRS_REG(3, 0, 0, 4, 1) 711#define ID_AA64PFR1_BT_SHIFT 0 712#define ID_AA64PFR1_BT_MASK (UL(0xf) << ID_AA64PFR1_BT_SHIFT) 713#define ID_AA64PFR1_BT_VAL(x) ((x) & ID_AA64PFR1_BT_MASK) 714#define ID_AA64PFR1_BT_NONE (UL(0x0) << ID_AA64PFR1_BT_SHIFT) 715#define ID_AA64PFR1_BT_IMPL (UL(0x1) << ID_AA64PFR1_BT_SHIFT) 716#define ID_AA64PFR1_SSBS_SHIFT 4 717#define ID_AA64PFR1_SSBS_MASK (UL(0xf) << ID_AA64PFR1_SSBS_SHIFT) 718#define ID_AA64PFR1_SSBS_VAL(x) ((x) & ID_AA64PFR1_SSBS_MASK) 719#define ID_AA64PFR1_SSBS_NONE (UL(0x0) << ID_AA64PFR1_SSBS_SHIFT) 720#define ID_AA64PFR1_SSBS_PSTATE (UL(0x1) << ID_AA64PFR1_SSBS_SHIFT) 721#define ID_AA64PFR1_SSBS_PSTATE_MSR (UL(0x2) << ID_AA64PFR1_SSBS_SHIFT) 722#define ID_AA64PFR1_MTE_SHIFT 8 723#define ID_AA64PFR1_MTE_MASK (UL(0xf) << ID_AA64PFR1_MTE_SHIFT) 724#define ID_AA64PFR1_MTE_VAL(x) ((x) & ID_AA64PFR1_MTE_MASK) 725#define ID_AA64PFR1_MTE_NONE (UL(0x0) << ID_AA64PFR1_MTE_SHIFT) 726#define ID_AA64PFR1_MTE_IMPL_EL0 (UL(0x1) << ID_AA64PFR1_MTE_SHIFT) 727#define ID_AA64PFR1_MTE_IMPL (UL(0x2) << ID_AA64PFR1_MTE_SHIFT) 728#define ID_AA64PFR1_RAS_frac_SHIFT 12 729#define ID_AA64PFR1_RAS_frac_MASK (UL(0xf) << ID_AA64PFR1_RAS_frac_SHIFT) 730#define ID_AA64PFR1_RAS_frac_VAL(x) ((x) & ID_AA64PFR1_RAS_frac_MASK) 731#define ID_AA64PFR1_RAS_frac_V1 (UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT) 732#define ID_AA64PFR1_RAS_frac_V2 (UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT) 733 734/* MAIR_EL1 - Memory Attribute Indirection Register */ 735#define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) 736#define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) 737#define MAIR_DEVICE_nGnRnE 0x00 738#define MAIR_NORMAL_NC 0x44 739#define MAIR_NORMAL_WT 0xbb 740#define MAIR_NORMAL_WB 0xff 741 742/* PAR_EL1 - Physical Address Register */ 743#define PAR_F_SHIFT 0 744#define PAR_F (0x1 << PAR_F_SHIFT) 745#define PAR_SUCCESS(x) (((x) & PAR_F) == 0) 746/* When PAR_F == 0 (success) */ 747#define PAR_LOW_MASK 0xfff 748#define PAR_SH_SHIFT 7 749#define PAR_SH_MASK (0x3 << PAR_SH_SHIFT) 750#define PAR_NS_SHIFT 9 751#define PAR_NS_MASK (0x3 << PAR_NS_SHIFT) 752#define PAR_PA_SHIFT 12 753#define PAR_PA_MASK 0x0000fffffffff000 754#define PAR_ATTR_SHIFT 56 755#define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT) 756/* When PAR_F == 1 (aborted) */ 757#define PAR_FST_SHIFT 1 758#define PAR_FST_MASK (0x3f << PAR_FST_SHIFT) 759#define PAR_PTW_SHIFT 8 760#define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT) 761#define PAR_S_SHIFT 9 762#define PAR_S_MASK (0x1 << PAR_S_SHIFT) 763 764/* SCTLR_EL1 - System Control Register */ 765#define SCTLR_RES0 0xc8222440 /* Reserved ARMv8.0, write 0 */ 766#define SCTLR_RES1 0x30d00800 /* Reserved ARMv8.0, write 1 */ 767 768#define SCTLR_M 0x00000001 769#define SCTLR_A 0x00000002 770#define SCTLR_C 0x00000004 771#define SCTLR_SA 0x00000008 772#define SCTLR_SA0 0x00000010 773#define SCTLR_CP15BEN 0x00000020 774/* Bit 6 is reserved */ 775#define SCTLR_ITD 0x00000080 776#define SCTLR_SED 0x00000100 777#define SCTLR_UMA 0x00000200 778/* Bit 10 is reserved */ 779/* Bit 11 is reserved */ 780#define SCTLR_I 0x00001000 781#define SCTLR_EnDB 0x00002000 /* ARMv8.3 */ 782#define SCTLR_DZE 0x00004000 783#define SCTLR_UCT 0x00008000 784#define SCTLR_nTWI 0x00010000 785/* Bit 17 is reserved */ 786#define SCTLR_nTWE 0x00040000 787#define SCTLR_WXN 0x00080000 788/* Bit 20 is reserved */ 789#define SCTLR_IESB 0x00200000 /* ARMv8.2 */ 790/* Bit 22 is reserved */ 791#define SCTLR_SPAN 0x00800000 /* ARMv8.1 */ 792#define SCTLR_EOE 0x01000000 793#define SCTLR_EE 0x02000000 794#define SCTLR_UCI 0x04000000 795#define SCTLR_EnDA 0x08000000 /* ARMv8.3 */ 796#define SCTLR_nTLSMD 0x10000000 /* ARMv8.2 */ 797#define SCTLR_LSMAOE 0x20000000 /* ARMv8.2 */ 798#define SCTLR_EnIB 0x40000000 /* ARMv8.3 */ 799#define SCTLR_EnIA 0x80000000 /* ARMv8.3 */ 800 801/* SPSR_EL1 */ 802/* 803 * When the exception is taken in AArch64: 804 * M[3:2] is the exception level 805 * M[1] is unused 806 * M[0] is the SP select: 807 * 0: always SP0 808 * 1: current ELs SP 809 */ 810#define PSR_M_EL0t 0x00000000 811#define PSR_M_EL1t 0x00000004 812#define PSR_M_EL1h 0x00000005 813#define PSR_M_EL2t 0x00000008 814#define PSR_M_EL2h 0x00000009 815#define PSR_M_64 0x00000000 816#define PSR_M_32 0x00000010 817#define PSR_M_MASK 0x0000000f 818 819#define PSR_T 0x00000020 820 821#define PSR_AARCH32 0x00000010 822#define PSR_F 0x00000040 823#define PSR_I 0x00000080 824#define PSR_A 0x00000100 825#define PSR_D 0x00000200 826#define PSR_DAIF (PSR_D | PSR_A | PSR_I | PSR_F) 827#define PSR_IL 0x00100000 828#define PSR_SS 0x00200000 829#define PSR_V 0x10000000 830#define PSR_C 0x20000000 831#define PSR_Z 0x40000000 832#define PSR_N 0x80000000 833#define PSR_FLAGS 0xf0000000 834 835/* TCR_EL1 - Translation Control Register */ 836/* Bits 63:59 are reserved */ 837#define TCR_TCMA1_SHIFT 58 838#define TCR_TCMA1 (1UL << TCR_TCMA1_SHIFT) 839#define TCR_TCMA0_SHIFT 57 840#define TCR_TCMA0 (1UL << TCR_TCMA0_SHIFT) 841#define TCR_E0PD1_SHIFT 56 842#define TCR_E0PD1 (1UL << TCR_E0PD1_SHIFT) 843#define TCR_E0PD0_SHIFT 55 844#define TCR_E0PD0 (1UL << TCR_E0PD0_SHIFT) 845#define TCR_NFD1_SHIFT 54 846#define TCR_NFD1 (1UL << TCR_NFD1_SHIFT) 847#define TCR_NFD0_SHIFT 53 848#define TCR_NFD0 (1UL << TCR_NFD0_SHIFT) 849#define TCR_TBID1_SHIFT 52 850#define TCR_TBID1 (1UL << TCR_TBID1_SHIFT) 851#define TCR_TBID0_SHIFT 51 852#define TCR_TBID0 (1UL << TCR_TBID0_SHIFT) 853#define TCR_HWU162_SHIFT 50 854#define TCR_HWU162 (1UL << TCR_HWU162_SHIFT) 855#define TCR_HWU161_SHIFT 49 856#define TCR_HWU161 (1UL << TCR_HWU161_SHIFT) 857#define TCR_HWU160_SHIFT 48 858#define TCR_HWU160 (1UL << TCR_HWU160_SHIFT) 859#define TCR_HWU159_SHIFT 47 860#define TCR_HWU159 (1UL << TCR_HWU159_SHIFT) 861#define TCR_HWU1 \ 862 (TCR_HWU159 | TCR_HWU160 | TCR_HWU161 | TCR_HWU162) 863#define TCR_HWU062_SHIFT 46 864#define TCR_HWU062 (1UL << TCR_HWU062_SHIFT) 865#define TCR_HWU061_SHIFT 45 866#define TCR_HWU061 (1UL << TCR_HWU061_SHIFT) 867#define TCR_HWU060_SHIFT 44 868#define TCR_HWU060 (1UL << TCR_HWU060_SHIFT) 869#define TCR_HWU059_SHIFT 43 870#define TCR_HWU059 (1UL << TCR_HWU059_SHIFT) 871#define TCR_HWU0 \ 872 (TCR_HWU059 | TCR_HWU060 | TCR_HWU061 | TCR_HWU062) 873#define TCR_HPD1_SHIFT 42 874#define TCR_HPD1 (1UL << TCR_HPD1_SHIFT) 875#define TCR_HPD0_SHIFT 41 876#define TCR_HPD0 (1UL << TCR_HPD0_SHIFT) 877#define TCR_HD_SHIFT 40 878#define TCR_HD (1UL << TCR_HD_SHIFT) 879#define TCR_HA_SHIFT 39 880#define TCR_HA (1UL << TCR_HA_SHIFT) 881#define TCR_TBI1_SHIFT 38 882#define TCR_TBI1 (1UL << TCR_TBI1_SHIFT) 883#define TCR_TBI0_SHIFT 37 884#define TCR_TBI0 (1U << TCR_TBI0_SHIFT) 885#define TCR_ASID_SHIFT 36 886#define TCR_ASID_WIDTH 1 887#define TCR_ASID_16 (1UL << TCR_ASID_SHIFT) 888/* Bit 35 is reserved */ 889#define TCR_IPS_SHIFT 32 890#define TCR_IPS_WIDTH 3 891#define TCR_IPS_32BIT (0UL << TCR_IPS_SHIFT) 892#define TCR_IPS_36BIT (1UL << TCR_IPS_SHIFT) 893#define TCR_IPS_40BIT (2UL << TCR_IPS_SHIFT) 894#define TCR_IPS_42BIT (3UL << TCR_IPS_SHIFT) 895#define TCR_IPS_44BIT (4UL << TCR_IPS_SHIFT) 896#define TCR_IPS_48BIT (5UL << TCR_IPS_SHIFT) 897#define TCR_TG1_SHIFT 30 898#define TCR_TG1_16K (1UL << TCR_TG1_SHIFT) 899#define TCR_TG1_4K (2UL << TCR_TG1_SHIFT) 900#define TCR_TG1_64K (3UL << TCR_TG1_SHIFT) 901#define TCR_SH1_SHIFT 28 902#define TCR_SH1_IS (3UL << TCR_SH1_SHIFT) 903#define TCR_ORGN1_SHIFT 26 904#define TCR_ORGN1_WBWA (1UL << TCR_ORGN1_SHIFT) 905#define TCR_IRGN1_SHIFT 24 906#define TCR_IRGN1_WBWA (1UL << TCR_IRGN1_SHIFT) 907#define TCR_EPD1_SHIFT 23 908#define TCR_EPD1 (1UL << TCR_EPD1_SHIFT) 909#define TCR_A1_SHIFT 22 910#define TCR_A1 (0x1UL << TCR_A1_SHIFT) 911#define TCR_T1SZ_SHIFT 16 912#define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) 913#define TCR_TG0_SHIFT 14 914#define TCR_TG0_16K (1UL << TCR_TG0_SHIFT) 915#define TCR_TG0_4K (2UL << TCR_TG0_SHIFT) 916#define TCR_TG0_64K (3UL << TCR_TG0_SHIFT) 917#define TCR_SH0_SHIFT 12 918#define TCR_SH0_IS (3UL << TCR_SH0_SHIFT) 919#define TCR_ORGN0_SHIFT 10 920#define TCR_ORGN0_WBWA (1UL << TCR_ORGN0_SHIFT) 921#define TCR_IRGN0_SHIFT 8 922#define TCR_IRGN0_WBWA (1UL << TCR_IRGN0_SHIFT) 923#define TCR_EPD0_SHIFT 7 924#define TCR_EPD0 (1UL << TCR_EPD1_SHIFT) 925/* Bit 6 is reserved */ 926#define TCR_T0SZ_SHIFT 0 927#define TCR_T0SZ_MASK 0x3f 928#define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) 929#define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) 930 931#define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\ 932 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)) 933#ifdef SMP 934#define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS) 935#else 936#define TCR_SMP_ATTRS 0 937#endif 938 939/* Saved Program Status Register */ 940#define DBG_SPSR_SS (0x1 << 21) 941 942/* Monitor Debug System Control Register */ 943#define DBG_MDSCR_SS (0x1 << 0) 944#define DBG_MDSCR_KDE (0x1 << 13) 945#define DBG_MDSCR_MDE (0x1 << 15) 946 947/* Debug Breakpoint Control Registers */ 948#define DBG_BCR_EN 0x1 949#define DBG_BCR_PMC_SHIFT 1 950#define DBG_BCR_PMC (0x3 << DBG_BCR_PMC_SHIFT) 951#define DBG_BCR_PMC_EL1 (0x1 << DBG_BCR_PMC_SHIFT) 952#define DBG_BCR_PMC_EL0 (0x2 << DBG_BCR_PMC_SHIFT) 953#define DBG_BCR_BAS_SHIFT 5 954#define DBG_BCR_BAS (0xf << DBG_BCR_BAS_SHIFT) 955#define DBG_BCR_HMC_SHIFT 13 956#define DBG_BCR_HMC (0x1 << DBG_BCR_HMC_SHIFT) 957#define DBG_BCR_SSC_SHIFT 14 958#define DBG_BCR_SSC (0x3 << DBG_BCR_SSC_SHIFT) 959#define DBG_BCR_LBN_SHIFT 16 960#define DBG_BCR_LBN (0xf << DBG_BCR_LBN_SHIFT) 961#define DBG_BCR_BT_SHIFT 20 962#define DBG_BCR_BT (0xf << DBG_BCR_BT_SHIFT) 963 964/* Debug Watchpoint Control Registers */ 965#define DBG_WCR_EN 0x1 966#define DBG_WCR_PAC_SHIFT 1 967#define DBG_WCR_PAC (0x3 << DBG_WCR_PAC_SHIFT) 968#define DBG_WCR_PAC_EL1 (0x1 << DBG_WCR_PAC_SHIFT) 969#define DBG_WCR_PAC_EL0 (0x2 << DBG_WCR_PAC_SHIFT) 970#define DBG_WCR_LSC_SHIFT 3 971#define DBG_WCR_LSC (0x3 << DBG_WCR_LSC_SHIFT) 972#define DBG_WCR_BAS_SHIFT 5 973#define DBG_WCR_BAS (0xff << DBG_WCR_BAS_SHIFT) 974#define DBG_WCR_BAS_MASK DBG_WCR_BAS 975#define DBG_WCR_HMC_SHIFT 13 976#define DBG_WCR_HMC (0x1 << DBG_WCR_HMC_SHIFT) 977#define DBG_WCR_SSC_SHIFT 14 978#define DBG_WCR_SSC (0x3 << DBG_WCR_SSC_SHIFT) 979#define DBG_WCR_LBN_SHIFT 16 980#define DBG_WCR_LBN (0xf << DBG_WCR_LBN_SHIFT) 981#define DBG_WCR_WT_SHIFT 20 982#define DBG_WCR_WT (0x1 << DBG_WCR_WT_SHIFT) 983#define DBG_WCR_MASK_SHIFT 24 984#define DBG_WCR_MASK (0x1f << DBG_WCR_MASK_SHIFT) 985 986/* Perfomance Monitoring Counters */ 987#define PMCR_E (1 << 0) /* Enable all counters */ 988#define PMCR_P (1 << 1) /* Reset all counters */ 989#define PMCR_C (1 << 2) /* Clock counter reset */ 990#define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ 991#define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ 992#define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ 993#define PMCR_LC (1 << 6) /* Long cycle count enable */ 994#define PMCR_IMP_SHIFT 24 /* Implementer code */ 995#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) 996#define PMCR_IMP_ARM 0x41 997#define PMCR_IDCODE_SHIFT 16 /* Identification code */ 998#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) 999#define PMCR_IDCODE_CORTEX_A57 0x01 1000#define PMCR_IDCODE_CORTEX_A72 0x02 1001#define PMCR_IDCODE_CORTEX_A53 0x03 1002#define PMCR_IDCODE_CORTEX_A73 0x04 1003#define PMCR_IDCODE_CORTEX_A35 0x0a 1004#define PMCR_IDCODE_CORTEX_A76 0x0b 1005#define PMCR_IDCODE_NEOVERSE_N1 0x0c 1006#define PMCR_IDCODE_CORTEX_A77 0x10 1007#define PMCR_IDCODE_CORTEX_A55 0x45 1008#define PMCR_IDCODE_NEOVERSE_E1 0x46 1009#define PMCR_IDCODE_CORTEX_A75 0x4a 1010#define PMCR_N_SHIFT 11 /* Number of counters implemented */ 1011#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) 1012 1013#endif /* !_MACHINE_ARMREG_H_ */ 1014