1/*- 2 * Copyright (c) 2018-2020 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by BAE Systems, the University of Cambridge 6 * Computer Laboratory, and Memorial University under DARPA/AFRL contract 7 * FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing 8 * (TC) research program. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34#ifndef _ARM64_CORESIGHT_ETM4X_H_ 35#define _ARM64_CORESIGHT_ETM4X_H_ 36 37#define TRCPRGCTLR 0x004 /* Trace Programming Control Register */ 38#define TRCPRGCTLR_EN (1 << 0) /* Trace unit enable bit */ 39#define TRCPROCSELR 0x008 /* Trace PE Select Control Register */ 40#define TRCSTATR 0x00C /* Trace Trace Status Register */ 41#define TRCSTATR_PMSTABLE (1 << 1) /* The programmers' model is stable. */ 42#define TRCSTATR_IDLE (1 << 0) /* The trace unit is idle. */ 43#define TRCCONFIGR 0x010 /* Trace Trace Configuration Register */ 44#define TRCCONFIGR_DV (1 << 17) /* Data value tracing is enabled when INSTP0 is not 0b00 */ 45#define TRCCONFIGR_DA (1 << 16) /* Data address tracing is enabled when INSTP0 is not 0b00. */ 46#define TRCCONFIGR_VMIDOPT (1 << 15) /* Control bit to configure the Virtual context identifier value */ 47#define TRCCONFIGR_QE_S 13 /* Q element enable field */ 48#define TRCCONFIGR_QE_M (0x3 << TRCCONFIGR_QE_S) 49#define TRCCONFIGR_RS (1 << 12) /* Return stack enable bit */ 50#define TRCCONFIGR_TS (1 << 11) /* Global timestamp tracing is enabled. */ 51#define TRCCONFIGR_COND_S 8 /* Conditional instruction tracing bit. */ 52#define TRCCONFIGR_COND_M (0x7 << TRCCONFIGR_COND_S) 53#define TRCCONFIGR_COND_DIS 0 54#define TRCCONFIGR_COND_LDR (1 << TRCCONFIGR_COND_S) /* Conditional load instructions are traced. */ 55#define TRCCONFIGR_COND_STR (2 << TRCCONFIGR_COND_S) /* Conditional store instructions are traced. */ 56#define TRCCONFIGR_COND_LDRSTR (3 << TRCCONFIGR_COND_S) /* Conditional load and store instructions are traced. */ 57#define TRCCONFIGR_COND_ALL (7 << TRCCONFIGR_COND_S) /* All conditional instructions are traced. */ 58#define TRCCONFIGR_VMID (1 << 7) /* Virtual context identifier tracing is enabled. */ 59#define TRCCONFIGR_CID (1 << 6) /* Context ID tracing is enabled. */ 60#define TRCCONFIGR_CCI (1 << 4) /* Cycle counting in the instruction trace is enabled. */ 61#define TRCCONFIGR_BB (1 << 3) /* Branch broadcast mode is enabled. */ 62#define TRCCONFIGR_INSTP0_S 1 /* Instruction P0 field. */ 63#define TRCCONFIGR_INSTP0_M (0x3 << TRCCONFIGR_INSTP0_S) 64#define TRCCONFIGR_INSTP0_NONE 0 /* Do not trace load and store instructions as P0 instructions. */ 65#define TRCCONFIGR_INSTP0_LDR (1 << TRCCONFIGR_INSTP0_S) /* Trace load instructions as P0 instructions. */ 66#define TRCCONFIGR_INSTP0_STR (2 << TRCCONFIGR_INSTP0_S) /* Trace store instructions as P0 instructions. */ 67#define TRCCONFIGR_INSTP0_LDRSTR (3 << TRCCONFIGR_INSTP0_S) /* Trace load and store instructions as P0 instr. */ 68#define TRCAUXCTLR 0x018 /* Trace Auxiliary Control Register */ 69#define TRCEVENTCTL0R 0x020 /* Trace Event Control 0 Register */ 70#define TRCEVENTCTL1R 0x024 /* Trace Event Control 1 Register */ 71#define TRCSTALLCTLR 0x02C /* Trace Stall Control Register */ 72#define TRCTSCTLR 0x030 /* Trace Global Timestamp Control Register */ 73#define TRCSYNCPR 0x034 /* Trace Synchronization Period Register */ 74#define TRCSYNCPR_PERIOD_S 0 75#define TRCSYNCPR_PERIOD_M 0x1f 76#define TRCSYNCPR_1K (10 << TRCSYNCPR_PERIOD_S) 77#define TRCSYNCPR_2K (11 << TRCSYNCPR_PERIOD_S) 78#define TRCSYNCPR_4K (12 << TRCSYNCPR_PERIOD_S) 79#define TRCCCCTLR 0x038 /* Trace Cycle Count Control Register */ 80#define TRCBBCTLR 0x03C /* Trace Branch Broadcast Control Register */ 81#define TRCTRACEIDR 0x040 /* Trace Trace ID Register */ 82#define TRCQCTLR 0x044 /* Trace Q Element Control Register */ 83#define TRCQCTLR_MODE_INC (1 << 8) /* Include mode. */ 84#define TRCVICTLR 0x080 /* Trace ViewInst Main Control Register */ 85#define TRCVICTLR_SSSTATUS (1 << 9) /* The start/stop logic is in the started state. */ 86#define TRCVICTLR_EXLEVEL_NS_S 20 87#define TRCVICTLR_EXLEVEL_NS_M (0xf << TRCVICTLR_EXLEVEL_NS_S) 88#define TRCVICTLR_EXLEVEL_NS(n) (0x1 << ((n) + TRCVICTLR_EXLEVEL_NS_S)) 89#define TRCVICTLR_EXLEVEL_S_S 16 90#define TRCVICTLR_EXLEVEL_S_M (0xf << TRCVICTLR_EXLEVEL_S_S) 91#define TRCVICTLR_EXLEVEL_S(n) (0x1 << ((n) + TRCVICTLR_EXLEVEL_S_S)) 92#define EVENT_SEL_S 0 93#define EVENT_SEL_M (0x1f << EVENT_SEL_S) 94#define TRCVIIECTLR 0x084 /* Trace ViewInst Include/Exclude Control Register */ 95#define TRCVIIECTLR_INCLUDE_S 0 96#define TRCVISSCTLR 0x088 /* Trace ViewInst Start/Stop Control Register */ 97#define TRCVIPCSSCTLR 0x08C /* Trace ViewInst Start/Stop PE Comparator Control Register */ 98#define TRCVDCTLR 0x0A0 /* Trace ViewData Main Control Register */ 99#define TRCVDCTLR_TRCEXDATA (1 << 12) /* Exception and exception return data transfers are traced */ 100#define TRCVDCTLR_TBI (1 << 11) /* The trace unit assigns bits[63:56] to have the same value as bits[63:56] of the data address. */ 101#define TRCVDCTLR_PCREL (1 << 10) /* The trace unit does not trace the address or value portions of PC-relative transfers. */ 102#define TRCVDCTLR_SPREL_S 8 103#define TRCVDCTLR_SPREL_M (0x3 << TRCVDCTLR_SPREL_S) 104#define TRCVDCTLR_EVENT_S 0 105#define TRCVDCTLR_EVENT_M (0xff << TRCVDCTLR_EVENT_S) 106#define TRCVDSACCTLR 0x0A4 /* Trace ViewData Include/Exclude Single Address Comparator Control Register */ 107#define TRCVDARCCTLR 0x0A8 /* Trace ViewData Include/Exclude Address Range Comparator Control Register */ 108#define TRCSEQEVR(n) (0x100 + (n) * 0x4) /* Trace Sequencer State Transition Control Register [n=0-2] */ 109#define TRCSEQRSTEVR 0x118 /* Trace Sequencer Reset Control Register */ 110#define TRCSEQSTR 0x11C /* Trace Sequencer State Register */ 111#define TRCEXTINSELR 0x120 /* Trace External Input Select Register */ 112#define TRCCNTRLDVR(n) (0x140 + (n) * 0x4) /* 32 Trace Counter Reload Value Register [n=0-3] */ 113#define TRCCNTCTLR(n) (0x150 + (n) * 0x4) /* 32 Trace Counter Control Register [n=0-3] */ 114#define TRCCNTVR(n) (0x160 + (n) * 0x4) /* 32 Trace Counter Value Register [n=0-3] */ 115#define TRCIMSPEC(n) (0x1C0 + (n) * 0x4) /* Trace IMPLEMENTATION DEFINED register [n=0-7] */ 116 117#define TRCIDR0(n) (0x1E0 + 0x4 * (n)) 118#define TRCIDR8(n) (0x180 + 0x4 * (n)) 119#define TRCIDR(n) ((n > 7) ? TRCIDR8(n) : TRCIDR0(n)) 120#define TRCIDR1_TRCARCHMAJ_S 8 121#define TRCIDR1_TRCARCHMAJ_M (0xf << TRCIDR1_TRCARCHMAJ_S) 122#define TRCIDR1_TRCARCHMIN_S 4 123#define TRCIDR1_TRCARCHMIN_M (0xf << TRCIDR1_TRCARCHMIN_S) 124 125#define TRCRSCTLR(n) (0x200 + (n) * 0x4) /* Trace Resource Selection Control Register [n=2-31] */ 126#define TRCSSCCR(n) (0x280 + (n) * 0x4) /* Trace Single-shot Comparator Control Register [n=0-7] */ 127#define TRCSSCSR(n) (0x2A0 + (n) * 0x4) /* Trace Single-shot Comparator Status Register [n=0-7] */ 128#define TRCSSPCICR(n) (0x2C0 + (n) * 0x4) /* Trace Single-shot PE Comparator Input Control [n=0-7] */ 129#define TRCOSLAR 0x300 /* Management OS Lock Access Register */ 130#define TRCOSLSR 0x304 /* Management OS Lock Status Register */ 131#define TRCPDCR 0x310 /* Management PowerDown Control Register */ 132#define TRCPDSR 0x314 /* Management PowerDown Status Register */ 133#define TRCACVR(n) (0x400 + (n) * 0x8) /* Trace Address Comparator Value Register [n=0-15] */ 134#define TRCACATR(n) (0x480 + (n) * 0x8) /* Trace Address Comparator Access Type Register [n=0-15] */ 135#define TRCACATR_DTBM (1 << 21) 136#define TRCACATR_DATARANGE (1 << 20) 137#define TRCACATR_DATASIZE_S 18 138#define TRCACATR_DATASIZE_M (0x3 << TRCACATR_DATASIZE_S) 139#define TRCACATR_DATASIZE_B (0x0 << TRCACATR_DATASIZE_S) 140#define TRCACATR_DATASIZE_HW (0x1 << TRCACATR_DATASIZE_S) 141#define TRCACATR_DATASIZE_W (0x2 << TRCACATR_DATASIZE_S) 142#define TRCACATR_DATASIZE_DW (0x3 << TRCACATR_DATASIZE_S) 143#define TRCACATR_DATAMATCH_S 16 144#define TRCACATR_DATAMATCH_M (0x3 << TRCACATR_DATAMATCH_S) 145#define TRCACATR_EXLEVEL_S_S 8 146#define TRCACATR_EXLEVEL_S_M (0xf << TRCACATR_EXLEVEL_S_S) 147#define TRCACATR_EXLEVEL_S(n) (0x1 << ((n) + TRCACATR_EXLEVEL_S_S)) 148#define TRCACATR_EXLEVEL_NS_S 12 149#define TRCACATR_EXLEVEL_NS_M (0xf << TRCACATR_EXLEVEL_NS_S) 150#define TRCACATR_EXLEVEL_NS(n) (0x1 << ((n) + TRCACATR_EXLEVEL_NS_S)) 151#define TRCDVCVR(n) (0x500 + (n) * 0x8) /* Trace Data Value Comparator Value Register [n=0-7] */ 152#define TRCDVCMR(n) (0x580 + (n) * 0x8) /* Trace Data Value Comparator Mask Register [n=0-7] */ 153#define TRCCIDCVR(n) (0x600 + (n) * 0x8) /* Trace Context ID Comparator Value Register [n=0-7] */ 154#define TRCVMIDCVR(n) (0x640 + (n) * 0x8) /* Trace Virtual context identifier Comparator Value [n=0-7] */ 155#define TRCCIDCCTLR0 0x680 /* Trace Context ID Comparator Control Register 0 */ 156#define TRCCIDCCTLR1 0x684 /* Trace Context ID Comparator Control Register 1 */ 157#define TRCVMIDCCTLR0 0x688 /* Trace Virtual context identifier Comparator Control Register 0 */ 158#define TRCVMIDCCTLR1 0x68C /* Trace Virtual context identifier Comparator Control Register 1 */ 159#define TRCITCTRL 0xF00 /* Management Integration Mode Control register */ 160#define TRCCLAIMSET 0xFA0 /* Trace Claim Tag Set register */ 161#define TRCCLAIMCLR 0xFA4 /* Trace Claim Tag Clear register */ 162#define TRCDEVAFF0 0xFA8 /* Management Device Affinity register 0 */ 163#define TRCDEVAFF1 0xFAC /* Management Device Affinity register 1 */ 164#define TRCLAR 0xFB0 /* Management Software Lock Access Register */ 165#define TRCLSR 0xFB4 /* Management Software Lock Status Register */ 166#define TRCAUTHSTATUS 0xFB8 /* Management Authentication Status register */ 167#define TRCDEVARCH 0xFBC /* Management Device Architecture register */ 168#define TRCDEVID 0xFC8 /* Management Device ID register */ 169#define TRCDEVTYPE 0xFCC /* Management Device Type register */ 170#define TRCPIDR4 0xFD0 /* Management Peripheral ID4 Register */ 171#define TRCPIDR(n) (0xFE0 + (n) * 0x4) /* Management Peripheral IDn Register [n=0-3] */ 172#define TRCPIDR567(n) (0xFD4 + ((n) - 5) * 0x4) /* Management Peripheral ID5 to Peripheral ID7 Registers */ 173#define TRCCIDR(n) (0xFF0 + (n) * 0x4) /* Management Component IDn Register [n=0-4] */ 174 175DECLARE_CLASS(etm_driver); 176 177struct etm_softc { 178 struct resource *res; 179 struct coresight_platform_data *pdata; 180}; 181 182int etm_attach(device_t dev); 183 184#endif /* !_ARM64_CORESIGHT_ETM4X_H_ */ 185