1/*-
2 * Copyright (c) 2015,2016 Annapurna Labs Ltd. and affiliates
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * Alpine PCI/PCI-Express controller driver.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD$");
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/kernel.h>
39#include <sys/module.h>
40#include <sys/bus.h>
41#include <sys/rman.h>
42#include <sys/intr.h>
43
44#include <dev/ofw/openfirm.h>
45#include <dev/ofw/ofw_bus.h>
46#include <dev/ofw/ofw_bus_subr.h>
47#include <dev/pci/pci_host_generic.h>
48#include <dev/pci/pci_host_generic_fdt.h>
49#include <dev/pci/pcivar.h>
50#include <dev/pci/pcireg.h>
51
52#include "pcib_if.h"
53
54#include "contrib/alpine-hal/al_hal_unit_adapter_regs.h"
55#include "contrib/alpine-hal/al_hal_pcie.h"
56#include "contrib/alpine-hal/al_hal_pcie_axi_reg.h"
57
58#define ANNAPURNA_VENDOR_ID		0x1c36
59
60/* Forward prototypes */
61static int al_pcib_probe(device_t);
62static int al_pcib_attach(device_t);
63static void al_pcib_fixup(device_t);
64
65static struct ofw_compat_data compat_data[] = {
66	{"annapurna-labs,al-internal-pcie",	true},
67	{"annapurna-labs,alpine-internal-pcie",	true},
68	{NULL,					false}
69};
70
71/*
72 * Bus interface definitions.
73 */
74static device_method_t al_pcib_methods[] = {
75	/* Device interface */
76	DEVMETHOD(device_probe,			al_pcib_probe),
77	DEVMETHOD(device_attach,		al_pcib_attach),
78
79	DEVMETHOD_END
80};
81
82DEFINE_CLASS_1(pcib, al_pcib_driver, al_pcib_methods,
83    sizeof(struct generic_pcie_fdt_softc), generic_pcie_fdt_driver);
84
85static devclass_t anpa_pcib_devclass;
86
87DRIVER_MODULE(alpine_pcib, simplebus, al_pcib_driver, anpa_pcib_devclass, 0, 0);
88DRIVER_MODULE(alpine_pcib, ofwbus, al_pcib_driver, anpa_pcib_devclass, 0, 0);
89
90static int
91al_pcib_probe(device_t dev)
92{
93
94	if (!ofw_bus_status_okay(dev))
95		return (ENXIO);
96
97	if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
98		return (ENXIO);
99
100	device_set_desc(dev,
101	    "Annapurna-Labs Integrated Internal PCI-E Controller");
102	return (BUS_PROBE_DEFAULT);
103}
104
105static int
106al_pcib_attach(device_t dev)
107{
108	int rv;
109
110	rv = pci_host_generic_attach(dev);
111
112	/* Annapurna quirk: configure vendor-specific registers */
113	if (rv == 0)
114		al_pcib_fixup(dev);
115
116	return (rv);
117}
118
119static void
120al_pcib_fixup(device_t dev)
121{
122	uint32_t val;
123	uint16_t vid;
124	uint8_t hdrtype;
125	int bus, slot, func, maxfunc;
126
127	/* Fixup is only needed on bus 0 */
128	bus = 0;
129	for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
130		maxfunc = 0;
131		for (func = 0; func <= maxfunc; func++) {
132			hdrtype = PCIB_READ_CONFIG(dev, bus, slot, func,
133			    PCIR_HDRTYPE, 1);
134
135			if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
136				continue;
137
138			if (func == 0 && (hdrtype & PCIM_MFDEV) != 0)
139				maxfunc = PCI_FUNCMAX;
140
141			vid = PCIB_READ_CONFIG(dev, bus, slot, func,
142			    PCIR_VENDOR, 2);
143			if (vid == ANNAPURNA_VENDOR_ID) {
144				val = PCIB_READ_CONFIG(dev, bus, slot, func,
145				    AL_PCI_AXI_CFG_AND_CTR_0, 4);
146				val |= PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_AXUSER_MASK;
147				PCIB_WRITE_CONFIG(dev, bus, slot, func,
148				    AL_PCI_AXI_CFG_AND_CTR_0, val, 4);
149
150				val = PCIB_READ_CONFIG(dev, bus, slot, func,
151				    AL_PCI_APP_CONTROL, 4);
152				val &= ~0xffff;
153				val |= PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_SEL_TGTID_MASK;
154				PCIB_WRITE_CONFIG(dev, bus, slot, func,
155				    AL_PCI_APP_CONTROL, val, 4);
156			}
157		}
158	}
159}
160