1/*- 2 * Copyright (c) 2015 Luiz Otavio O Souza <loos@freebsd.org> All rights reserved. 3 * Copyright (c) 2014-2015 M. Warner Losh <imp@FreeBSD.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * The magic-bit-bang sequence used in this code may be based on a linux 27 * platform driver in the Allwinner SDK from Allwinner Technology Co., Ltd. 28 * www.allwinnertech.com, by Daniel Wang <danielwang@allwinnertech.com> 29 * though none of the original code was copied. 30 */ 31 32#include "opt_bus.h" 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD$"); 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/bus.h> 40#include <sys/rman.h> 41#include <sys/kernel.h> 42#include <sys/module.h> 43 44#include <machine/bus.h> 45#include <dev/ofw/ofw_bus.h> 46#include <dev/ofw/ofw_bus_subr.h> 47 48#include <dev/ahci/ahci.h> 49#include <dev/extres/clk/clk.h> 50#include <dev/extres/regulator/regulator.h> 51 52/* 53 * Allwinner a1x/a2x/a8x SATA attachment. This is just the AHCI register 54 * set with a few extra implementation-specific registers that need to 55 * be accounted for. There's only one PHY in the system, and it needs 56 * to be trained to bring the link up. In addition, there's some DMA 57 * specific things that need to be done as well. These things are also 58 * just about completely undocumented, except in ugly code in the Linux 59 * SDK Allwinner releases. 60 */ 61 62/* BITx -- Unknown bit that needs to be set/cleared at position x */ 63/* UFx -- Uknown multi-bit field frobbed during init */ 64#define AHCI_BISTAFR 0x00A0 65#define AHCI_BISTCR 0x00A4 66#define AHCI_BISTFCTR 0x00A8 67#define AHCI_BISTSR 0x00AC 68#define AHCI_BISTDECR 0x00B0 69#define AHCI_DIAGNR 0x00B4 70#define AHCI_DIAGNR1 0x00B8 71#define AHCI_OOBR 0x00BC 72#define AHCI_PHYCS0R 0x00C0 73/* Bits 0..17 are a mystery */ 74#define PHYCS0R_BIT18 (1 << 18) 75#define PHYCS0R_POWER_ENABLE (1 << 19) 76#define PHYCS0R_UF1_MASK (7 << 20) /* Unknown Field 1 */ 77#define PHYCS0R_UF1_INIT (3 << 20) 78#define PHYCS0R_BIT23 (1 << 23) 79#define PHYCS0R_UF2_MASK (7 << 24) /* Uknown Field 2 */ 80#define PHYCS0R_UF2_INIT (5 << 24) 81/* Bit 27 mystery */ 82#define PHYCS0R_POWER_STATUS_MASK (7 << 28) 83#define PHYCS0R_PS_GOOD (2 << 28) 84/* Bit 31 mystery */ 85#define AHCI_PHYCS1R 0x00C4 86/* Bits 0..5 are a mystery */ 87#define PHYCS1R_UF1_MASK (3 << 6) 88#define PHYCS1R_UF1_INIT (2 << 6) 89#define PHYCS1R_UF2_MASK (0x1f << 8) 90#define PHYCS1R_UF2_INIT (6 << 8) 91/* Bits 13..14 are a mystery */ 92#define PHYCS1R_BIT15 (1 << 15) 93#define PHYCS1R_UF3_MASK (3 << 16) 94#define PHYCS1R_UF3_INIT (2 << 16) 95/* Bit 18 mystery */ 96#define PHYCS1R_HIGHZ (1 << 19) 97/* Bits 20..27 mystery */ 98#define PHYCS1R_BIT28 (1 << 28) 99/* Bits 29..31 mystery */ 100#define AHCI_PHYCS2R 0x00C8 101/* bits 0..4 mystery */ 102#define PHYCS2R_UF1_MASK (0x1f << 5) 103#define PHYCS2R_UF1_INIT (0x19 << 5) 104/* Bits 10..23 mystery */ 105#define PHYCS2R_CALIBRATE (1 << 24) 106/* Bits 25..31 mystery */ 107#define AHCI_TIMER1MS 0x00E0 108#define AHCI_GPARAM1R 0x00E8 109#define AHCI_GPARAM2R 0x00EC 110#define AHCI_PPARAMR 0x00F0 111#define AHCI_TESTR 0x00F4 112#define AHCI_VERSIONR 0x00F8 113#define AHCI_IDR 0x00FC 114#define AHCI_RWCR 0x00FC 115 116#define AHCI_P0DMACR 0x0070 117#define AHCI_P0PHYCR 0x0078 118#define AHCI_P0PHYSR 0x007C 119 120#define PLL_FREQ 100000000 121 122struct ahci_a10_softc { 123 struct ahci_controller ahci_ctlr; 124 regulator_t ahci_reg; 125 clk_t clk_pll; 126 clk_t clk_gate; 127}; 128 129static void inline 130ahci_set(struct resource *m, bus_size_t off, uint32_t set) 131{ 132 uint32_t val = ATA_INL(m, off); 133 134 val |= set; 135 ATA_OUTL(m, off, val); 136} 137 138static void inline 139ahci_clr(struct resource *m, bus_size_t off, uint32_t clr) 140{ 141 uint32_t val = ATA_INL(m, off); 142 143 val &= ~clr; 144 ATA_OUTL(m, off, val); 145} 146 147static void inline 148ahci_mask_set(struct resource *m, bus_size_t off, uint32_t mask, uint32_t set) 149{ 150 uint32_t val = ATA_INL(m, off); 151 152 val &= mask; 153 val |= set; 154 ATA_OUTL(m, off, val); 155} 156 157/* 158 * Should this be phy_reset or phy_init 159 */ 160#define PHY_RESET_TIMEOUT 1000 161static void 162ahci_a10_phy_reset(device_t dev) 163{ 164 uint32_t to, val; 165 struct ahci_controller *ctlr = device_get_softc(dev); 166 167 /* 168 * Here starts the magic -- most of the comments are based 169 * on guesswork, names of routines and printf error 170 * messages. The code works, but it will do that even if the 171 * comments are 100% BS. 172 */ 173 174 /* 175 * Lock out other access while we initialize. Or at least that 176 * seems to be the case based on Linux SDK #defines. Maybe this 177 * put things into reset? 178 */ 179 ATA_OUTL(ctlr->r_mem, AHCI_RWCR, 0); 180 DELAY(100); 181 182 /* 183 * Set bit 19 in PHYCS1R. Guessing this disables driving the PHY 184 * port for a bit while we reset things. 185 */ 186 ahci_set(ctlr->r_mem, AHCI_PHYCS1R, PHYCS1R_HIGHZ); 187 188 /* 189 * Frob PHYCS0R... 190 */ 191 ahci_mask_set(ctlr->r_mem, AHCI_PHYCS0R, 192 ~PHYCS0R_UF2_MASK, 193 PHYCS0R_UF2_INIT | PHYCS0R_BIT23 | PHYCS0R_BIT18); 194 195 /* 196 * Set three fields in PHYCS1R 197 */ 198 ahci_mask_set(ctlr->r_mem, AHCI_PHYCS1R, 199 ~(PHYCS1R_UF1_MASK | PHYCS1R_UF2_MASK | PHYCS1R_UF3_MASK), 200 PHYCS1R_UF1_INIT | PHYCS1R_UF2_INIT | PHYCS1R_UF3_INIT); 201 202 /* 203 * Two more mystery bits in PHYCS1R. -- can these be combined above? 204 */ 205 ahci_set(ctlr->r_mem, AHCI_PHYCS1R, PHYCS1R_BIT15 | PHYCS1R_BIT28); 206 207 /* 208 * Now clear that first mysery bit. Perhaps this starts 209 * driving the PHY again so we can power it up and start 210 * talking to the SATA drive, if any below. 211 */ 212 ahci_clr(ctlr->r_mem, AHCI_PHYCS1R, PHYCS1R_HIGHZ); 213 214 /* 215 * Frob PHYCS0R again... 216 */ 217 ahci_mask_set(ctlr->r_mem, AHCI_PHYCS0R, 218 ~PHYCS0R_UF1_MASK, PHYCS0R_UF1_INIT); 219 220 /* 221 * Frob PHYCS2R, because 25 means something? 222 */ 223 ahci_mask_set(ctlr->r_mem, AHCI_PHYCS2R, ~PHYCS2R_UF1_MASK, 224 PHYCS2R_UF1_INIT); 225 226 DELAY(100); /* WAG */ 227 228 /* 229 * Turn on the power to the PHY and wait for it to report back 230 * good? 231 */ 232 ahci_set(ctlr->r_mem, AHCI_PHYCS0R, PHYCS0R_POWER_ENABLE); 233 for (to = PHY_RESET_TIMEOUT; to > 0; to--) { 234 val = ATA_INL(ctlr->r_mem, AHCI_PHYCS0R); 235 if ((val & PHYCS0R_POWER_STATUS_MASK) == PHYCS0R_PS_GOOD) 236 break; 237 DELAY(10); 238 } 239 if (to == 0 && bootverbose) 240 device_printf(dev, "PHY Power Failed PHYCS0R = %#x\n", val); 241 242 /* 243 * Calibrate the clocks between the device and the host. This appears 244 * to be an automated process that clears the bit when it is done. 245 */ 246 ahci_set(ctlr->r_mem, AHCI_PHYCS2R, PHYCS2R_CALIBRATE); 247 for (to = PHY_RESET_TIMEOUT; to > 0; to--) { 248 val = ATA_INL(ctlr->r_mem, AHCI_PHYCS2R); 249 if ((val & PHYCS2R_CALIBRATE) == 0) 250 break; 251 DELAY(10); 252 } 253 if (to == 0 && bootverbose) 254 device_printf(dev, "PHY Cal Failed PHYCS2R %#x\n", val); 255 256 /* 257 * OK, let things settle down a bit. 258 */ 259 DELAY(1000); 260 261 /* 262 * Go back into normal mode now that we've calibrated the PHY. 263 */ 264 ATA_OUTL(ctlr->r_mem, AHCI_RWCR, 7); 265} 266 267static void 268ahci_a10_ch_start(struct ahci_channel *ch) 269{ 270 uint32_t reg; 271 272 /* 273 * Magical values from Allwinner SDK, setup the DMA before start 274 * operations on this channel. 275 */ 276 reg = ATA_INL(ch->r_mem, AHCI_P0DMACR); 277 reg &= ~0xff00; 278 reg |= 0x4400; 279 ATA_OUTL(ch->r_mem, AHCI_P0DMACR, reg); 280} 281 282static int 283ahci_a10_ctlr_reset(device_t dev) 284{ 285 286 ahci_a10_phy_reset(dev); 287 288 return (ahci_ctlr_reset(dev)); 289} 290 291static int 292ahci_a10_probe(device_t dev) 293{ 294 295 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-ahci")) 296 return (ENXIO); 297 device_set_desc(dev, "Allwinner Integrated AHCI controller"); 298 299 return (BUS_PROBE_DEFAULT); 300} 301 302static int 303ahci_a10_attach(device_t dev) 304{ 305 int error; 306 struct ahci_a10_softc *sc; 307 struct ahci_controller *ctlr; 308 309 sc = device_get_softc(dev); 310 ctlr = &sc->ahci_ctlr; 311 312 ctlr->quirks = AHCI_Q_NOPMP; 313 ctlr->vendorid = 0; 314 ctlr->deviceid = 0; 315 ctlr->subvendorid = 0; 316 ctlr->subdeviceid = 0; 317 ctlr->r_rid = 0; 318 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 319 &ctlr->r_rid, RF_ACTIVE))) 320 return (ENXIO); 321 322 /* Enable the (optional) regulator */ 323 if (regulator_get_by_ofw_property(dev, 0, "target-supply", 324 &sc->ahci_reg) == 0) { 325 error = regulator_enable(sc->ahci_reg); 326 if (error != 0) { 327 device_printf(dev, "Could not enable regulator\n"); 328 goto fail; 329 } 330 } 331 332 /* Enable clocks */ 333 error = clk_get_by_ofw_index(dev, 0, 0, &sc->clk_gate); 334 if (error != 0) { 335 device_printf(dev, "Cannot get gate clock\n"); 336 goto fail; 337 } 338 error = clk_get_by_ofw_index(dev, 0, 1, &sc->clk_pll); 339 if (error != 0) { 340 device_printf(dev, "Cannot get PLL clock\n"); 341 goto fail; 342 } 343 error = clk_set_freq(sc->clk_pll, PLL_FREQ, CLK_SET_ROUND_DOWN); 344 if (error != 0) { 345 device_printf(dev, "Cannot set PLL frequency\n"); 346 goto fail; 347 } 348 error = clk_enable(sc->clk_pll); 349 if (error != 0) { 350 device_printf(dev, "Cannot enable PLL\n"); 351 goto fail; 352 } 353 error = clk_enable(sc->clk_gate); 354 if (error != 0) { 355 device_printf(dev, "Cannot enable clk gate\n"); 356 goto fail; 357 } 358 359 /* Reset controller */ 360 if ((error = ahci_a10_ctlr_reset(dev)) != 0) 361 goto fail; 362 363 /* 364 * No MSI registers on this platform. 365 */ 366 ctlr->msi = 0; 367 ctlr->numirqs = 1; 368 369 /* Channel start callback(). */ 370 ctlr->ch_start = ahci_a10_ch_start; 371 372 /* 373 * Note: ahci_attach will release ctlr->r_mem on errors automatically 374 */ 375 return (ahci_attach(dev)); 376 377fail: 378 if (sc->ahci_reg != NULL) 379 regulator_disable(sc->ahci_reg); 380 if (sc->clk_gate != NULL) 381 clk_release(sc->clk_gate); 382 if (sc->clk_pll != NULL) 383 clk_release(sc->clk_pll); 384 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 385 return (error); 386} 387 388static int 389ahci_a10_detach(device_t dev) 390{ 391 struct ahci_a10_softc *sc; 392 struct ahci_controller *ctlr; 393 394 sc = device_get_softc(dev); 395 ctlr = &sc->ahci_ctlr; 396 397 if (sc->ahci_reg != NULL) 398 regulator_disable(sc->ahci_reg); 399 if (sc->clk_gate != NULL) 400 clk_release(sc->clk_gate); 401 if (sc->clk_pll != NULL) 402 clk_release(sc->clk_pll); 403 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 404 return (ahci_detach(dev)); 405} 406 407static device_method_t ahci_ata_methods[] = { 408 DEVMETHOD(device_probe, ahci_a10_probe), 409 DEVMETHOD(device_attach, ahci_a10_attach), 410 DEVMETHOD(device_detach, ahci_a10_detach), 411 DEVMETHOD(bus_print_child, ahci_print_child), 412 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 413 DEVMETHOD(bus_release_resource, ahci_release_resource), 414 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 415 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 416 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 417 DEVMETHOD_END 418}; 419 420static driver_t ahci_ata_driver = { 421 "ahci", 422 ahci_ata_methods, 423 sizeof(struct ahci_a10_softc) 424}; 425 426DRIVER_MODULE(a10_ahci, simplebus, ahci_ata_driver, ahci_devclass, 0, 0); 427