1/*-
2 * Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by BAE Systems, the University of Cambridge
6 * Computer Laboratory, and Memorial University under DARPA/AFRL contract
7 * FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing
8 * (TC) research program.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * $FreeBSD$
32 */
33
34#ifndef _AMD64_SGX_SGXVAR_H_
35#define _AMD64_SGX_SGXVAR_H_
36
37#define	SGX_CPUID			0x12
38#define	SGX_PAGE_SIZE			4096
39#define	SGX_VA_PAGE_SLOTS		512
40#define	SGX_VA_PAGES_OFFS		512
41#define	SGX_SECS_VM_OBJECT_INDEX	-1
42#define	SGX_SIGSTRUCT_SIZE		1808
43#define	SGX_EINITTOKEN_SIZE		304
44#define	SGX_IOCTL_MAX_DATA_LEN		26
45#define	SGX_ENCL_SIZE_MAX_DEF		0x1000000000ULL
46#define	SGX_EFAULT			99
47
48#ifndef LOCORE
49static MALLOC_DEFINE(M_SGX, "sgx", "SGX driver");
50
51struct sgx_vm_handle {
52	struct sgx_softc	*sc;
53	vm_object_t		mem;
54	uint64_t		base;
55	vm_size_t		size;
56	struct sgx_enclave	*enclave;
57};
58
59/* EPC (Enclave Page Cache) page. */
60struct epc_page {
61	uint64_t		base;
62	uint64_t		phys;
63	int			index;
64};
65
66struct sgx_enclave {
67	uint64_t			base;
68	uint64_t			size;
69	struct sgx_vm_handle		*vmh;
70	TAILQ_ENTRY(sgx_enclave)	next;
71	vm_object_t			object;
72	struct epc_page			*secs_epc_page;
73};
74
75struct sgx_softc {
76	struct cdev			*sgx_cdev;
77	struct mtx			mtx_encls;
78	struct mtx			mtx;
79	uint64_t			epc_base;
80	uint64_t			epc_size;
81	struct epc_page			*epc_pages;
82	struct vmem			*vmem_epc;
83	uint32_t			npages;
84	TAILQ_HEAD(, sgx_enclave)	enclaves;
85	uint64_t			enclave_size_max;
86	uint8_t				state;
87#define	SGX_STATE_RUNNING		(1 << 0)
88};
89#endif /* !LOCORE */
90
91#endif /* !_AMD64_SGX_SGXVAR_H_ */
92