1/*!
2* \file       trc_mem_acc_cache.h
3* \brief      OpenCSD : Memory accessor cache.
4*
5* \copyright  Copyright (c) 2018, ARM Limited. All Rights Reserved.
6*/
7
8/*
9* Redistribution and use in source and binary forms, with or without modification,
10* are permitted provided that the following conditions are met:
11*
12* 1. Redistributions of source code must retain the above copyright notice,
13* this list of conditions and the following disclaimer.
14*
15* 2. Redistributions in binary form must reproduce the above copyright notice,
16* this list of conditions and the following disclaimer in the documentation
17* and/or other materials provided with the distribution.
18*
19* 3. Neither the name of the copyright holder nor the names of its contributors
20* may be used to endorse or promote products derived from this software without
21* specific prior written permission.
22*
23* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
24* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33*/
34
35#ifndef ARM_TRC_MEM_ACC_CACHE_H_INCLUDED
36#define ARM_TRC_MEM_ACC_CACHE_H_INCLUDED
37
38#include <string>
39#include "opencsd/ocsd_if_types.h"
40
41#define MEM_ACC_CACHE_PAGE_SIZE 256
42#define MEM_ACC_CACHE_MRU_SIZE 12
43
44class TrcMemAccessorBase;
45class ITraceErrorLog;
46
47typedef struct cache_block {
48    ocsd_vaddr_t st_addr;
49    uint32_t valid_len;
50    uint8_t data[MEM_ACC_CACHE_PAGE_SIZE];
51} cache_block_t;
52
53// enable define to collect stats for debugging / cache performance tests
54//#define LOG_CACHE_STATS
55
56
57/** class TrcMemAccCache - cache small amounts of data from accessors to speed up decode. */
58class TrcMemAccCache
59{
60public:
61    TrcMemAccCache();
62    ~TrcMemAccCache() {};
63
64    void enableCaching(bool bEnable) { m_bCacheEnabled = bEnable; };
65    void invalidateAll();
66    const bool enabled() const { return m_bCacheEnabled; };
67    const bool enabled_for_size(const uint32_t reqSize) const
68    {
69        return (m_bCacheEnabled && (reqSize <= MEM_ACC_CACHE_PAGE_SIZE));
70    }
71
72
73    /** read bytes from cache if possible - load new page if needed, bail out if data not available */
74    ocsd_err_t readBytesFromCache(TrcMemAccessorBase *p_accessor, const ocsd_vaddr_t address, const ocsd_mem_space_acc_t mem_space, const uint8_t trcID, uint32_t *numBytes, uint8_t *byteBuffer);
75
76    void setErrorLog(ITraceErrorLog *log);
77    void logAndClearCounts();
78
79private:
80    bool blockInCache(const ocsd_vaddr_t address, const uint32_t reqBytes); // run through each page to look for data.
81    bool blockInPage(const ocsd_vaddr_t address, const uint32_t reqBytes);
82    void logMsg(const std::string &szMsg);
83
84    cache_block_t m_mru[MEM_ACC_CACHE_MRU_SIZE];
85    int m_mru_idx = 0;  // in use index
86    int m_mru_next_new = 0; // next new page at this index.
87    bool m_bCacheEnabled = false;
88
89#ifdef LOG_CACHE_STATS
90    uint32_t m_hits = 0;
91    uint32_t m_misses = 0;
92    uint32_t m_pages = 0;
93    uint32_t m_hit_rl[MEM_ACC_CACHE_MRU_SIZE];
94    uint32_t m_hit_rl_max[MEM_ACC_CACHE_MRU_SIZE];
95#endif
96
97    ITraceErrorLog *m_err_log = 0;
98};
99
100inline TrcMemAccCache::TrcMemAccCache()
101{
102    for (int i = 0; i < MEM_ACC_CACHE_MRU_SIZE; i++)
103    {
104        m_mru[i].st_addr = 0;
105        m_mru[i].valid_len = 0;
106#ifdef LOG_CACHE_STATS
107        m_hit_rl[i] = 0;
108        m_hit_rl_max[i] = 0;
109#endif
110    }
111}
112
113inline bool TrcMemAccCache::blockInPage(const ocsd_vaddr_t address, const uint32_t reqBytes)
114{
115    if ((m_mru[m_mru_idx].st_addr <= address) &&
116        m_mru[m_mru_idx].st_addr + m_mru[m_mru_idx].valid_len >= (address + reqBytes))
117        return true;
118    return false;
119}
120
121inline bool TrcMemAccCache::blockInCache(const ocsd_vaddr_t address, const uint32_t reqBytes)
122{
123    int tests = MEM_ACC_CACHE_MRU_SIZE;
124    while (tests)
125    {
126        if (blockInPage(address, reqBytes))
127            return true; // found address in page
128        tests--;
129        m_mru_idx++;
130        if (m_mru_idx == MEM_ACC_CACHE_MRU_SIZE)
131            m_mru_idx = 0;
132    }
133    return false;
134}
135
136inline void TrcMemAccCache::invalidateAll()
137{
138    for (int i = 0; i < MEM_ACC_CACHE_MRU_SIZE; i++)
139    {
140        m_mru[i].valid_len = 0;
141        m_mru[i].st_addr = 0;
142    }
143    m_mru_idx = 0;
144    m_mru_next_new = 0;
145}
146
147#endif // ARM_TRC_MEM_ACC_CACHE_H_INCLUDED
148
149/* End of File trc_mem_acc_cache.h */
150