1//===- PseudoLoweringEmitter.cpp - PseudoLowering Generator -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "CodeGenInstruction.h"
10#include "CodeGenTarget.h"
11#include "llvm/ADT/IndexedMap.h"
12#include "llvm/ADT/SmallVector.h"
13#include "llvm/ADT/StringMap.h"
14#include "llvm/Support/Debug.h"
15#include "llvm/Support/ErrorHandling.h"
16#include "llvm/TableGen/Error.h"
17#include "llvm/TableGen/Record.h"
18#include "llvm/TableGen/TableGenBackend.h"
19#include <vector>
20using namespace llvm;
21
22#define DEBUG_TYPE "pseudo-lowering"
23
24namespace {
25class PseudoLoweringEmitter {
26  struct OpData {
27    enum MapKind { Operand, Imm, Reg };
28    MapKind Kind;
29    union {
30      unsigned Operand;   // Operand number mapped to.
31      uint64_t Imm;       // Integer immedate value.
32      Record *Reg;        // Physical register.
33    } Data;
34  };
35  struct PseudoExpansion {
36    CodeGenInstruction Source;  // The source pseudo instruction definition.
37    CodeGenInstruction Dest;    // The destination instruction to lower to.
38    IndexedMap<OpData> OperandMap;
39
40    PseudoExpansion(CodeGenInstruction &s, CodeGenInstruction &d,
41                    IndexedMap<OpData> &m) :
42      Source(s), Dest(d), OperandMap(m) {}
43  };
44
45  RecordKeeper &Records;
46
47  // It's overkill to have an instance of the full CodeGenTarget object,
48  // but it loads everything on demand, not in the constructor, so it's
49  // lightweight in performance, so it works out OK.
50  CodeGenTarget Target;
51
52  SmallVector<PseudoExpansion, 64> Expansions;
53
54  unsigned addDagOperandMapping(Record *Rec, DagInit *Dag,
55                                CodeGenInstruction &Insn,
56                                IndexedMap<OpData> &OperandMap,
57                                unsigned BaseIdx);
58  void evaluateExpansion(Record *Pseudo);
59  void emitLoweringEmitter(raw_ostream &o);
60public:
61  PseudoLoweringEmitter(RecordKeeper &R) : Records(R), Target(R) {}
62
63  /// run - Output the pseudo-lowerings.
64  void run(raw_ostream &o);
65};
66} // End anonymous namespace
67
68// FIXME: This pass currently can only expand a pseudo to a single instruction.
69//        The pseudo expansion really should take a list of dags, not just
70//        a single dag, so we can do fancier things.
71
72unsigned PseudoLoweringEmitter::
73addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn,
74                     IndexedMap<OpData> &OperandMap, unsigned BaseIdx) {
75  unsigned OpsAdded = 0;
76  for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) {
77    if (DefInit *DI = dyn_cast<DefInit>(Dag->getArg(i))) {
78      // Physical register reference. Explicit check for the special case
79      // "zero_reg" definition.
80      if (DI->getDef()->isSubClassOf("Register") ||
81          DI->getDef()->getName() == "zero_reg") {
82        OperandMap[BaseIdx + i].Kind = OpData::Reg;
83        OperandMap[BaseIdx + i].Data.Reg = DI->getDef();
84        ++OpsAdded;
85        continue;
86      }
87
88      // Normal operands should always have the same type, or we have a
89      // problem.
90      // FIXME: We probably shouldn't ever get a non-zero BaseIdx here.
91      assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!");
92      if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
93        PrintFatalError(Rec->getLoc(),
94                      "Pseudo operand type '" + DI->getDef()->getName() +
95                      "' does not match expansion operand type '" +
96                      Insn.Operands[BaseIdx + i].Rec->getName() + "'");
97      // Source operand maps to destination operand. The Data element
98      // will be filled in later, just set the Kind for now. Do it
99      // for each corresponding MachineInstr operand, not just the first.
100      for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
101        OperandMap[BaseIdx + i + I].Kind = OpData::Operand;
102      OpsAdded += Insn.Operands[i].MINumOperands;
103    } else if (IntInit *II = dyn_cast<IntInit>(Dag->getArg(i))) {
104      OperandMap[BaseIdx + i].Kind = OpData::Imm;
105      OperandMap[BaseIdx + i].Data.Imm = II->getValue();
106      ++OpsAdded;
107    } else if (DagInit *SubDag = dyn_cast<DagInit>(Dag->getArg(i))) {
108      // Just add the operands recursively. This is almost certainly
109      // a constant value for a complex operand (> 1 MI operand).
110      unsigned NewOps =
111        addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i);
112      OpsAdded += NewOps;
113      // Since we added more than one, we also need to adjust the base.
114      BaseIdx += NewOps - 1;
115    } else
116      llvm_unreachable("Unhandled pseudo-expansion argument type!");
117  }
118  return OpsAdded;
119}
120
121void PseudoLoweringEmitter::evaluateExpansion(Record *Rec) {
122  LLVM_DEBUG(dbgs() << "Pseudo definition: " << Rec->getName() << "\n");
123
124  // Validate that the result pattern has the corrent number and types
125  // of arguments for the instruction it references.
126  DagInit *Dag = Rec->getValueAsDag("ResultInst");
127  assert(Dag && "Missing result instruction in pseudo expansion!");
128  LLVM_DEBUG(dbgs() << "  Result: " << *Dag << "\n");
129
130  DefInit *OpDef = dyn_cast<DefInit>(Dag->getOperator());
131  if (!OpDef)
132    PrintFatalError(Rec->getLoc(), Rec->getName() +
133                  " has unexpected operator type!");
134  Record *Operator = OpDef->getDef();
135  if (!Operator->isSubClassOf("Instruction"))
136    PrintFatalError(Rec->getLoc(), "Pseudo result '" + Operator->getName() +
137                    "' is not an instruction!");
138
139  CodeGenInstruction Insn(Operator);
140
141  if (Insn.isCodeGenOnly || Insn.isPseudo)
142    PrintFatalError(Rec->getLoc(), "Pseudo result '" + Operator->getName() +
143                    "' cannot be another pseudo instruction!");
144
145  if (Insn.Operands.size() != Dag->getNumArgs())
146    PrintFatalError(Rec->getLoc(), "Pseudo result '" + Operator->getName() +
147                    "' operand count mismatch");
148
149  unsigned NumMIOperands = 0;
150  for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i)
151    NumMIOperands += Insn.Operands[i].MINumOperands;
152  IndexedMap<OpData> OperandMap;
153  OperandMap.grow(NumMIOperands);
154
155  addDagOperandMapping(Rec, Dag, Insn, OperandMap, 0);
156
157  // If there are more operands that weren't in the DAG, they have to
158  // be operands that have default values, or we have an error. Currently,
159  // Operands that are a subclass of OperandWithDefaultOp have default values.
160
161  // Validate that each result pattern argument has a matching (by name)
162  // argument in the source instruction, in either the (outs) or (ins) list.
163  // Also check that the type of the arguments match.
164  //
165  // Record the mapping of the source to result arguments for use by
166  // the lowering emitter.
167  CodeGenInstruction SourceInsn(Rec);
168  StringMap<unsigned> SourceOperands;
169  for (unsigned i = 0, e = SourceInsn.Operands.size(); i != e; ++i)
170    SourceOperands[SourceInsn.Operands[i].Name] = i;
171
172  LLVM_DEBUG(dbgs() << "  Operand mapping:\n");
173  for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) {
174    // We've already handled constant values. Just map instruction operands
175    // here.
176    if (OperandMap[Insn.Operands[i].MIOperandNo].Kind != OpData::Operand)
177      continue;
178    StringMap<unsigned>::iterator SourceOp =
179      SourceOperands.find(Dag->getArgNameStr(i));
180    if (SourceOp == SourceOperands.end())
181      PrintFatalError(Rec->getLoc(),
182                      "Pseudo output operand '" + Dag->getArgNameStr(i) +
183                      "' has no matching source operand.");
184    // Map the source operand to the destination operand index for each
185    // MachineInstr operand.
186    for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
187      OperandMap[Insn.Operands[i].MIOperandNo + I].Data.Operand =
188        SourceOp->getValue();
189
190    LLVM_DEBUG(dbgs() << "    " << SourceOp->getValue() << " ==> " << i
191                      << "\n");
192  }
193
194  Expansions.push_back(PseudoExpansion(SourceInsn, Insn, OperandMap));
195}
196
197void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
198  // Emit file header.
199  emitSourceFileHeader("Pseudo-instruction MC lowering Source Fragment", o);
200
201  o << "bool " << Target.getName() + "AsmPrinter" << "::\n"
202    << "emitPseudoExpansionLowering(MCStreamer &OutStreamer,\n"
203    << "                            const MachineInstr *MI) {\n";
204
205  if (!Expansions.empty()) {
206    o << "  switch (MI->getOpcode()) {\n"
207      << "    default: return false;\n";
208    for (auto &Expansion : Expansions) {
209      CodeGenInstruction &Source = Expansion.Source;
210      CodeGenInstruction &Dest = Expansion.Dest;
211      o << "    case " << Source.Namespace << "::"
212        << Source.TheDef->getName() << ": {\n"
213        << "      MCInst TmpInst;\n"
214        << "      MCOperand MCOp;\n"
215        << "      TmpInst.setOpcode(" << Dest.Namespace << "::"
216        << Dest.TheDef->getName() << ");\n";
217
218      // Copy the operands from the source instruction.
219      // FIXME: Instruction operands with defaults values (predicates and cc_out
220      //        in ARM, for example shouldn't need explicit values in the
221      //        expansion DAG.
222      unsigned MIOpNo = 0;
223      for (const auto &DestOperand : Dest.Operands) {
224        o << "      // Operand: " << DestOperand.Name << "\n";
225        for (unsigned i = 0, e = DestOperand.MINumOperands; i != e; ++i) {
226          switch (Expansion.OperandMap[MIOpNo + i].Kind) {
227            case OpData::Operand:
228            o << "      lowerOperand(MI->getOperand("
229              << Source.Operands[Expansion.OperandMap[MIOpNo].Data
230              .Operand].MIOperandNo + i
231              << "), MCOp);\n"
232              << "      TmpInst.addOperand(MCOp);\n";
233            break;
234            case OpData::Imm:
235            o << "      TmpInst.addOperand(MCOperand::createImm("
236              << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
237            break;
238            case OpData::Reg: {
239              Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
240              o << "      TmpInst.addOperand(MCOperand::createReg(";
241              // "zero_reg" is special.
242              if (Reg->getName() == "zero_reg")
243                o << "0";
244              else
245                o << Reg->getValueAsString("Namespace") << "::"
246                  << Reg->getName();
247              o << "));\n";
248              break;
249            }
250          }
251        }
252        MIOpNo += DestOperand.MINumOperands;
253      }
254      if (Dest.Operands.isVariadic) {
255        MIOpNo = Source.Operands.size() + 1;
256        o << "      // variable_ops\n";
257        o << "      for (unsigned i = " << MIOpNo
258          << ", e = MI->getNumOperands(); i != e; ++i)\n"
259          << "        if (lowerOperand(MI->getOperand(i), MCOp))\n"
260          << "          TmpInst.addOperand(MCOp);\n";
261      }
262      o << "      EmitToStreamer(OutStreamer, TmpInst);\n"
263        << "      break;\n"
264        << "    }\n";
265    }
266    o << "  }\n  return true;";
267  } else
268    o << "  return false;";
269
270  o << "\n}\n\n";
271}
272
273void PseudoLoweringEmitter::run(raw_ostream &o) {
274  Record *ExpansionClass = Records.getClass("PseudoInstExpansion");
275  Record *InstructionClass = Records.getClass("Instruction");
276  assert(ExpansionClass && "PseudoInstExpansion class definition missing!");
277  assert(InstructionClass && "Instruction class definition missing!");
278
279  std::vector<Record*> Insts;
280  for (const auto &D : Records.getDefs()) {
281    if (D.second->isSubClassOf(ExpansionClass) &&
282        D.second->isSubClassOf(InstructionClass))
283      Insts.push_back(D.second.get());
284  }
285
286  // Process the pseudo expansion definitions, validating them as we do so.
287  for (unsigned i = 0, e = Insts.size(); i != e; ++i)
288    evaluateExpansion(Insts[i]);
289
290  // Generate expansion code to lower the pseudo to an MCInst of the real
291  // instruction.
292  emitLoweringEmitter(o);
293}
294
295namespace llvm {
296
297void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS) {
298  PseudoLoweringEmitter(RK).run(OS);
299}
300
301} // End llvm namespace
302