1//===---- X86InstrAMX.td - AMX Instruction Set Extension --*- tablegen -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the instructions that make up the Intel AMX instruction
10// set.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// AMX instructions
16
17let Predicates = [HasAMXTILE, In64BitMode] in {
18  let SchedRW = [WriteSystem] in {
19    let Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
20    def LDTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
21                       "ldtilecfg\t$src",
22                       [(int_x86_ldtilecfg addr:$src)]>, VEX, T8PS;
23    def STTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
24                       "sttilecfg\t$src",
25                       [(int_x86_sttilecfg addr:$src)]>, VEX, T8PD;
26    def TILELOADD : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
27                      (ins sibmem:$src),
28                      "tileloadd\t{$src, $dst|$dst, $src}", []>,
29                      VEX, T8XD;
30    def TILELOADDT1 : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
31                        (ins sibmem:$src),
32                        "tileloaddt1\t{$src, $dst|$dst, $src}", []>,
33                        VEX, T8PD;
34    let Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
35    def TILERELEASE : I<0x49, MRM_C0, (outs), (ins),
36                        "tilerelease", [(int_x86_tilerelease)]>, VEX, T8PS;
37    def TILESTORED : I<0x4b, MRMDestMemFSIB, (outs),
38                       (ins sibmem:$dst, TILE:$src),
39                       "tilestored\t{$src, $dst|$dst, $src}", []>,
40                       VEX, T8XS;
41    def TILEZERO : I<0x49, MRMr0, (outs TILE:$dst), (ins),
42                     "tilezero\t$dst", []>,
43                     VEX, T8XD;
44
45    let usesCustomInserter = 1 in {
46      // Pseudo instructions, using immediates instead of tile registers.
47      // To be translated to the actual instructions in X86ISelLowering.cpp
48      def PTILELOADD : PseudoI<(outs), (ins u8imm:$src1, sibmem:$src2), []>;
49      def PTILELOADDT1 : PseudoI<(outs), (ins u8imm:$src1,
50                                          sibmem:$src2), []>;
51      def PTILESTORED : PseudoI<(outs), (ins i8mem:$dst, u8imm:$src), []>;
52      def PTILEZERO : PseudoI<(outs), (ins u8imm:$src),
53                              [(int_x86_tilezero imm:$src)]>;
54    }
55  } // SchedRW
56} // HasAMXTILE
57
58let Predicates = [HasAMXINT8, In64BitMode] in {
59  let SchedRW = [WriteSystem] in {
60    let Constraints = "$src1 = $dst" in {
61      def TDPBSSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
62                      (ins TILE:$src1, TILE:$src2, TILE:$src3),
63                      "tdpbssd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
64                      VEX_4V, T8XD;
65      def TDPBSUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
66                      (ins TILE:$src1, TILE:$src2, TILE:$src3),
67                      "tdpbsud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
68                      VEX_4V, T8XS;
69      def TDPBUSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
70                      (ins TILE:$src1, TILE:$src2, TILE:$src3),
71                      "tdpbusd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
72                      VEX_4V, T8PD;
73      def TDPBUUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
74                      (ins TILE:$src1, TILE:$src2, TILE:$src3),
75                      "tdpbuud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
76                      VEX_4V, T8PS;
77    }
78
79    let usesCustomInserter = 1 in {
80      // Pseudo instructions, using immediates instead of tile registers.
81      // To be translated to the actual instructions in X86ISelLowering.cpp
82      def PTDPBSSD : PseudoI<(outs), (ins u8imm:$src1,
83                             u8imm:$src2, u8imm:$src3),
84                             [(int_x86_tdpbssd imm:$src1,
85                               imm:$src2, imm:$src3)]>;
86      def PTDPBSUD : PseudoI<(outs), (ins u8imm:$src1,
87                             u8imm:$src2, u8imm:$src3),
88                             [(int_x86_tdpbsud imm:$src1,
89                               imm:$src2, imm:$src3)]>;
90      def PTDPBUSD : PseudoI<(outs), (ins u8imm:$src1,
91                             u8imm:$src2, u8imm:$src3),
92                             [(int_x86_tdpbusd imm:$src1,
93                               imm:$src2, imm:$src3)]>;
94      def PTDPBUUD : PseudoI<(outs), (ins u8imm:$src1,
95                             u8imm:$src2, u8imm:$src3),
96                             [(int_x86_tdpbuud imm:$src1,
97                               imm:$src2, imm:$src3)]>;
98    }
99  }
100} // HasAMXTILE
101
102let Predicates = [HasAMXBF16, In64BitMode] in {
103  let SchedRW = [WriteSystem] in {
104    let Constraints = "$src1 = $dst" in
105    def TDPBF16PS : I<0x5c, MRMSrcReg4VOp3, (outs TILE:$dst),
106                      (ins TILE:$src1, TILE:$src2, TILE:$src3),
107                      "tdpbf16ps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
108                      []>, VEX_4V, T8XS;
109
110    let usesCustomInserter = 1 in {
111      // Pseudo instructions, using immediates instead of tile registers.
112      // To be translated to the actual instructions in X86ISelLowering.cpp
113      def PTDPBF16PS : PseudoI<(outs), (ins u8imm:$src1,
114                               u8imm:$src2, u8imm:$src3),
115                               [(int_x86_tdpbf16ps imm:$src1,
116                                 imm:$src2, imm:$src3)]>;
117    }
118  }
119} // HasAMXTILE, HasAMXBF16
120