1//===- RISCVMatInt.h - Immediate materialisation ---------------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_RISCV_MATINT_H
10#define LLVM_LIB_TARGET_RISCV_MATINT_H
11
12#include "llvm/ADT/APInt.h"
13#include "llvm/ADT/SmallVector.h"
14#include "llvm/Support/MachineValueType.h"
15#include <cstdint>
16
17namespace llvm {
18
19namespace RISCVMatInt {
20struct Inst {
21  unsigned Opc;
22  int64_t Imm;
23
24  Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {}
25};
26using InstSeq = SmallVector<Inst, 8>;
27
28// Helper to generate an instruction sequence that will materialise the given
29// immediate value into a register. A sequence of instructions represented by
30// a simple struct produced rather than directly emitting the instructions in
31// order to allow this helper to be used from both the MC layer and during
32// instruction selection.
33void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res);
34
35// Helper to estimate the number of instructions required to materialise the
36// given immediate value into a register. This estimate does not account for
37// `Val` possibly fitting into an immediate, and so may over-estimate.
38//
39// This will attempt to produce instructions to materialise `Val` as an
40// `Size`-bit immediate. `IsRV64` should match the target architecture.
41int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64);
42} // namespace RISCVMatInt
43} // namespace llvm
44#endif
45