1//==- RISCVSchedRocket64.td - Rocket Scheduling Definitions -*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// ===---------------------------------------------------------------------===// 10// The following definitions describe the simpler per-operand machine model. 11// This works with MachineScheduler. See MCSchedule.h for details. 12 13// Rocket machine model for scheduling and other instruction cost heuristics. 14def Rocket64Model : SchedMachineModel { 15 let MicroOpBufferSize = 0; // Explicitly set to zero since Rocket is in-order. 16 let IssueWidth = 1; // 1 micro-ops are dispatched per cycle. 17 let LoadLatency = 3; 18 let MispredictPenalty = 3; 19 let UnsupportedFeatures = [HasStdExtV]; 20} 21 22//===----------------------------------------------------------------------===// 23// Define each kind of processor resource and number available. 24 25// Modeling each pipeline as a ProcResource using the BufferSize = 0 since 26// Rocket is in-order. 27 28let BufferSize = 0 in { 29def Rocket64UnitALU : ProcResource<1>; // Int ALU 30def Rocket64UnitIMul : ProcResource<1>; // Int Multiply 31def Rocket64UnitMem : ProcResource<1>; // Load/Store 32def Rocket64UnitB : ProcResource<1>; // Branch 33 34def Rocket64UnitFPALU : ProcResource<1>; // FP ALU 35} 36 37let BufferSize = 1 in { 38def Rocket64UnitIDiv : ProcResource<1>; // Int Division 39def Rocket64UnitFPDivSqrt : ProcResource<1>; // FP Divide/Sqrt 40} 41 42//===----------------------------------------------------------------------===// 43// Subtarget-specific SchedWrite types which both map the ProcResources and 44// set the latency. 45 46let SchedModel = Rocket64Model in { 47 48def : WriteRes<WriteJmp, [Rocket64UnitB]>; 49def : WriteRes<WriteJal, [Rocket64UnitB]>; 50def : WriteRes<WriteJalr, [Rocket64UnitB]>; 51def : WriteRes<WriteJmpReg, [Rocket64UnitB]>; 52 53def : WriteRes<WriteIALU32, [Rocket64UnitALU]>; 54def : WriteRes<WriteIALU, [Rocket64UnitALU]>; 55def : WriteRes<WriteShift32, [Rocket64UnitALU]>; 56def : WriteRes<WriteShift, [Rocket64UnitALU]>; 57 58let Latency = 4 in { 59def : WriteRes<WriteIMul, [Rocket64UnitIMul]>; 60def : WriteRes<WriteIMul32, [Rocket64UnitIMul]>; 61} 62 63// Integer divide varies based on operand magnitude and sign; worse case latency is 34. 64def : WriteRes<WriteIDiv32, [Rocket64UnitIDiv]> { 65 let Latency = 34; 66 let ResourceCycles = [34]; 67} 68def : WriteRes<WriteIDiv, [Rocket64UnitIDiv]> { 69 let Latency = 33; 70 let ResourceCycles = [33]; 71} 72 73// Memory 74def : WriteRes<WriteSTB, [Rocket64UnitMem]>; 75def : WriteRes<WriteSTH, [Rocket64UnitMem]>; 76def : WriteRes<WriteSTW, [Rocket64UnitMem]>; 77def : WriteRes<WriteSTD, [Rocket64UnitMem]>; 78def : WriteRes<WriteFST32, [Rocket64UnitMem]>; 79def : WriteRes<WriteFST64, [Rocket64UnitMem]>; 80 81let Latency = 3 in { 82def : WriteRes<WriteLDB, [Rocket64UnitMem]>; 83def : WriteRes<WriteLDH, [Rocket64UnitMem]>; 84def : WriteRes<WriteCSR, [Rocket64UnitALU]>; 85} 86 87let Latency = 2 in { 88def : WriteRes<WriteLDW, [Rocket64UnitMem]>; 89def : WriteRes<WriteLDWU, [Rocket64UnitMem]>; 90def : WriteRes<WriteLDD, [Rocket64UnitMem]>; 91def : WriteRes<WriteFLD32, [Rocket64UnitMem]>; 92def : WriteRes<WriteFLD64, [Rocket64UnitMem]>; 93 94def : WriteRes<WriteAtomicW, [Rocket64UnitMem]>; 95def : WriteRes<WriteAtomicD, [Rocket64UnitMem]>; 96 97def : WriteRes<WriteAtomicLDW, [Rocket64UnitMem]>; 98def : WriteRes<WriteAtomicLDD, [Rocket64UnitMem]>; 99} 100 101def : WriteRes<WriteAtomicSTW, [Rocket64UnitMem]>; 102def : WriteRes<WriteAtomicSTD, [Rocket64UnitMem]>; 103 104// Most FP single precision operations are 4 cycles 105let Latency = 4 in { 106def : WriteRes<WriteFALU32, [Rocket64UnitFPALU]>; 107def : WriteRes<WriteFSGNJ32, [Rocket64UnitFPALU]>; 108def : WriteRes<WriteFMinMax32, [Rocket64UnitFPALU]>; 109} 110 111let Latency = 6 in { 112// Most FP double precision operations are 6 cycles 113def : WriteRes<WriteFALU64, [Rocket64UnitFPALU]>; 114def : WriteRes<WriteFSGNJ64, [Rocket64UnitFPALU]>; 115def : WriteRes<WriteFMinMax64, [Rocket64UnitFPALU]>; 116} 117 118// Conversion instructions 119let Latency = 2 in { 120def : WriteRes<WriteFCvtI32ToF32, [Rocket32UnitFPALU]>; 121def : WriteRes<WriteFCvtI32ToF64, [Rocket32UnitFPALU]>; 122def : WriteRes<WriteFCvtI64ToF32, [Rocket32UnitFPALU]>; 123def : WriteRes<WriteFCvtI64ToF64, [Rocket32UnitFPALU]>; 124def : WriteRes<WriteFCvtF32ToI32, [Rocket32UnitFPALU]>; 125def : WriteRes<WriteFCvtF32ToI64, [Rocket32UnitFPALU]>; 126def : WriteRes<WriteFCvtF64ToI32, [Rocket32UnitFPALU]>; 127def : WriteRes<WriteFCvtF64ToI64, [Rocket32UnitFPALU]>; 128def : WriteRes<WriteFCvtF32ToF64, [Rocket32UnitFPALU]>; 129def : WriteRes<WriteFCvtF64ToF32, [Rocket32UnitFPALU]>; 130 131def : WriteRes<WriteFClass32, [Rocket64UnitFPALU]>; 132def : WriteRes<WriteFClass64, [Rocket64UnitFPALU]>; 133def : WriteRes<WriteFCmp32, [Rocket64UnitFPALU]>; 134def : WriteRes<WriteFCmp64, [Rocket64UnitFPALU]>; 135def : WriteRes<WriteFMovF32ToI32, [Rocket64UnitFPALU]>; 136def : WriteRes<WriteFMovI32ToF32, [Rocket64UnitFPALU]>; 137def : WriteRes<WriteFMovF64ToI64, [Rocket64UnitFPALU]>; 138def : WriteRes<WriteFMovI64ToF64, [Rocket64UnitFPALU]>; 139} 140 141let Latency = 5 in { 142def : WriteRes<WriteFMul32, [Rocket64UnitFPALU]>; 143def : WriteRes<WriteFMulAdd32, [Rocket64UnitFPALU]>; 144def : WriteRes<WriteFMulSub32, [Rocket64UnitFPALU]>; 145} 146 147let Latency = 7 in { 148def : WriteRes<WriteFMul64, [Rocket64UnitFPALU]>; 149def : WriteRes<WriteFMulAdd64, [Rocket64UnitFPALU]>; 150def : WriteRes<WriteFMulSub64, [Rocket64UnitFPALU]>; 151} 152 153// FP Divide unit on Rocket is not pipelined, so set resource cycles to latency 154let Latency = 20, ResourceCycles = [20] in { 155def : WriteRes<WriteFDiv32, [Rocket64UnitFPDivSqrt]>; 156def : WriteRes<WriteFDiv64, [Rocket64UnitFPDivSqrt]>; 157} 158 159// FP Sqrt unit on Rocket is not pipelined, so set resource cycles to latency 160def : WriteRes<WriteFSqrt32, [Rocket64UnitFPDivSqrt]> { let Latency = 20; 161 let ResourceCycles = [20]; } 162def : WriteRes<WriteFSqrt64, [Rocket64UnitFPDivSqrt]> { let Latency = 25; 163 let ResourceCycles = [25]; } 164 165def : WriteRes<WriteNop, []>; 166 167def : InstRW<[WriteIALU], (instrs COPY)>; 168 169//===----------------------------------------------------------------------===// 170// Subtarget-specific SchedRead types with cycles. 171// Dummy definitions for RocketCore. 172def : ReadAdvance<ReadJmp, 0>; 173def : ReadAdvance<ReadJalr, 0>; 174def : ReadAdvance<ReadCSR, 0>; 175def : ReadAdvance<ReadStoreData, 0>; 176def : ReadAdvance<ReadMemBase, 0>; 177def : ReadAdvance<ReadIALU, 0>; 178def : ReadAdvance<ReadIALU32, 0>; 179def : ReadAdvance<ReadShift, 0>; 180def : ReadAdvance<ReadShift32, 0>; 181def : ReadAdvance<ReadIDiv, 0>; 182def : ReadAdvance<ReadIDiv32, 0>; 183def : ReadAdvance<ReadIMul, 0>; 184def : ReadAdvance<ReadIMul32, 0>; 185def : ReadAdvance<ReadAtomicWA, 0>; 186def : ReadAdvance<ReadAtomicWD, 0>; 187def : ReadAdvance<ReadAtomicDA, 0>; 188def : ReadAdvance<ReadAtomicDD, 0>; 189def : ReadAdvance<ReadAtomicLDW, 0>; 190def : ReadAdvance<ReadAtomicLDD, 0>; 191def : ReadAdvance<ReadAtomicSTW, 0>; 192def : ReadAdvance<ReadAtomicSTD, 0>; 193def : ReadAdvance<ReadFMemBase, 0>; 194def : ReadAdvance<ReadFALU32, 0>; 195def : ReadAdvance<ReadFALU64, 0>; 196def : ReadAdvance<ReadFMul32, 0>; 197def : ReadAdvance<ReadFMulAdd32, 0>; 198def : ReadAdvance<ReadFMulSub32, 0>; 199def : ReadAdvance<ReadFMul64, 0>; 200def : ReadAdvance<ReadFMulAdd64, 0>; 201def : ReadAdvance<ReadFMulSub64, 0>; 202def : ReadAdvance<ReadFDiv32, 0>; 203def : ReadAdvance<ReadFDiv64, 0>; 204def : ReadAdvance<ReadFSqrt32, 0>; 205def : ReadAdvance<ReadFSqrt64, 0>; 206def : ReadAdvance<ReadFCmp32, 0>; 207def : ReadAdvance<ReadFCmp64, 0>; 208def : ReadAdvance<ReadFSGNJ32, 0>; 209def : ReadAdvance<ReadFSGNJ64, 0>; 210def : ReadAdvance<ReadFMinMax32, 0>; 211def : ReadAdvance<ReadFMinMax64, 0>; 212def : ReadAdvance<ReadFCvtF32ToI32, 0>; 213def : ReadAdvance<ReadFCvtF32ToI64, 0>; 214def : ReadAdvance<ReadFCvtF64ToI32, 0>; 215def : ReadAdvance<ReadFCvtF64ToI64, 0>; 216def : ReadAdvance<ReadFCvtI32ToF32, 0>; 217def : ReadAdvance<ReadFCvtI32ToF64, 0>; 218def : ReadAdvance<ReadFCvtI64ToF32, 0>; 219def : ReadAdvance<ReadFCvtI64ToF64, 0>; 220def : ReadAdvance<ReadFCvtF32ToF64, 0>; 221def : ReadAdvance<ReadFCvtF64ToF32, 0>; 222def : ReadAdvance<ReadFMovF32ToI32, 0>; 223def : ReadAdvance<ReadFMovI32ToF32, 0>; 224def : ReadAdvance<ReadFMovF64ToI64, 0>; 225def : ReadAdvance<ReadFMovI64ToF64, 0>; 226def : ReadAdvance<ReadFClass32, 0>; 227def : ReadAdvance<ReadFClass64, 0>; 228} 229