1//==- RISCVSchedRocket32.td - Rocket Scheduling Definitions -*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// ===---------------------------------------------------------------------===// 10// The following definitions describe the simpler per-operand machine model. 11// This works with MachineScheduler. See MCSchedule.h for details. 12 13// Rocket machine model for scheduling and other instruction cost heuristics. 14def Rocket32Model : SchedMachineModel { 15 let MicroOpBufferSize = 0; // Explicitly set to zero since Rocket is in-order. 16 let IssueWidth = 1; // 1 micro-ops are dispatched per cycle. 17 let LoadLatency = 3; 18 let MispredictPenalty = 3; 19 let CompleteModel = 1; 20 let UnsupportedFeatures = [HasStdExtV]; 21} 22 23//===----------------------------------------------------------------------===// 24// Define each kind of processor resource and number available. 25 26// Modeling each pipeline as a ProcResource using the BufferSize = 0 since 27// Rocket is in-order. 28 29let BufferSize = 0 in { 30def Rocket32UnitALU : ProcResource<1>; // Int ALU 31def Rocket32UnitIMul : ProcResource<1>; // Int Multiply 32def Rocket32UnitMem : ProcResource<1>; // Load/Store 33def Rocket32UnitB : ProcResource<1>; // Branch 34 35def Rocket32UnitFPALU : ProcResource<1>; // FP ALU 36} 37 38let BufferSize = 1 in { 39def Rocket32UnitIDiv : ProcResource<1>; // Int Division 40def Rocket32UnitFPDivSqrt : ProcResource<1>; // FP Divide/Sqrt' 41} 42 43//===----------------------------------------------------------------------===// 44// Subtarget-specific SchedWrite types which both map the ProcResources and 45// set the latency. 46 47let SchedModel = Rocket32Model in { 48 49def : WriteRes<WriteJmp, [Rocket32UnitB]>; 50def : WriteRes<WriteJal, [Rocket32UnitB]>; 51def : WriteRes<WriteJalr, [Rocket32UnitB]>; 52def : WriteRes<WriteJmpReg, [Rocket32UnitB]>; 53 54def : WriteRes<WriteIALU, [Rocket32UnitALU]>; 55def : WriteRes<WriteShift, [Rocket32UnitALU]>; 56 57// Multiplies on Rocket differ by implementation; placeholder until 58// we can determine how to read from command line 59def : WriteRes<WriteIMul, [Rocket32UnitIMul]> { let Latency = 4; } 60 61// 32-bit divides have worse case latency of 34 cycle 62def : WriteRes<WriteIDiv, [Rocket32UnitIDiv]> { 63 let Latency = 34; 64 let ResourceCycles = [34]; 65} 66 67// Memory 68def : WriteRes<WriteSTB, [Rocket32UnitMem]>; 69def : WriteRes<WriteSTH, [Rocket32UnitMem]>; 70def : WriteRes<WriteSTW, [Rocket32UnitMem]>; 71def : WriteRes<WriteFST32, [Rocket32UnitMem]>; 72def : WriteRes<WriteFST64, [Rocket32UnitMem]>; 73 74let Latency = 3 in { 75def : WriteRes<WriteLDB, [Rocket32UnitMem]>; 76def : WriteRes<WriteLDH, [Rocket32UnitMem]>; 77def : WriteRes<WriteCSR, [Rocket32UnitALU]>; 78} 79 80let Latency = 2 in { 81def : WriteRes<WriteLDW, [Rocket32UnitMem]>; 82def : WriteRes<WriteFLD32, [Rocket32UnitMem]>; 83def : WriteRes<WriteFLD64, [Rocket32UnitMem]>; 84 85def : WriteRes<WriteAtomicW, [Rocket32UnitMem]>; 86def : WriteRes<WriteAtomicLDW, [Rocket32UnitMem]>; 87} 88 89def : WriteRes<WriteAtomicSTW, [Rocket32UnitMem]>; 90 91// Most FP single precision operations are 4 cycles 92let Latency = 4 in { 93def : WriteRes<WriteFALU32, [Rocket32UnitFPALU]>; 94def : WriteRes<WriteFSGNJ32, [Rocket32UnitFPALU]>; 95def : WriteRes<WriteFMinMax32, [Rocket32UnitFPALU]>; 96} 97 98// Most FP double precision operations are 6 cycles 99let Latency = 6 in { 100def : WriteRes<WriteFALU64, [Rocket32UnitFPALU]>; 101def : WriteRes<WriteFSGNJ64, [Rocket32UnitFPALU]>; 102def : WriteRes<WriteFMinMax64, [Rocket32UnitFPALU]>; 103} 104 105let Latency = 2 in { 106def : WriteRes<WriteFCvtI32ToF32, [Rocket32UnitFPALU]>; 107def : WriteRes<WriteFCvtI32ToF64, [Rocket32UnitFPALU]>; 108def : WriteRes<WriteFCvtF32ToI32, [Rocket32UnitFPALU]>; 109def : WriteRes<WriteFCvtF64ToI32, [Rocket32UnitFPALU]>; 110def : WriteRes<WriteFCvtF32ToF64, [Rocket32UnitFPALU]>; 111def : WriteRes<WriteFCvtF64ToF32, [Rocket32UnitFPALU]>; 112 113def : WriteRes<WriteFClass32, [Rocket32UnitFPALU]>; 114def : WriteRes<WriteFClass64, [Rocket32UnitFPALU]>; 115def : WriteRes<WriteFCmp32, [Rocket32UnitFPALU]>; 116def : WriteRes<WriteFCmp64, [Rocket32UnitFPALU]>; 117def : WriteRes<WriteFMovF32ToI32, [Rocket32UnitFPALU]>; 118def : WriteRes<WriteFMovI32ToF32, [Rocket32UnitFPALU]>; 119} 120 121let Latency = 5 in { 122def : WriteRes<WriteFMul32, [Rocket32UnitFPALU]>; 123def : WriteRes<WriteFMulAdd32, [Rocket32UnitFPALU]>; 124def : WriteRes<WriteFMulSub32, [Rocket32UnitFPALU]>; 125} 126 127let Latency = 7 in { 128def : WriteRes<WriteFMul64, [Rocket32UnitFPALU]>; 129def : WriteRes<WriteFMulAdd64, [Rocket32UnitFPALU]>; 130def : WriteRes<WriteFMulSub64, [Rocket32UnitFPALU]>; 131} 132 133// FP Divide unit on Rocket is not pipelined, so set resource cycles to latency 134let Latency = 20, ResourceCycles = [20] in { 135def : WriteRes<WriteFDiv32, [Rocket32UnitFPDivSqrt]>; 136def : WriteRes<WriteFDiv64, [Rocket32UnitFPDivSqrt]>; 137} 138 139// FP Sqrt unit on Rocket is not pipelined, so set resource cycles to latency 140def : WriteRes<WriteFSqrt32, [Rocket32UnitFPDivSqrt]> { let Latency = 20; 141 let ResourceCycles = [20];} 142def : WriteRes<WriteFSqrt64, [Rocket32UnitFPDivSqrt]> { let Latency = 25; 143 let ResourceCycles = [25];} 144 145def : WriteRes<WriteNop, []>; 146 147def : InstRW<[WriteIALU], (instrs COPY)>; 148 149let Unsupported = 1 in { 150def : WriteRes<WriteIALU32, []>; 151def : WriteRes<WriteShift32, []>; 152def : WriteRes<WriteIMul32, []>; 153def : WriteRes<WriteIDiv32, []>; 154def : WriteRes<WriteSTD, []>; 155def : WriteRes<WriteLDWU, []>; 156def : WriteRes<WriteLDD, []>; 157def : WriteRes<WriteAtomicD, []>; 158def : WriteRes<WriteAtomicLDD, []>; 159def : WriteRes<WriteAtomicSTD, []>; 160def : WriteRes<WriteFCvtI64ToF32, []>; 161def : WriteRes<WriteFCvtI64ToF64, []>; 162def : WriteRes<WriteFCvtF64ToI64, []>; 163def : WriteRes<WriteFCvtF32ToI64, []>; 164def : WriteRes<WriteFMovI64ToF64, []>; 165def : WriteRes<WriteFMovF64ToI64, []>; 166} 167 168//===----------------------------------------------------------------------===// 169// Subtarget-specific SchedRead types with cycles. 170// Dummy definitions for RocketCore. 171def : ReadAdvance<ReadJmp, 0>; 172def : ReadAdvance<ReadJalr, 0>; 173def : ReadAdvance<ReadCSR, 0>; 174def : ReadAdvance<ReadStoreData, 0>; 175def : ReadAdvance<ReadMemBase, 0>; 176def : ReadAdvance<ReadIALU, 0>; 177def : ReadAdvance<ReadIALU32, 0>; 178def : ReadAdvance<ReadShift, 0>; 179def : ReadAdvance<ReadShift32, 0>; 180def : ReadAdvance<ReadIDiv, 0>; 181def : ReadAdvance<ReadIDiv32, 0>; 182def : ReadAdvance<ReadIMul, 0>; 183def : ReadAdvance<ReadIMul32, 0>; 184def : ReadAdvance<ReadAtomicWA, 0>; 185def : ReadAdvance<ReadAtomicWD, 0>; 186def : ReadAdvance<ReadAtomicDA, 0>; 187def : ReadAdvance<ReadAtomicDD, 0>; 188def : ReadAdvance<ReadAtomicLDW, 0>; 189def : ReadAdvance<ReadAtomicLDD, 0>; 190def : ReadAdvance<ReadAtomicSTW, 0>; 191def : ReadAdvance<ReadAtomicSTD, 0>; 192def : ReadAdvance<ReadFMemBase, 0>; 193def : ReadAdvance<ReadFALU32, 0>; 194def : ReadAdvance<ReadFALU64, 0>; 195def : ReadAdvance<ReadFMul32, 0>; 196def : ReadAdvance<ReadFMulAdd32, 0>; 197def : ReadAdvance<ReadFMulSub32, 0>; 198def : ReadAdvance<ReadFMul64, 0>; 199def : ReadAdvance<ReadFMulAdd64, 0>; 200def : ReadAdvance<ReadFMulSub64, 0>; 201def : ReadAdvance<ReadFDiv32, 0>; 202def : ReadAdvance<ReadFDiv64, 0>; 203def : ReadAdvance<ReadFSqrt32, 0>; 204def : ReadAdvance<ReadFSqrt64, 0>; 205def : ReadAdvance<ReadFCmp32, 0>; 206def : ReadAdvance<ReadFCmp64, 0>; 207def : ReadAdvance<ReadFSGNJ32, 0>; 208def : ReadAdvance<ReadFSGNJ64, 0>; 209def : ReadAdvance<ReadFMinMax32, 0>; 210def : ReadAdvance<ReadFMinMax64, 0>; 211def : ReadAdvance<ReadFCvtF32ToI32, 0>; 212def : ReadAdvance<ReadFCvtF32ToI64, 0>; 213def : ReadAdvance<ReadFCvtF64ToI32, 0>; 214def : ReadAdvance<ReadFCvtF64ToI64, 0>; 215def : ReadAdvance<ReadFCvtI32ToF32, 0>; 216def : ReadAdvance<ReadFCvtI32ToF64, 0>; 217def : ReadAdvance<ReadFCvtI64ToF32, 0>; 218def : ReadAdvance<ReadFCvtI64ToF64, 0>; 219def : ReadAdvance<ReadFCvtF32ToF64, 0>; 220def : ReadAdvance<ReadFCvtF64ToF32, 0>; 221def : ReadAdvance<ReadFMovF32ToI32, 0>; 222def : ReadAdvance<ReadFMovI32ToF32, 0>; 223def : ReadAdvance<ReadFMovF64ToI64, 0>; 224def : ReadAdvance<ReadFMovI64ToF64, 0>; 225def : ReadAdvance<ReadFClass32, 0>; 226def : ReadAdvance<ReadFClass64, 0>; 227} 228