1//===-- RISCVInstrInfoB.td - RISC-V 'B' instructions -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions from the standard 'B' Bitmanip 10// extension, version 0.92. 11// This version is still experimental as the 'B' extension hasn't been 12// ratified yet. 13// 14//===----------------------------------------------------------------------===// 15 16//===----------------------------------------------------------------------===// 17// Operand definitions. 18//===----------------------------------------------------------------------===// 19 20def UImmLog2XLenHalfAsmOperand : AsmOperandClass { 21 let Name = "UImmLog2XLenHalf"; 22 let RenderMethod = "addImmOperands"; 23 let DiagnosticType = "InvalidUImmLog2XLenHalf"; 24} 25 26def shfl_uimm : Operand<XLenVT>, ImmLeaf<XLenVT, [{ 27 if (Subtarget->is64Bit()) 28 return isUInt<5>(Imm); 29 return isUInt<4>(Imm); 30}]> { 31 let ParserMatchClass = UImmLog2XLenHalfAsmOperand; 32 let DecoderMethod = "decodeUImmOperand<5>"; 33 let MCOperandPredicate = [{ 34 int64_t Imm; 35 if (!MCOp.evaluateAsConstantImm(Imm)) 36 return false; 37 if (STI.getTargetTriple().isArch64Bit()) 38 return isUInt<5>(Imm); 39 return isUInt<4>(Imm); 40 }]; 41} 42 43//===----------------------------------------------------------------------===// 44// Instruction class templates 45//===----------------------------------------------------------------------===// 46 47// Some of these templates should be moved to RISCVInstrFormats.td once the B 48// extension has been ratified. 49 50let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 51class RVBUnary<bits<7> funct7, bits<5> funct5, bits<3> funct3, 52 RISCVOpcode opcode, string opcodestr> 53 : RVInstR<funct7, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1), 54 opcodestr, "$rd, $rs1"> { 55 let Inst{24-20} = funct5; 56} 57 58let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 59class RVBALUW_ri<bits<3> funct3, string opcodestr> 60 : RVInstI<funct3, OPC_OP_IMM_32, (outs GPR:$rd), 61 (ins GPR:$rs1, simm12:$imm12), opcodestr, "$rd, $rs1, $imm12">; 62 63let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 64class RVBShift_ri<bits<5> funct5, bits<3> funct3, RISCVOpcode opcode, 65 string opcodestr> 66 : RVInstI<funct3, opcode, (outs GPR:$rd), 67 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr, 68 "$rd, $rs1, $shamt"> { 69 bits<6> shamt; 70 71 let Inst{31-27} = funct5; 72 // NOTE: the bit op(26)=1 is used to select funnel shifts. All other 73 // shifts operations and operations that live in the encoding space 74 // of the shifts (single bit operations, grev, gorc) use op(26) = 0 75 let Inst{26} = 0; 76 let Inst{25-20} = shamt; 77} 78 79let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 80class RVBShiftW_ri<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, 81 string opcodestr> 82 : RVInstI<funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1, uimm5:$shamt), 83 opcodestr, "$rd, $rs1, $shamt"> { 84 bits<5> shamt; 85 86 let Inst{31-25} = funct7; 87 let Inst{24-20} = shamt; 88} 89 90let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 91class RVBShfl_ri<bits<6> funct6, bits<3> funct3, RISCVOpcode opcode, 92 string opcodestr> 93 : RVInstI<funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1, shfl_uimm:$shamt), 94 opcodestr, "$rd, $rs1, $shamt"> { 95 bits<6> shamt; 96 97 let Inst{31-26} = funct6; 98 let Inst{25-20} = shamt; 99} 100 101let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 102class RVBTernaryR<bits<2> funct2, bits<3> funct3_b, RISCVOpcode opcode, 103 string opcodestr, string argstr> 104 : RVInstR4<funct2, opcode, (outs GPR:$rd), 105 (ins GPR:$rs1, GPR:$rs2, GPR:$rs3), opcodestr, argstr> { 106 let Inst{14-12} = funct3_b; 107} 108 109// Currently used by FSRI only 110let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 111class RVBTernaryImm6<bits<3> funct3_b, RISCVOpcode opcode, 112 string opcodestr, string argstr> 113 : RVInstR4<0b10, opcode, (outs GPR:$rd), 114 (ins GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt), 115 opcodestr, argstr> { 116 bits<6> shamt; 117 118 // NOTE: the first argument of RVInstR4 is hardcoded to 0b10 like the other 119 // funnel shift instructions. The second bit of the argument though is 120 // overwritten by the shamt as the encoding of this particular instruction 121 // requires. This is to obtain op(26) = 1 as required by funnel shift 122 // instructions without the need of a confusing argument in the definition 123 // of the instruction. 124 let Inst{25-20} = shamt; 125 let Inst{14-12} = funct3_b; 126} 127 128// Currently used by FSRIW only 129let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 130class RVBTernaryImm5<bits<2> funct2, bits<3> funct3_b, RISCVOpcode opcode, 131 string opcodestr, string argstr> 132 : RVInstR4<funct2, opcode, (outs GPR:$rd), 133 (ins GPR:$rs1, GPR:$rs3, uimm5:$shamt), opcodestr, argstr> { 134 bits<5> shamt; 135 136 let Inst{24-20} = shamt; 137 let Inst{14-12} = funct3_b; 138} 139 140//===----------------------------------------------------------------------===// 141// Instructions 142//===----------------------------------------------------------------------===// 143 144let Predicates = [HasStdExtZbbOrZbp] in { 145def ANDN : ALU_rr<0b0100000, 0b111, "andn">, Sched<[]>; 146def ORN : ALU_rr<0b0100000, 0b110, "orn">, Sched<[]>; 147def XNOR : ALU_rr<0b0100000, 0b100, "xnor">, Sched<[]>; 148} // Predicates = [HasStdExtZbbOrZbp] 149 150let Predicates = [HasStdExtZbb] in { 151def SLO : ALU_rr<0b0010000, 0b001, "slo">, Sched<[]>; 152def SRO : ALU_rr<0b0010000, 0b101, "sro">, Sched<[]>; 153} // Predicates = [HasStdExtZbb] 154 155let Predicates = [HasStdExtZbbOrZbp] in { 156def ROL : ALU_rr<0b0110000, 0b001, "rol">, Sched<[]>; 157def ROR : ALU_rr<0b0110000, 0b101, "ror">, Sched<[]>; 158} // Predicates = [HasStdExtZbbOrZbp] 159 160let Predicates = [HasStdExtZbs] in { 161def SBCLR : ALU_rr<0b0100100, 0b001, "sbclr">, Sched<[]>; 162def SBSET : ALU_rr<0b0010100, 0b001, "sbset">, Sched<[]>; 163def SBINV : ALU_rr<0b0110100, 0b001, "sbinv">, Sched<[]>; 164def SBEXT : ALU_rr<0b0100100, 0b101, "sbext">, Sched<[]>; 165} // Predicates = [HasStdExtZbs] 166 167let Predicates = [HasStdExtZbp] in { 168def GORC : ALU_rr<0b0010100, 0b101, "gorc">, Sched<[]>; 169def GREV : ALU_rr<0b0110100, 0b101, "grev">, Sched<[]>; 170} // Predicates = [HasStdExtZbp] 171 172let Predicates = [HasStdExtZbb] in { 173def SLOI : RVBShift_ri<0b00100, 0b001, OPC_OP_IMM, "sloi">, Sched<[]>; 174def SROI : RVBShift_ri<0b00100, 0b101, OPC_OP_IMM, "sroi">, Sched<[]>; 175} // Predicates = [HasStdExtZbb] 176 177let Predicates = [HasStdExtZbbOrZbp] in 178def RORI : RVBShift_ri<0b01100, 0b101, OPC_OP_IMM, "rori">, Sched<[]>; 179 180let Predicates = [HasStdExtZbs] in { 181def SBCLRI : RVBShift_ri<0b01001, 0b001, OPC_OP_IMM, "sbclri">, Sched<[]>; 182def SBSETI : RVBShift_ri<0b00101, 0b001, OPC_OP_IMM, "sbseti">, Sched<[]>; 183def SBINVI : RVBShift_ri<0b01101, 0b001, OPC_OP_IMM, "sbinvi">, Sched<[]>; 184def SBEXTI : RVBShift_ri<0b01001, 0b101, OPC_OP_IMM, "sbexti">, Sched<[]>; 185} // Predicates = [HasStdExtZbs] 186 187let Predicates = [HasStdExtZbp] in { 188def GREVI : RVBShift_ri<0b01101, 0b101, OPC_OP_IMM, "grevi">, Sched<[]>; 189def GORCI : RVBShift_ri<0b00101, 0b101, OPC_OP_IMM, "gorci">, Sched<[]>; 190} // Predicates = [HasStdExtZbp] 191 192let Predicates = [HasStdExtZbt] in { 193def CMIX : RVBTernaryR<0b11, 0b001, OPC_OP, "cmix", "$rd, $rs2, $rs1, $rs3">, 194 Sched<[]>; 195def CMOV : RVBTernaryR<0b11, 0b101, OPC_OP, "cmov", "$rd, $rs2, $rs1, $rs3">, 196 Sched<[]>; 197def FSL : RVBTernaryR<0b10, 0b001, OPC_OP, "fsl", "$rd, $rs1, $rs3, $rs2">, 198 Sched<[]>; 199def FSR : RVBTernaryR<0b10, 0b101, OPC_OP, "fsr", "$rd, $rs1, $rs3, $rs2">, 200 Sched<[]>; 201def FSRI : RVBTernaryImm6<0b101, OPC_OP_IMM, "fsri", 202 "$rd, $rs1, $rs3, $shamt">, Sched<[]>; 203} // Predicates = [HasStdExtZbt] 204 205let Predicates = [HasStdExtZbb] in { 206def CLZ : RVBUnary<0b0110000, 0b00000, 0b001, RISCVOpcode<0b0010011>, "clz">, 207 Sched<[]>; 208def CTZ : RVBUnary<0b0110000, 0b00001, 0b001, RISCVOpcode<0b0010011>, "ctz">, 209 Sched<[]>; 210def PCNT : RVBUnary<0b0110000, 0b00010, 0b001, RISCVOpcode<0b0010011>, "pcnt">, 211 Sched<[]>; 212} // Predicates = [HasStdExtZbb] 213 214let Predicates = [HasStdExtZbm, IsRV64] in 215def BMATFLIP : RVBUnary<0b0110000, 0b00011, 0b001, RISCVOpcode<0b0010011>, 216 "bmatflip">, Sched<[]>; 217 218let Predicates = [HasStdExtZbb] in { 219def SEXTB : RVBUnary<0b0110000, 0b00100, 0b001, RISCVOpcode<0b0010011>, 220 "sext.b">, Sched<[]>; 221def SEXTH : RVBUnary<0b0110000, 0b00101, 0b001, RISCVOpcode<0b0010011>, 222 "sext.h">, Sched<[]>; 223} // Predicates = [HasStdExtZbb] 224 225let Predicates = [HasStdExtZbr] in { 226def CRC32B : RVBUnary<0b0110000, 0b10000, 0b001, RISCVOpcode<0b0010011>, 227 "crc32.b">, Sched<[]>; 228def CRC32H : RVBUnary<0b0110000, 0b10001, 0b001, RISCVOpcode<0b0010011>, 229 "crc32.h">, Sched<[]>; 230def CRC32W : RVBUnary<0b0110000, 0b10010, 0b001, RISCVOpcode<0b0010011>, 231 "crc32.w">, Sched<[]>; 232} // Predicates = [HasStdExtZbr] 233 234let Predicates = [HasStdExtZbr, IsRV64] in 235def CRC32D : RVBUnary<0b0110000, 0b10011, 0b001, RISCVOpcode<0b0010011>, 236 "crc32.d">, Sched<[]>; 237 238let Predicates = [HasStdExtZbr] in { 239def CRC32CB : RVBUnary<0b0110000, 0b11000, 0b001, RISCVOpcode<0b0010011>, 240 "crc32c.b">, Sched<[]>; 241def CRC32CH : RVBUnary<0b0110000, 0b11001, 0b001, RISCVOpcode<0b0010011>, 242 "crc32c.h">, Sched<[]>; 243def CRC32CW : RVBUnary<0b0110000, 0b11010, 0b001, RISCVOpcode<0b0010011>, 244 "crc32c.w">, Sched<[]>; 245} // Predicates = [HasStdExtZbr] 246 247let Predicates = [HasStdExtZbr, IsRV64] in 248def CRC32CD : RVBUnary<0b0110000, 0b11011, 0b001, RISCVOpcode<0b0010011>, 249 "crc32c.d">, Sched<[]>; 250 251let Predicates = [HasStdExtZbc] in { 252def CLMUL : ALU_rr<0b0000101, 0b001, "clmul">, Sched<[]>; 253def CLMULR : ALU_rr<0b0000101, 0b010, "clmulr">, Sched<[]>; 254def CLMULH : ALU_rr<0b0000101, 0b011, "clmulh">, Sched<[]>; 255} // Predicates = [HasStdExtZbc] 256 257let Predicates = [HasStdExtZbb] in { 258def MIN : ALU_rr<0b0000101, 0b100, "min">, Sched<[]>; 259def MAX : ALU_rr<0b0000101, 0b101, "max">, Sched<[]>; 260def MINU : ALU_rr<0b0000101, 0b110, "minu">, Sched<[]>; 261def MAXU : ALU_rr<0b0000101, 0b111, "maxu">, Sched<[]>; 262} // Predicates = [HasStdExtZbb] 263 264let Predicates = [HasStdExtZbp] in { 265def SHFL : ALU_rr<0b0000100, 0b001, "shfl">, Sched<[]>; 266def UNSHFL : ALU_rr<0b0000100, 0b101, "unshfl">, Sched<[]>; 267} // Predicates = [HasStdExtZbp] 268 269let Predicates = [HasStdExtZbe] in { 270def BDEP : ALU_rr<0b0100100, 0b110, "bdep">, Sched<[]>; 271def BEXT : ALU_rr<0b0000100, 0b110, "bext">, Sched<[]>; 272} // Predicates = [HasStdExtZbe] 273 274let Predicates = [HasStdExtZbbOrZbp] in { 275def PACK : ALU_rr<0b0000100, 0b100, "pack">, Sched<[]>; 276def PACKU : ALU_rr<0b0100100, 0b100, "packu">, Sched<[]>; 277} // Predicates = [HasStdExtZbbOrZbp] 278 279let Predicates = [HasStdExtZbm, IsRV64] in { 280def BMATOR : ALU_rr<0b0000100, 0b011, "bmator">, Sched<[]>; 281def BMATXOR : ALU_rr<0b0100100, 0b011, "bmatxor">, Sched<[]>; 282} // Predicates = [HasStdExtZbm, IsRV64] 283 284let Predicates = [HasStdExtZbbOrZbp] in 285def PACKH : ALU_rr<0b0000100, 0b111, "packh">, Sched<[]>; 286 287let Predicates = [HasStdExtZbf] in 288def BFP : ALU_rr<0b0100100, 0b111, "bfp">, Sched<[]>; 289 290let Predicates = [HasStdExtZbp] in { 291def SHFLI : RVBShfl_ri<0b000010, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>; 292def UNSHFLI : RVBShfl_ri<0b000010, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>; 293} // Predicates = [HasStdExtZbp] 294 295let Predicates = [HasStdExtZbb, IsRV64] in { 296def ADDIWU : RVBALUW_ri<0b100, "addiwu">, Sched<[]>; 297def SLLIUW : RVBShift_ri<0b00001, 0b001, OPC_OP_IMM_32, "slliu.w">, Sched<[]>; 298def ADDWU : ALUW_rr<0b0000101, 0b000, "addwu">, Sched<[]>; 299def SUBWU : ALUW_rr<0b0100101, 0b000, "subwu">, Sched<[]>; 300def ADDUW : ALUW_rr<0b0000100, 0b000, "addu.w">, Sched<[]>; 301def SUBUW : ALUW_rr<0b0100100, 0b000, "subu.w">, Sched<[]>; 302} // Predicates = [HasStdExtZbb, IsRV64] 303 304let Predicates = [HasStdExtZbb, IsRV64] in { 305def SLOW : ALUW_rr<0b0010000, 0b001, "slow">, Sched<[]>; 306def SROW : ALUW_rr<0b0010000, 0b101, "srow">, Sched<[]>; 307} // Predicates = [HasStdExtZbb, IsRV64] 308 309let Predicates = [HasStdExtZbbOrZbp, IsRV64] in { 310def ROLW : ALUW_rr<0b0110000, 0b001, "rolw">, Sched<[]>; 311def RORW : ALUW_rr<0b0110000, 0b101, "rorw">, Sched<[]>; 312} // Predicates = [HasStdExtZbbOrZbp, IsRV64] 313 314let Predicates = [HasStdExtZbs, IsRV64] in { 315def SBCLRW : ALUW_rr<0b0100100, 0b001, "sbclrw">, Sched<[]>; 316def SBSETW : ALUW_rr<0b0010100, 0b001, "sbsetw">, Sched<[]>; 317def SBINVW : ALUW_rr<0b0110100, 0b001, "sbinvw">, Sched<[]>; 318def SBEXTW : ALUW_rr<0b0100100, 0b101, "sbextw">, Sched<[]>; 319} // Predicates = [HasStdExtZbs, IsRV64] 320 321let Predicates = [HasStdExtZbp, IsRV64] in { 322def GORCW : ALUW_rr<0b0010100, 0b101, "gorcw">, Sched<[]>; 323def GREVW : ALUW_rr<0b0110100, 0b101, "grevw">, Sched<[]>; 324} // Predicates = [HasStdExtZbp, IsRV64] 325 326let Predicates = [HasStdExtZbb, IsRV64] in { 327def SLOIW : RVBShiftW_ri<0b0010000, 0b001, OPC_OP_IMM_32, "sloiw">, Sched<[]>; 328def SROIW : RVBShiftW_ri<0b0010000, 0b101, OPC_OP_IMM_32, "sroiw">, Sched<[]>; 329} // Predicates = [HasStdExtZbb, IsRV64] 330 331let Predicates = [HasStdExtZbbOrZbp, IsRV64] in 332def RORIW : RVBShiftW_ri<0b0110000, 0b101, OPC_OP_IMM_32, "roriw">, Sched<[]>; 333 334let Predicates = [HasStdExtZbs, IsRV64] in { 335def SBCLRIW : RVBShiftW_ri<0b0100100, 0b001, OPC_OP_IMM_32, "sbclriw">, 336 Sched<[]>; 337def SBSETIW : RVBShiftW_ri<0b0010100, 0b001, OPC_OP_IMM_32, "sbsetiw">, 338 Sched<[]>; 339def SBINVIW : RVBShiftW_ri<0b0110100, 0b001, OPC_OP_IMM_32, "sbinviw">, 340 Sched<[]>; 341} // Predicates = [HasStdExtZbs, IsRV64] 342 343let Predicates = [HasStdExtZbp, IsRV64] in { 344def GORCIW : RVBShiftW_ri<0b0010100, 0b101, OPC_OP_IMM_32, "gorciw">, Sched<[]>; 345def GREVIW : RVBShiftW_ri<0b0110100, 0b101, OPC_OP_IMM_32, "greviw">, Sched<[]>; 346} // Predicates = [HasStdExtZbp, IsRV64] 347 348let Predicates = [HasStdExtZbt, IsRV64] in { 349def FSLW : RVBTernaryR<0b10, 0b001, OPC_OP_32, 350 "fslw", "$rd, $rs1, $rs3, $rs2">, Sched<[]>; 351def FSRW : RVBTernaryR<0b10, 0b101, OPC_OP_32, "fsrw", 352 "$rd, $rs1, $rs3, $rs2">, Sched<[]>; 353def FSRIW : RVBTernaryImm5<0b10, 0b101, OPC_OP_IMM_32, 354 "fsriw", "$rd, $rs1, $rs3, $shamt">, Sched<[]>; 355} // Predicates = [HasStdExtZbt, IsRV64] 356 357let Predicates = [HasStdExtZbb, IsRV64] in { 358def CLZW : RVBUnary<0b0110000, 0b00000, 0b001, RISCVOpcode<0b0011011>, 359 "clzw">, Sched<[]>; 360def CTZW : RVBUnary<0b0110000, 0b00001, 0b001, RISCVOpcode<0b0011011>, 361 "ctzw">, Sched<[]>; 362def PCNTW : RVBUnary<0b0110000, 0b00010, 0b001, RISCVOpcode<0b0011011>, 363 "pcntw">, Sched<[]>; 364} // Predicates = [HasStdExtZbb, IsRV64] 365 366let Predicates = [HasStdExtZbc, IsRV64] in { 367def CLMULW : ALUW_rr<0b0000101, 0b001, "clmulw">, Sched<[]>; 368def CLMULRW : ALUW_rr<0b0000101, 0b010, "clmulrw">, Sched<[]>; 369def CLMULHW : ALUW_rr<0b0000101, 0b011, "clmulhw">, Sched<[]>; 370} // Predicates = [HasStdExtZbc, IsRV64] 371 372let Predicates = [HasStdExtZbp, IsRV64] in { 373def SHFLW : ALUW_rr<0b0000100, 0b001, "shflw">, Sched<[]>; 374def UNSHFLW : ALUW_rr<0b0000100, 0b101, "unshflw">, Sched<[]>; 375} // Predicates = [HasStdExtZbp, IsRV64] 376 377let Predicates = [HasStdExtZbe, IsRV64] in { 378def BDEPW : ALUW_rr<0b0100100, 0b110, "bdepw">, Sched<[]>; 379def BEXTW : ALUW_rr<0b0000100, 0b110, "bextw">, Sched<[]>; 380} // Predicates = [HasStdExtZbe, IsRV64] 381 382let Predicates = [HasStdExtZbbOrZbp, IsRV64] in { 383def PACKW : ALUW_rr<0b0000100, 0b100, "packw">, Sched<[]>; 384def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">, Sched<[]>; 385} // Predicates = [HasStdExtZbbOrZbp, IsRV64] 386 387let Predicates = [HasStdExtZbf, IsRV64] in 388def BFPW : ALUW_rr<0b0100100, 0b111, "bfpw">, Sched<[]>; 389 390//===----------------------------------------------------------------------===// 391// Future compressed instructions 392//===----------------------------------------------------------------------===// 393 394// The presence of these instructions in the B extension is purely experimental 395// and they should be moved to the C extension as soon as they are ratified. 396 397let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 398class RVBInstC<bits<2> funct2, string opcodestr> 399 : RVInst16<(outs GPRC:$rs_wb), (ins GPRC:$rs), opcodestr, "$rs", [], 400 InstFormatCR> { 401 bits<3> rs; 402 let Constraints = "$rs = $rs_wb"; 403 404 let Inst{15-12} = 0b0110; 405 let Inst{11-10} = funct2; 406 let Inst{9-7} = rs; 407 let Inst{6-0} = 0b0000001; 408} 409 410// The namespace RVBC exists to avoid encoding conflicts with the compressed 411// instructions c.addi16sp and c.lui already implemented in the C extension. 412 413let DecoderNamespace = "RVBC", Predicates = [HasStdExtZbproposedc, HasStdExtC] in { 414def C_NOT : RVBInstC<0b00, "c.not">, Sched<[]>; 415def C_NEG : RVBInstC<0b01, "c.neg">, Sched<[]>; 416} // DecoderNamespace = "RVBC", Predicates = [HasStdExtZbproposedc, HasStdExtC] 417 418let DecoderNamespace = "RVBC", Predicates = [HasStdExtZbproposedc, HasStdExtZbbOrZbp, HasStdExtC, IsRV64] in 419def C_ZEXTW : RVBInstC<0b10, "c.zext.w">, Sched<[]>; 420 421//===----------------------------------------------------------------------===// 422// Pseudo Instructions 423//===----------------------------------------------------------------------===// 424 425let Predicates = [HasStdExtZbb, IsRV32] in { 426def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF)>; 427def : InstAlias<"zext.h $rd, $rs", (PACK GPR:$rd, GPR:$rs, X0)>; 428} // Predicates = [HasStdExtZbb, IsRV32] 429 430let Predicates = [HasStdExtZbb, IsRV64] in { 431def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF)>; 432def : InstAlias<"zext.h $rd, $rs", (PACKW GPR:$rd, GPR:$rs, X0)>; 433def : InstAlias<"zext.w $rd, $rs", (PACK GPR:$rd, GPR:$rs, X0)>; 434} // Predicates = [HasStdExtZbb, IsRV64] 435 436let Predicates = [HasStdExtZbbOrZbp] in { 437def : InstAlias<"rev.p $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00001)>, 438 Sched<[]>; 439def : InstAlias<"rev2.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00010)>, 440 Sched<[]>; 441def : InstAlias<"rev.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00011)>, 442 Sched<[]>; 443def : InstAlias<"rev4.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00100)>, 444 Sched<[]>; 445def : InstAlias<"rev2.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00110)>, 446 Sched<[]>; 447def : InstAlias<"rev.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00111)>, 448 Sched<[]>; 449def : InstAlias<"rev8.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01000)>, 450 Sched<[]>; 451def : InstAlias<"rev4.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01100)>, 452 Sched<[]>; 453def : InstAlias<"rev2.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01110)>, 454 Sched<[]>; 455def : InstAlias<"rev.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01111)>, 456 Sched<[]>; 457 458def : InstAlias<"zip.n $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0001)>, 459 Sched<[]>; 460def : InstAlias<"unzip.n $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0001)>, 461 Sched<[]>; 462def : InstAlias<"zip2.b $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0010)>, 463 Sched<[]>; 464def : InstAlias<"unzip2.b $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0010)>, 465 Sched<[]>; 466def : InstAlias<"zip.b $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0011)>, 467 Sched<[]>; 468def : InstAlias<"unzip.b $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0011)>, 469 Sched<[]>; 470def : InstAlias<"zip4.h $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0100)>, 471 Sched<[]>; 472def : InstAlias<"unzip4.h $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0100)>, 473 Sched<[]>; 474def : InstAlias<"zip2.h $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0110)>, 475 Sched<[]>; 476def : InstAlias<"unzip2.h $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0110)>, 477 Sched<[]>; 478def : InstAlias<"zip.h $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0111)>, 479 Sched<[]>; 480def : InstAlias<"unzip.h $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0111)>, 481 Sched<[]>; 482 483def : InstAlias<"orc.p $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00001)>, 484 Sched<[]>; 485def : InstAlias<"orc2.n $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00010)>, 486 Sched<[]>; 487def : InstAlias<"orc.n $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00011)>, 488 Sched<[]>; 489def : InstAlias<"orc4.b $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00100)>, 490 Sched<[]>; 491def : InstAlias<"orc2.b $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00110)>, 492 Sched<[]>; 493def : InstAlias<"orc.b $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00111)>, 494 Sched<[]>; 495def : InstAlias<"orc8.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01000)>, 496 Sched<[]>; 497def : InstAlias<"orc4.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01100)>, 498 Sched<[]>; 499def : InstAlias<"orc2.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01110)>, 500 Sched<[]>; 501def : InstAlias<"orc.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01111)>, 502 Sched<[]>; 503} // Predicates = [HasStdExtZbbOrZbp] 504 505let Predicates = [HasStdExtZbbOrZbp, IsRV32] in { 506def : InstAlias<"rev16 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b10000)>, Sched<[]>; 507def : InstAlias<"rev8 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11000)>, Sched<[]>; 508def : InstAlias<"rev4 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11100)>, Sched<[]>; 509def : InstAlias<"rev2 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11110)>, Sched<[]>; 510def : InstAlias<"rev $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11111)>, Sched<[]>; 511 512def : InstAlias<"zip8 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1000)>, 513 Sched<[]>; 514def : InstAlias<"unzip8 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1000)>, 515 Sched<[]>; 516def : InstAlias<"zip4 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1100)>, 517 Sched<[]>; 518def : InstAlias<"unzip4 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1100)>, 519 Sched<[]>; 520def : InstAlias<"zip2 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1110)>, 521 Sched<[]>; 522def : InstAlias<"unzip2 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1110)>, 523 Sched<[]>; 524def : InstAlias<"zip $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1111)>, 525 Sched<[]>; 526def : InstAlias<"unzip $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1111)>, 527 Sched<[]>; 528 529def : InstAlias<"orc16 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b10000)>, Sched<[]>; 530def : InstAlias<"orc8 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11000)>, Sched<[]>; 531def : InstAlias<"orc4 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11100)>, Sched<[]>; 532def : InstAlias<"orc2 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11110)>, Sched<[]>; 533def : InstAlias<"orc $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11111)>, Sched<[]>; 534} // Predicates = [HasStdExtZbbOrZbp, IsRV32] 535 536let Predicates = [HasStdExtZbbOrZbp, IsRV64] in { 537def : InstAlias<"rev16.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b010000)>, 538 Sched<[]>; 539def : InstAlias<"rev8.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011000)>, 540 Sched<[]>; 541def : InstAlias<"rev4.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011100)>, 542 Sched<[]>; 543def : InstAlias<"rev2.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011110)>, 544 Sched<[]>; 545def : InstAlias<"rev.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011111)>, 546 Sched<[]>; 547def : InstAlias<"rev32 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b100000)>, 548 Sched<[]>; 549def : InstAlias<"rev16 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b110000)>, 550 Sched<[]>; 551def : InstAlias<"rev8 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111000)>, 552 Sched<[]>; 553def : InstAlias<"rev4 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111100)>, 554 Sched<[]>; 555def : InstAlias<"rev2 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111110)>, 556 Sched<[]>; 557def : InstAlias<"rev $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111111)>, 558 Sched<[]>; 559 560def : InstAlias<"zip8.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01000)>, 561 Sched<[]>; 562def : InstAlias<"unzip8.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01000)>, 563 Sched<[]>; 564def : InstAlias<"zip4.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01100)>, 565 Sched<[]>; 566def : InstAlias<"unzip4.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01100)>, 567 Sched<[]>; 568def : InstAlias<"zip2.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01110)>, 569 Sched<[]>; 570def : InstAlias<"unzip2.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01110)>, 571 Sched<[]>; 572def : InstAlias<"zip.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01111)>, 573 Sched<[]>; 574def : InstAlias<"unzip.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01111)>, 575 Sched<[]>; 576def : InstAlias<"zip16 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b10000)>, 577 Sched<[]>; 578def : InstAlias<"unzip16 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b10000)>, 579 Sched<[]>; 580def : InstAlias<"zip8 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11000)>, 581 Sched<[]>; 582def : InstAlias<"unzip8 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11000)>, 583 Sched<[]>; 584def : InstAlias<"zip4 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11100)>, 585 Sched<[]>; 586def : InstAlias<"unzip4 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11100)>, 587 Sched<[]>; 588def : InstAlias<"zip2 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11110)>, 589 Sched<[]>; 590def : InstAlias<"unzip2 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11110)>, 591 Sched<[]>; 592def : InstAlias<"zip $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11111)>, 593 Sched<[]>; 594def : InstAlias<"unzip $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11111)>, 595 Sched<[]>; 596 597def : InstAlias<"orc16.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b010000)>, 598 Sched<[]>; 599def : InstAlias<"orc8.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011000)>, 600 Sched<[]>; 601def : InstAlias<"orc4.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011100)>, 602 Sched<[]>; 603def : InstAlias<"orc2.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011110)>, 604 Sched<[]>; 605def : InstAlias<"orc.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011111)>, 606 Sched<[]>; 607def : InstAlias<"orc32 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b100000)>, 608 Sched<[]>; 609def : InstAlias<"orc16 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b110000)>, 610 Sched<[]>; 611def : InstAlias<"orc8 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111000)>, 612 Sched<[]>; 613def : InstAlias<"orc4 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111100)>, 614 Sched<[]>; 615def : InstAlias<"orc2 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111110)>, 616 Sched<[]>; 617def : InstAlias<"orc $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111111)>, 618 Sched<[]>; 619} // Predicates = [HasStdExtZbbOrZbp, IsRV64] 620 621//===----------------------------------------------------------------------===// 622// Compressed Instruction patterns 623//===----------------------------------------------------------------------===// 624let Predicates = [HasStdExtZbproposedc, HasStdExtC] in { 625def : CompressPat<(XORI GPRC:$rs1, GPRC:$rs1, -1), 626 (C_NOT GPRC:$rs1)>; 627def : CompressPat<(SUB GPRC:$rs1, X0, GPRC:$rs1), 628 (C_NEG GPRC:$rs1)>; 629} // Predicates = [HasStdExtZbproposedc, HasStdExtC] 630 631let Predicates = [HasStdExtZbproposedc, HasStdExtZbbOrZbp, HasStdExtC, IsRV64] in { 632def : CompressPat<(PACK GPRC:$rs1, GPRC:$rs1, X0), 633 (C_ZEXTW GPRC:$rs1)>; 634} // Predicates = [HasStdExtZbproposedc, HasStdExtC, IsRV64] 635 636//===----------------------------------------------------------------------===// 637// Codegen patterns 638//===----------------------------------------------------------------------===// 639def SLOIPat : ComplexPattern<XLenVT, 2, "SelectSLOI", [or]>; 640def SROIPat : ComplexPattern<XLenVT, 2, "SelectSROI", [or]>; 641def RORIPat : ComplexPattern<XLenVT, 2, "SelectRORI", [rotl]>; 642def SLLIUWPat : ComplexPattern<i64, 2, "SelectSLLIUW", [and]>; 643def SLOIWPat : ComplexPattern<i64, 2, "SelectSLOIW", [sext_inreg]>; 644def SROIWPat : ComplexPattern<i64, 2, "SelectSROIW", [or]>; 645def RORIWPat : ComplexPattern<i64, 2, "SelectRORIW", [sext_inreg]>; 646def FSRIWPat : ComplexPattern<i64, 3, "SelectFSRIW", [sext_inreg]>; 647 648let Predicates = [HasStdExtZbbOrZbp] in { 649def : Pat<(and GPR:$rs1, (not GPR:$rs2)), (ANDN GPR:$rs1, GPR:$rs2)>; 650def : Pat<(or GPR:$rs1, (not GPR:$rs2)), (ORN GPR:$rs1, GPR:$rs2)>; 651def : Pat<(xor GPR:$rs1, (not GPR:$rs2)), (XNOR GPR:$rs1, GPR:$rs2)>; 652} // Predicates = [HasStdExtZbbOrZbp] 653 654let Predicates = [HasStdExtZbb] in { 655def : Pat<(xor (shl (xor GPR:$rs1, -1), GPR:$rs2), -1), 656 (SLO GPR:$rs1, GPR:$rs2)>; 657def : Pat<(xor (srl (xor GPR:$rs1, -1), GPR:$rs2), -1), 658 (SRO GPR:$rs1, GPR:$rs2)>; 659} // Predicates = [HasStdExtZbb] 660 661let Predicates = [HasStdExtZbbOrZbp] in { 662def : Pat<(rotl GPR:$rs1, GPR:$rs2), (ROL GPR:$rs1, GPR:$rs2)>; 663def : Pat<(fshl GPR:$rs1, GPR:$rs1, GPR:$rs2), (ROL GPR:$rs1, GPR:$rs2)>; 664def : Pat<(rotr GPR:$rs1, GPR:$rs2), (ROR GPR:$rs1, GPR:$rs2)>; 665def : Pat<(fshr GPR:$rs1, GPR:$rs1, GPR:$rs2), (ROR GPR:$rs1, GPR:$rs2)>; 666} // Predicates = [HasStdExtZbbOrZbp] 667 668let Predicates = [HasStdExtZbs, IsRV32] in 669def : Pat<(and (xor (shl 1, (and GPR:$rs2, 31)), -1), GPR:$rs1), 670 (SBCLR GPR:$rs1, GPR:$rs2)>; 671let Predicates = [HasStdExtZbs, IsRV64] in 672def : Pat<(and (xor (shl 1, (and GPR:$rs2, 63)), -1), GPR:$rs1), 673 (SBCLR GPR:$rs1, GPR:$rs2)>; 674 675let Predicates = [HasStdExtZbs] in 676def : Pat<(and (rotl -2, GPR:$rs2), GPR:$rs1), (SBCLR GPR:$rs1, GPR:$rs2)>; 677 678let Predicates = [HasStdExtZbs, IsRV32] in 679def : Pat<(or (shl 1, (and GPR:$rs2, 31)), GPR:$rs1), 680 (SBSET GPR:$rs1, GPR:$rs2)>; 681let Predicates = [HasStdExtZbs, IsRV64] in 682def : Pat<(or (shl 1, (and GPR:$rs2, 63)), GPR:$rs1), 683 (SBSET GPR:$rs1, GPR:$rs2)>; 684 685let Predicates = [HasStdExtZbs, IsRV32] in 686def : Pat<(xor (shl 1, (and GPR:$rs2, 31)), GPR:$rs1), 687 (SBINV GPR:$rs1, GPR:$rs2)>; 688let Predicates = [HasStdExtZbs, IsRV64] in 689def : Pat<(xor (shl 1, (and GPR:$rs2, 63)), GPR:$rs1), 690 (SBINV GPR:$rs1, GPR:$rs2)>; 691 692let Predicates = [HasStdExtZbs, IsRV32] in 693def : Pat<(and (srl GPR:$rs1, (and GPR:$rs2, 31)), 1), 694 (SBEXT GPR:$rs1, GPR:$rs2)>; 695 696let Predicates = [HasStdExtZbs, IsRV64] in 697def : Pat<(and (srl GPR:$rs1, (and GPR:$rs2, 63)), 1), 698 (SBEXT GPR:$rs1, GPR:$rs2)>; 699 700let Predicates = [HasStdExtZbb] in { 701def : Pat<(SLOIPat GPR:$rs1, uimmlog2xlen:$shamt), 702 (SLOI GPR:$rs1, uimmlog2xlen:$shamt)>; 703def : Pat<(SROIPat GPR:$rs1, uimmlog2xlen:$shamt), 704 (SROI GPR:$rs1, uimmlog2xlen:$shamt)>; 705} // Predicates = [HasStdExtZbb] 706 707// There's no encoding for roli in the current version of the 'B' extension 708// (v0.92) as it can be implemented with rori by negating the immediate. 709// For this reason we pattern-match only against rori[w]. 710let Predicates = [HasStdExtZbbOrZbp] in 711def : Pat<(RORIPat GPR:$rs1, uimmlog2xlen:$shamt), 712 (RORI GPR:$rs1, uimmlog2xlen:$shamt)>; 713 714// We don't pattern-match sbclri[w], sbseti[w], sbinvi[w] because they are 715// pattern-matched by simple andi, ori, and xori. 716let Predicates = [HasStdExtZbs] in 717def : Pat<(and (srl GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1)), 718 (SBEXTI GPR:$rs1, uimmlog2xlen:$shamt)>; 719 720let Predicates = [HasStdExtZbp, IsRV32] in { 721def : Pat<(or (or (and (srl GPR:$rs1, (i32 1)), (i32 0x55555555)), GPR:$rs1), 722 (and (shl GPR:$rs1, (i32 1)), (i32 0xAAAAAAAA))), 723 (GORCI GPR:$rs1, (i32 1))>; 724def : Pat<(or (or (and (srl GPR:$rs1, (i32 2)), (i32 0x33333333)), GPR:$rs1), 725 (and (shl GPR:$rs1, (i32 2)), (i32 0xCCCCCCCC))), 726 (GORCI GPR:$rs1, (i32 2))>; 727def : Pat<(or (or (and (srl GPR:$rs1, (i32 4)), (i32 0x0F0F0F0F)), GPR:$rs1), 728 (and (shl GPR:$rs1, (i32 4)), (i32 0xF0F0F0F0))), 729 (GORCI GPR:$rs1, (i32 4))>; 730def : Pat<(or (or (and (srl GPR:$rs1, (i32 8)), (i32 0x00FF00FF)), GPR:$rs1), 731 (and (shl GPR:$rs1, (i32 8)), (i32 0xFF00FF00))), 732 (GORCI GPR:$rs1, (i32 8))>; 733def : Pat<(or (or (srl GPR:$rs1, (i32 16)), GPR:$rs1), 734 (shl GPR:$rs1, (i32 16))), 735 (GORCI GPR:$rs1, (i32 16))>; 736} // Predicates = [HasStdExtZbp, IsRV32] 737 738let Predicates = [HasStdExtZbp, IsRV64] in { 739def : Pat<(or (or (and (srl GPR:$rs1, (i64 1)), (i64 0x5555555555555555)), 740 GPR:$rs1), 741 (and (shl GPR:$rs1, (i64 1)), (i64 0xAAAAAAAAAAAAAAAA))), 742 (GORCI GPR:$rs1, (i64 1))>; 743def : Pat<(or (or (and (srl GPR:$rs1, (i64 2)), (i64 0x3333333333333333)), 744 GPR:$rs1), 745 (and (shl GPR:$rs1, (i64 2)), (i64 0xCCCCCCCCCCCCCCCC))), 746 (GORCI GPR:$rs1, (i64 2))>; 747def : Pat<(or (or (and (srl GPR:$rs1, (i64 4)), (i64 0x0F0F0F0F0F0F0F0F)), 748 GPR:$rs1), 749 (and (shl GPR:$rs1, (i64 4)), (i64 0xF0F0F0F0F0F0F0F0))), 750 (GORCI GPR:$rs1, (i64 4))>; 751def : Pat<(or (or (and (srl GPR:$rs1, (i64 8)), (i64 0x00FF00FF00FF00FF)), 752 GPR:$rs1), 753 (and (shl GPR:$rs1, (i64 8)), (i64 0xFF00FF00FF00FF00))), 754 (GORCI GPR:$rs1, (i64 8))>; 755def : Pat<(or (or (and (srl GPR:$rs1, (i64 16)), (i64 0x0000FFFF0000FFFF)), 756 GPR:$rs1), 757 (and (shl GPR:$rs1, (i64 16)), (i64 0xFFFF0000FFFF0000))), 758 (GORCI GPR:$rs1, (i64 16))>; 759def : Pat<(or (or (srl GPR:$rs1, (i64 32)), GPR:$rs1), 760 (shl GPR:$rs1, (i64 32))), 761 (GORCI GPR:$rs1, (i64 32))>; 762} // Predicates = [HasStdExtZbp, IsRV64] 763 764let Predicates = [HasStdExtZbp, IsRV32] in { 765def : Pat<(or (and (shl GPR:$rs1, (i32 1)), (i32 0xAAAAAAAA)), 766 (and (srl GPR:$rs1, (i32 1)), (i32 0x55555555))), 767 (GREVI GPR:$rs1, (i32 1))>; 768def : Pat<(or (and (shl GPR:$rs1, (i32 2)), (i32 0xCCCCCCCC)), 769 (and (srl GPR:$rs1, (i32 2)), (i32 0x33333333))), 770 (GREVI GPR:$rs1, (i32 2))>; 771def : Pat<(or (and (shl GPR:$rs1, (i32 4)), (i32 0xF0F0F0F0)), 772 (and (srl GPR:$rs1, (i32 4)), (i32 0x0F0F0F0F))), 773 (GREVI GPR:$rs1, (i32 4))>; 774def : Pat<(or (and (shl GPR:$rs1, (i32 8)), (i32 0xFF00FF00)), 775 (and (srl GPR:$rs1, (i32 8)), (i32 0x00FF00FF))), 776 (GREVI GPR:$rs1, (i32 8))>; 777def : Pat<(rotr (bswap GPR:$rs1), (i32 16)), (GREVI GPR:$rs1, (i32 8))>; 778def : Pat<(or (shl GPR:$rs1, (i32 16)), (srl GPR:$rs1, (i32 16))), 779 (GREVI GPR:$rs1, (i32 16))>; 780def : Pat<(rotl GPR:$rs1, (i32 16)), (GREVI GPR:$rs1, (i32 16))>; 781def : Pat<(bswap GPR:$rs1), (GREVI GPR:$rs1, (i32 24))>; 782def : Pat<(bitreverse GPR:$rs1), (GREVI GPR:$rs1, (i32 31))>; 783} // Predicates = [HasStdExtZbp, IsRV32] 784 785let Predicates = [HasStdExtZbp, IsRV64] in { 786def : Pat<(or (and (shl GPR:$rs1, (i64 1)), (i64 0xAAAAAAAAAAAAAAAA)), 787 (and (srl GPR:$rs1, (i64 1)), (i64 0x5555555555555555))), 788 (GREVI GPR:$rs1, (i64 1))>; 789def : Pat<(or (and (shl GPR:$rs1, (i64 2)), (i64 0xCCCCCCCCCCCCCCCC)), 790 (and (srl GPR:$rs1, (i64 2)), (i64 0x3333333333333333))), 791 (GREVI GPR:$rs1, (i64 2))>; 792def : Pat<(or (and (shl GPR:$rs1, (i64 4)), (i64 0xF0F0F0F0F0F0F0F0)), 793 (and (srl GPR:$rs1, (i64 4)), (i64 0x0F0F0F0F0F0F0F0F))), 794 (GREVI GPR:$rs1, (i64 4))>; 795def : Pat<(or (and (shl GPR:$rs1, (i64 8)), (i64 0xFF00FF00FF00FF00)), 796 (and (srl GPR:$rs1, (i64 8)), (i64 0x00FF00FF00FF00FF))), 797 (GREVI GPR:$rs1, (i64 8))>; 798def : Pat<(or (and (shl GPR:$rs1, (i64 16)), (i64 0xFFFF0000FFFF0000)), 799 (and (srl GPR:$rs1, (i64 16)), (i64 0x0000FFFF0000FFFF))), 800 (GREVI GPR:$rs1, (i64 16))>; 801def : Pat<(or (shl GPR:$rs1, (i64 32)), (srl GPR:$rs1, (i64 32))), 802 (GREVI GPR:$rs1, (i64 32))>; 803def : Pat<(rotl GPR:$rs1, (i64 32)), (GREVI GPR:$rs1, (i64 32))>; 804def : Pat<(bswap GPR:$rs1), (GREVI GPR:$rs1, (i64 56))>; 805def : Pat<(bitreverse GPR:$rs1), (GREVI GPR:$rs1, (i64 63))>; 806} // Predicates = [HasStdExtZbp, IsRV64] 807 808let Predicates = [HasStdExtZbt] in { 809def : Pat<(or (and (xor GPR:$rs2, -1), GPR:$rs3), (and GPR:$rs2, GPR:$rs1)), 810 (CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>; 811def : Pat<(riscv_selectcc GPR:$rs2, (XLenVT 0), (XLenVT 17), GPR:$rs3, GPR:$rs1), 812 (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>; 813def : Pat<(fshl GPR:$rs1, GPR:$rs2, GPR:$rs3), 814 (FSL GPR:$rs1, GPR:$rs2, GPR:$rs3)>; 815def : Pat<(fshr GPR:$rs1, GPR:$rs2, GPR:$rs3), 816 (FSR GPR:$rs1, GPR:$rs2, GPR:$rs3)>; 817def : Pat<(fshr GPR:$rs1, GPR:$rs2, uimmlog2xlen:$shamt), 818 (FSRI GPR:$rs1, GPR:$rs2, uimmlog2xlen:$shamt)>; 819} // Predicates = [HasStdExtZbt] 820 821let Predicates = [HasStdExtZbb] in { 822def : Pat<(ctlz GPR:$rs1), (CLZ GPR:$rs1)>; 823def : Pat<(cttz GPR:$rs1), (CTZ GPR:$rs1)>; 824def : Pat<(ctpop GPR:$rs1), (PCNT GPR:$rs1)>; 825} // Predicates = [HasStdExtZbb] 826 827let Predicates = [HasStdExtZbb, IsRV32] in 828def : Pat<(sra (shl GPR:$rs1, (i32 24)), (i32 24)), (SEXTB GPR:$rs1)>; 829let Predicates = [HasStdExtZbb, IsRV64] in 830def : Pat<(sra (shl GPR:$rs1, (i64 56)), (i64 56)), (SEXTB GPR:$rs1)>; 831 832let Predicates = [HasStdExtZbb, IsRV32] in 833def : Pat<(sra (shl GPR:$rs1, (i32 16)), (i32 16)), (SEXTH GPR:$rs1)>; 834let Predicates = [HasStdExtZbb, IsRV64] in 835def : Pat<(sra (shl GPR:$rs1, (i64 48)), (i64 48)), (SEXTH GPR:$rs1)>; 836 837let Predicates = [HasStdExtZbb] in { 838def : Pat<(smin GPR:$rs1, GPR:$rs2), (MIN GPR:$rs1, GPR:$rs2)>; 839def : Pat<(riscv_selectcc GPR:$rs1, GPR:$rs2, (XLenVT 20), GPR:$rs1, GPR:$rs2), 840 (MIN GPR:$rs1, GPR:$rs2)>; 841def : Pat<(smax GPR:$rs1, GPR:$rs2), (MAX GPR:$rs1, GPR:$rs2)>; 842def : Pat<(riscv_selectcc GPR:$rs2, GPR:$rs1, (XLenVT 20), GPR:$rs1, GPR:$rs2), 843 (MAX GPR:$rs1, GPR:$rs2)>; 844def : Pat<(umin GPR:$rs1, GPR:$rs2), (MINU GPR:$rs1, GPR:$rs2)>; 845def : Pat<(riscv_selectcc GPR:$rs1, GPR:$rs2, (XLenVT 12), GPR:$rs1, GPR:$rs2), 846 (MINU GPR:$rs1, GPR:$rs2)>; 847def : Pat<(umax GPR:$rs1, GPR:$rs2), (MAXU GPR:$rs1, GPR:$rs2)>; 848def : Pat<(riscv_selectcc GPR:$rs2, GPR:$rs1, (XLenVT 12), GPR:$rs1, GPR:$rs2), 849 (MAXU GPR:$rs1, GPR:$rs2)>; 850} // Predicates = [HasStdExtZbb] 851 852let Predicates = [HasStdExtZbbOrZbp, IsRV32] in 853def : Pat<(or (and GPR:$rs1, 0x0000FFFF), (shl GPR:$rs2, (i32 16))), 854 (PACK GPR:$rs1, GPR:$rs2)>; 855let Predicates = [HasStdExtZbbOrZbp, IsRV64] in 856def : Pat<(or (and GPR:$rs1, 0x00000000FFFFFFFF), (shl GPR:$rs2, (i64 32))), 857 (PACK GPR:$rs1, GPR:$rs2)>; 858let Predicates = [HasStdExtZbbOrZbp, IsRV32] in 859def : Pat<(or (and GPR:$rs2, 0xFFFF0000), (srl GPR:$rs1, (i32 16))), 860 (PACKU GPR:$rs1, GPR:$rs2)>; 861let Predicates = [HasStdExtZbbOrZbp, IsRV64] in 862def : Pat<(or (and GPR:$rs2, 0xFFFFFFFF00000000), (srl GPR:$rs1, (i64 32))), 863 (PACKU GPR:$rs1, GPR:$rs2)>; 864let Predicates = [HasStdExtZbbOrZbp] in 865def : Pat<(or (and (shl GPR:$rs2, (XLenVT 8)), 0xFF00), 866 (and GPR:$rs1, 0x00FF)), 867 (PACKH GPR:$rs1, GPR:$rs2)>; 868 869let Predicates = [HasStdExtZbp, IsRV32] in { 870def : Pat<(or (or (and (shl GPR:$rs1, (i32 8)), (i32 0x00FF0000)), 871 (and GPR:$rs1, (i32 0xFF0000FF))), 872 (and (srl GPR:$rs1, (i32 8)), (i32 0x0000FF00))), 873 (SHFLI GPR:$rs1, (i32 8))>; 874def : Pat<(or (or (and (shl GPR:$rs1, (i32 4)), (i32 0x0F000F00)), 875 (and GPR:$rs1, (i32 0xF00FF00F))), 876 (and (srl GPR:$rs1, (i32 4)), (i32 0x00F000F0))), 877 (SHFLI GPR:$rs1, (i32 4))>; 878def : Pat<(or (or (and (shl GPR:$rs1, (i32 2)), (i32 0x30303030)), 879 (and GPR:$rs1, (i32 0xC3C3C3C3))), 880 (and (srl GPR:$rs1, (i32 2)), (i32 0x0C0C0C0C))), 881 (SHFLI GPR:$rs1, (i32 2))>; 882def : Pat<(or (or (and (shl GPR:$rs1, (i32 1)), (i32 0x44444444)), 883 (and GPR:$rs1, (i32 0x99999999))), 884 (and (srl GPR:$rs1, (i32 1)), (i32 0x22222222))), 885 (SHFLI GPR:$rs1, (i32 1))>; 886} // Predicates = [HasStdExtZbp, IsRV32] 887 888let Predicates = [HasStdExtZbp, IsRV64] in { 889def : Pat<(or (or (and (shl GPR:$rs1, (i64 16)), (i64 0x0000FFFF00000000)), 890 (and GPR:$rs1, (i64 0xFFFF00000000FFFF))), 891 (and (srl GPR:$rs1, (i64 16)), (i64 0x00000000FFFF0000))), 892 (SHFLI GPR:$rs1, (i64 16))>; 893def : Pat<(or (or (and (shl GPR:$rs1, (i64 8)), (i64 0x00FF000000FF0000)), 894 (and GPR:$rs1, (i64 0xFF0000FFFF0000FF))), 895 (and (srl GPR:$rs1, (i64 8)), (i64 0x0000FF000000FF00))), 896 (SHFLI GPR:$rs1, (i64 8))>; 897def : Pat<(or (or (and (shl GPR:$rs1, (i64 4)), (i64 0x0F000F000F000F00)), 898 (and GPR:$rs1, (i64 0xF00FF00FF00FF00F))), 899 (and (srl GPR:$rs1, (i64 4)), (i64 0x00F000F000F000F0))), 900 (SHFLI GPR:$rs1, (i64 4))>; 901def : Pat<(or (or (and (shl GPR:$rs1, (i64 2)), (i64 0x3030303030303030)), 902 (and GPR:$rs1, (i64 0xC3C3C3C3C3C3C3C3))), 903 (and (srl GPR:$rs1, (i64 2)), (i64 0x0C0C0C0C0C0C0C0C))), 904 (SHFLI GPR:$rs1, (i64 2))>; 905def : Pat<(or (or (and (shl GPR:$rs1, (i64 1)), (i64 0x4444444444444444)), 906 (and GPR:$rs1, (i64 0x9999999999999999))), 907 (and (srl GPR:$rs1, (i64 1)), (i64 0x2222222222222222))), 908 (SHFLI GPR:$rs1, (i64 1))>; 909} // Predicates = [HasStdExtZbp, IsRV64] 910 911let Predicates = [HasStdExtZbb, IsRV64] in { 912def : Pat<(and (add GPR:$rs, simm12:$simm12), (i64 0xFFFFFFFF)), 913 (ADDIWU GPR:$rs, simm12:$simm12)>; 914def : Pat<(SLLIUWPat GPR:$rs1, uimmlog2xlen:$shamt), 915 (SLLIUW GPR:$rs1, uimmlog2xlen:$shamt)>; 916def : Pat<(and (add GPR:$rs1, GPR:$rs2), (i64 0xFFFFFFFF)), 917 (ADDWU GPR:$rs1, GPR:$rs2)>; 918def : Pat<(and (sub GPR:$rs1, GPR:$rs2), (i64 0xFFFFFFFF)), 919 (SUBWU GPR:$rs1, GPR:$rs2)>; 920def : Pat<(add GPR:$rs1, (and GPR:$rs2, (i64 0xFFFFFFFF))), 921 (ADDUW GPR:$rs1, GPR:$rs2)>; 922def : Pat<(sub GPR:$rs1, (and GPR:$rs2, (i64 0xFFFFFFFF))), 923 (SUBUW GPR:$rs1, GPR:$rs2)>; 924def : Pat<(xor (riscv_sllw (xor GPR:$rs1, -1), GPR:$rs2), -1), 925 (SLOW GPR:$rs1, GPR:$rs2)>; 926def : Pat<(xor (riscv_srlw (xor GPR:$rs1, -1), GPR:$rs2), -1), 927 (SROW GPR:$rs1, GPR:$rs2)>; 928} // Predicates = [HasStdExtZbb, IsRV64] 929 930let Predicates = [HasStdExtZbbOrZbp, IsRV64] in { 931def : Pat<(or (riscv_sllw (assertsexti32 GPR:$rs1), (assertsexti32 GPR:$rs2)), 932 (riscv_srlw (assertsexti32 GPR:$rs1), 933 (sub (i64 0), (assertsexti32 GPR:$rs2)))), 934 (ROLW GPR:$rs1, GPR:$rs2)>; 935def : Pat<(or (riscv_sllw (assertsexti32 GPR:$rs1), 936 (sub (i64 0), (assertsexti32 GPR:$rs2))), 937 (riscv_srlw (assertsexti32 GPR:$rs1), (assertsexti32 GPR:$rs2))), 938 (RORW GPR:$rs1, GPR:$rs2)>; 939} // Predicates = [HasStdExtZbbOrZbp, IsRV64] 940 941let Predicates = [HasStdExtZbs, IsRV64] in { 942def : Pat<(and (xor (riscv_sllw 1, (assertsexti32 GPR:$rs2)), -1), 943 (assertsexti32 GPR:$rs1)), 944 (SBCLRW GPR:$rs1, GPR:$rs2)>; 945def : Pat<(or (riscv_sllw 1, (assertsexti32 GPR:$rs2)), 946 (assertsexti32 GPR:$rs1)), 947 (SBSETW GPR:$rs1, GPR:$rs2)>; 948def : Pat<(xor (riscv_sllw 1, (assertsexti32 GPR:$rs2)), 949 (assertsexti32 GPR:$rs1)), 950 (SBINVW GPR:$rs1, GPR:$rs2)>; 951def : Pat<(and (riscv_srlw (assertsexti32 GPR:$rs1), (assertsexti32 GPR:$rs2)), 952 1), 953 (SBEXTW GPR:$rs1, GPR:$rs2)>; 954} // Predicates = [HasStdExtZbs, IsRV64] 955 956let Predicates = [HasStdExtZbb, IsRV64] in { 957def : Pat<(SLOIWPat GPR:$rs1, uimmlog2xlen:$shamt), 958 (SLOIW GPR:$rs1, uimmlog2xlen:$shamt)>; 959def : Pat<(SROIWPat GPR:$rs1, uimmlog2xlen:$shamt), 960 (SROIW GPR:$rs1, uimmlog2xlen:$shamt)>; 961} // Predicates = [HasStdExtZbb, IsRV64] 962 963let Predicates = [HasStdExtZbbOrZbp, IsRV64] in 964def : Pat<(RORIWPat GPR:$rs1, uimmlog2xlen:$shamt), 965 (RORIW GPR:$rs1, uimmlog2xlen:$shamt)>; 966 967let Predicates = [HasStdExtZbp, IsRV64] in { 968def : Pat<(sext_inreg (or (or (and (srl GPR:$rs1, (i64 1)), (i64 0x55555555)), 969 GPR:$rs1), 970 (and (shl GPR:$rs1, (i64 1)), (i64 0xAAAAAAAA))), 971 i32), 972 (GORCIW GPR:$rs1, (i64 1))>; 973def : Pat<(sext_inreg (or (or (and (srl GPR:$rs1, (i64 2)), (i64 0x33333333)), 974 GPR:$rs1), 975 (and (shl GPR:$rs1, (i64 2)), (i64 0xCCCCCCCC))), 976 i32), 977 (GORCIW GPR:$rs1, (i64 2))>; 978def : Pat<(sext_inreg (or (or (and (srl GPR:$rs1, (i64 4)), (i64 0x0F0F0F0F)), 979 GPR:$rs1), 980 (and (shl GPR:$rs1, (i64 4)), (i64 0xF0F0F0F0))), 981 i32), 982 (GORCIW GPR:$rs1, (i64 4))>; 983def : Pat<(sext_inreg (or (or (and (srl GPR:$rs1, (i64 8)), (i64 0x00FF00FF)), 984 GPR:$rs1), 985 (and (shl GPR:$rs1, (i64 8)), (i64 0xFF00FF00))), 986 i32), 987 (GORCIW GPR:$rs1, (i64 8))>; 988def : Pat<(sext_inreg (or (or (and (srl GPR:$rs1, (i64 16)), (i64 0x0000FFFF)), 989 GPR:$rs1), 990 (and (shl GPR:$rs1, (i64 16)), (i64 0xFFFF0000))), 991 i32), 992 (GORCIW GPR:$rs1, (i64 16))>; 993def : Pat<(sext_inreg (or (or (srl (and GPR:$rs1, (i64 0xFFFF0000)), (i64 16)), 994 GPR:$rs1), 995 (shl GPR:$rs1, (i64 16))), i32), 996 (GORCIW GPR:$rs1, (i64 16))>; 997 998def : Pat<(sext_inreg (or (and (shl GPR:$rs1, (i64 1)), (i64 0xAAAAAAAA)), 999 (and (srl GPR:$rs1, (i64 1)), (i64 0x55555555))), 1000 i32), 1001 (GREVIW GPR:$rs1, (i64 1))>; 1002def : Pat<(sext_inreg (or (and (shl GPR:$rs1, (i64 2)), (i64 0xCCCCCCCC)), 1003 (and (srl GPR:$rs1, (i64 2)), (i64 0x33333333))), 1004 i32), 1005 (GREVIW GPR:$rs1, (i64 2))>; 1006def : Pat<(sext_inreg (or (and (shl GPR:$rs1, (i64 4)), (i64 0xF0F0F0F0)), 1007 (and (srl GPR:$rs1, (i64 4)), (i64 0x0F0F0F0F))), 1008 i32), 1009 (GREVIW GPR:$rs1, (i64 4))>; 1010def : Pat<(sext_inreg (or (and (shl GPR:$rs1, (i64 8)), (i64 0xFF00FF00)), 1011 (and (srl GPR:$rs1, (i64 8)), (i64 0x00FF00FF))), 1012 i32), 1013 (GREVIW GPR:$rs1, (i64 8))>; 1014def : Pat<(sext_inreg (or (shl GPR:$rs1, (i64 16)), 1015 (srl (and GPR:$rs1, 0xFFFF0000), (i64 16))), i32), 1016 (GREVIW GPR:$rs1, (i64 16))>; 1017def : Pat<(sra (bswap GPR:$rs1), (i64 32)), (GREVIW GPR:$rs1, (i64 24))>; 1018def : Pat<(sra (bitreverse GPR:$rs1), (i64 32)), (GREVIW GPR:$rs1, (i64 31))>; 1019} // Predicates = [HasStdExtZbp, IsRV64] 1020 1021let Predicates = [HasStdExtZbt, IsRV64] in { 1022def : Pat<(riscv_selectcc (and (assertsexti32 GPR:$rs3), 31), 1023 (i64 0), 1024 (i64 17), 1025 (assertsexti32 GPR:$rs1), 1026 (or (riscv_sllw (assertsexti32 GPR:$rs1), 1027 (and (assertsexti32 GPR:$rs3), 31)), 1028 (riscv_srlw (assertsexti32 GPR:$rs2), 1029 (sub (i64 32), 1030 (assertsexti32 GPR:$rs3))))), 1031 (FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>; 1032def : Pat<(riscv_selectcc (and (assertsexti32 GPR:$rs3), 31), 1033 (i64 0), 1034 (i64 17), 1035 (assertsexti32 GPR:$rs2), 1036 (or (riscv_sllw (assertsexti32 GPR:$rs1), 1037 (sub (i64 32), 1038 (assertsexti32 GPR:$rs3))), 1039 (riscv_srlw (assertsexti32 GPR:$rs2), 1040 (and (assertsexti32 GPR:$rs3), 31)))), 1041 (FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>; 1042def : Pat<(FSRIWPat GPR:$rs1, GPR:$rs2, uimmlog2xlen:$shamt), 1043 (FSRIW GPR:$rs1, GPR:$rs2, uimmlog2xlen:$shamt)>; 1044} // Predicates = [HasStdExtZbt, IsRV64] 1045 1046let Predicates = [HasStdExtZbb, IsRV64] in { 1047def : Pat<(add (ctlz (and GPR:$rs1, (i64 0xFFFFFFFF))), (i64 -32)), 1048 (CLZW GPR:$rs1)>; 1049// We don't pattern-match CTZW here as it has the same pattern and result as 1050// RV64 CTZ 1051def : Pat<(ctpop (and GPR:$rs1, (i64 0xFFFFFFFF))), (PCNTW GPR:$rs1)>; 1052} // Predicates = [HasStdExtZbb, IsRV64] 1053 1054let Predicates = [HasStdExtZbbOrZbp, IsRV64] in { 1055def : Pat<(sext_inreg (or (shl (assertsexti32 GPR:$rs2), (i64 16)), 1056 (and (assertsexti32 GPR:$rs1), 0x000000000000FFFF)), 1057 i32), 1058 (PACKW GPR:$rs1, GPR:$rs2)>; 1059def : Pat<(or (and (assertsexti32 GPR:$rs2), 0xFFFFFFFFFFFF0000), 1060 (srl (and (assertsexti32 GPR:$rs1), 0x00000000FFFF0000), 1061 (i64 16))), 1062 (PACKUW GPR:$rs1, GPR:$rs2)>; 1063} // Predicates = [HasStdExtZbbOrZbp, IsRV64] 1064