1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2010 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30#ifndef _POWERPC_PS3_IF_GLCREG_H 31#define _POWERPC_PS3_IF_GLCREG_H 32 33#define GLC_MAX_TX_PACKETS 128 34#define GLC_MAX_RX_PACKETS 128 35 36struct glc_dmadesc; 37 38/* 39 * software state for transmit job mbufs (may be elements of mbuf chains) 40 */ 41 42struct glc_txsoft { 43 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 44 bus_dmamap_t txs_dmamap; /* our DMA map */ 45 int txs_firstdesc; /* first descriptor in packet */ 46 int txs_lastdesc; /* last descriptor in packet */ 47 48 int txs_ndescs; /* number of descriptors */ 49 STAILQ_ENTRY(glc_txsoft) txs_q; 50}; 51 52STAILQ_HEAD(glc_txsq, glc_txsoft); 53 54/* 55 * software state for receive jobs 56 */ 57struct glc_rxsoft { 58 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 59 bus_dmamap_t rxs_dmamap; /* our DMA map */ 60 61 int rxs_desc_slot; /* DMA descriptor for this packet */ 62 bus_addr_t rxs_desc; 63 64 bus_dma_segment_t segment; 65}; 66 67struct glc_softc { 68 struct ifnet *sc_ifp; 69 device_t sc_self; 70 struct mtx sc_mtx; 71 u_char sc_enaddr[ETHER_ADDR_LEN]; 72 int sc_tx_vlan, sc_rx_vlan; 73 int sc_ifpflags; 74 75 uint64_t sc_dma_base[5]; 76 bus_dma_tag_t sc_dmadesc_tag; 77 78 int sc_irqid; 79 struct resource *sc_irq; 80 void *sc_irqctx; 81 uint64_t *sc_hwirq_status; 82 volatile uint64_t sc_interrupt_status; 83 84 struct ifmedia sc_media; 85 86 /* Transmission */ 87 88 bus_dma_tag_t sc_txdma_tag; 89 struct glc_txsoft sc_txsoft[GLC_MAX_TX_PACKETS]; 90 struct glc_dmadesc *sc_txdmadesc; 91 int next_txdma_slot, first_used_txdma_slot, bsy_txdma_slots; 92 bus_dmamap_t sc_txdmadesc_map; 93 bus_addr_t sc_txdmadesc_phys; 94 95 struct glc_txsq sc_txfreeq; 96 struct glc_txsq sc_txdirtyq; 97 98 /* Reception */ 99 100 bus_dma_tag_t sc_rxdma_tag; 101 struct glc_rxsoft sc_rxsoft[GLC_MAX_RX_PACKETS]; 102 struct glc_dmadesc *sc_rxdmadesc; 103 int sc_next_rxdma_slot; 104 bus_dmamap_t sc_rxdmadesc_map; 105 bus_addr_t sc_rxdmadesc_phys; 106 107 int sc_bus, sc_dev; 108 int sc_wdog_timer; 109 struct callout sc_tick_ch; 110}; 111 112#define GELIC_GET_MAC_ADDRESS 0x0001 113#define GELIC_GET_LINK_STATUS 0x0002 114#define GELIC_SET_LINK_MODE 0x0003 115#define GELIC_LINK_UP 0x0001 116#define GELIC_FULL_DUPLEX 0x0002 117#define GELIC_AUTO_NEG 0x0004 118#define GELIC_SPEED_10 0x0010 119#define GELIC_SPEED_100 0x0020 120#define GELIC_SPEED_1000 0x0040 121#define GELIC_GET_VLAN_ID 0x0004 122#define GELIC_VLAN_TX_ETHERNET 0x0002 123#define GELIC_VLAN_RX_ETHERNET 0x0012 124#define GELIC_VLAN_TX_WIRELESS 0x0003 125#define GELIC_VLAN_RX_WIRELESS 0x0013 126 127/* Command status code */ 128#define GELIC_DESCR_OWNED 0xa0000000 129#define GELIC_CMDSTAT_DMA_DONE 0x00000000 130#define GELIC_CMDSTAT_CHAIN_END 0x00000002 131#define GELIC_CMDSTAT_CSUM_TCP 0x00020000 132#define GELIC_CMDSTAT_CSUM_UDP 0x00030000 133#define GELIC_CMDSTAT_NOIPSEC 0x00080000 134#define GELIC_CMDSTAT_LAST 0x00040000 135#define GELIC_RXERRORS 0x7def8000 136 137/* RX Data Status codes */ 138#define GELIC_RX_IPCSUM 0x20000000 139#define GELIC_RX_TCPUDPCSUM 0x10000000 140 141/* Interrupt options */ 142#define GELIC_INT_RXDONE 0x0000000000004000UL 143#define GELIC_INT_RXFRAME 0x1000000000000000UL 144#define GELIC_INT_TXDONE 0x0080000000000000UL 145#define GELIC_INT_TX_CHAIN_END 0x0100000000000000UL 146#define GELIC_INT_PHY 0x0000000020000000UL 147 148/* Hardware DMA descriptor. Must be 32-byte aligned */ 149 150struct glc_dmadesc { 151 uint32_t paddr; /* Must be 128 byte aligned for receive */ 152 uint32_t len; 153 uint32_t next; 154 uint32_t cmd_stat; 155 uint32_t result_size; 156 uint32_t valid_size; 157 uint32_t data_stat; 158 uint32_t rxerror; 159}; 160 161#endif /* _POWERPC_PS3_IF_GLCREG_H */ 162 163