1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND BSD-4-Clause 3 * 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31/*- 32 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 33 * Copyright (C) 1995, 1996 TooLs GmbH. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by TooLs GmbH. 47 * 4. The name of TooLs GmbH may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 55 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 56 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 57 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 58 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 59 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 * 61 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 62 */ 63/*- 64 * Copyright (C) 2001 Benno Rice. 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 76 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 77 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 78 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 79 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 80 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 81 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 82 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 83 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 84 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 85 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 86 */ 87 88#include <sys/cdefs.h> 89__FBSDID("$FreeBSD$"); 90 91/* 92 * Manages physical address maps. 93 * 94 * Since the information managed by this module is also stored by the 95 * logical address mapping module, this module may throw away valid virtual 96 * to physical mappings at almost any time. However, invalidations of 97 * mappings must be done as requested. 98 * 99 * In order to cope with hardware architectures which make virtual to 100 * physical map invalidates expensive, this module may delay invalidate 101 * reduced protection operations until such time as they are actually 102 * necessary. This module is given full information as to which processors 103 * are currently using which maps, and to when physical maps must be made 104 * correct. 105 */ 106 107#include "opt_kstack_pages.h" 108 109#include <sys/param.h> 110#include <sys/kernel.h> 111#include <sys/conf.h> 112#include <sys/queue.h> 113#include <sys/cpuset.h> 114#include <sys/kerneldump.h> 115#include <sys/ktr.h> 116#include <sys/lock.h> 117#include <sys/msgbuf.h> 118#include <sys/mutex.h> 119#include <sys/proc.h> 120#include <sys/rwlock.h> 121#include <sys/sched.h> 122#include <sys/sysctl.h> 123#include <sys/systm.h> 124#include <sys/vmmeter.h> 125 126#include <dev/ofw/openfirm.h> 127 128#include <vm/vm.h> 129#include <vm/vm_param.h> 130#include <vm/vm_kern.h> 131#include <vm/vm_page.h> 132#include <vm/vm_map.h> 133#include <vm/vm_object.h> 134#include <vm/vm_extern.h> 135#include <vm/vm_pageout.h> 136#include <vm/uma.h> 137 138#include <machine/cpu.h> 139#include <machine/platform.h> 140#include <machine/bat.h> 141#include <machine/frame.h> 142#include <machine/md_var.h> 143#include <machine/psl.h> 144#include <machine/pte.h> 145#include <machine/smp.h> 146#include <machine/sr.h> 147#include <machine/mmuvar.h> 148#include <machine/trap.h> 149 150#include "mmu_if.h" 151 152#define MOEA_DEBUG 153 154#define TODO panic("%s: not implemented", __func__); 155 156#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 157#define VSID_TO_SR(vsid) ((vsid) & 0xf) 158#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 159 160struct ofw_map { 161 vm_offset_t om_va; 162 vm_size_t om_len; 163 vm_offset_t om_pa; 164 u_int om_mode; 165}; 166 167extern unsigned char _etext[]; 168extern unsigned char _end[]; 169 170/* 171 * Map of physical memory regions. 172 */ 173static struct mem_region *regions; 174static struct mem_region *pregions; 175static u_int phys_avail_count; 176static int regions_sz, pregions_sz; 177static struct ofw_map *translations; 178 179/* 180 * Lock for the pteg and pvo tables. 181 */ 182struct mtx moea_table_mutex; 183struct mtx moea_vsid_mutex; 184 185/* tlbie instruction synchronization */ 186static struct mtx tlbie_mtx; 187 188/* 189 * PTEG data. 190 */ 191static struct pteg *moea_pteg_table; 192u_int moea_pteg_count; 193u_int moea_pteg_mask; 194 195/* 196 * PVO data. 197 */ 198struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 199struct pvo_head moea_pvo_kunmanaged = 200 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 201 202static struct rwlock_padalign pvh_global_lock; 203 204uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 205uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 206 207#define BPVO_POOL_SIZE 32768 208static struct pvo_entry *moea_bpvo_pool; 209static int moea_bpvo_pool_index = 0; 210 211#define VSID_NBPW (sizeof(u_int32_t) * 8) 212static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 213 214static boolean_t moea_initialized = FALSE; 215 216/* 217 * Statistics. 218 */ 219u_int moea_pte_valid = 0; 220u_int moea_pte_overflow = 0; 221u_int moea_pte_replacements = 0; 222u_int moea_pvo_entries = 0; 223u_int moea_pvo_enter_calls = 0; 224u_int moea_pvo_remove_calls = 0; 225u_int moea_pte_spills = 0; 226SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 227 0, ""); 228SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 229 &moea_pte_overflow, 0, ""); 230SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 231 &moea_pte_replacements, 0, ""); 232SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 233 0, ""); 234SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 235 &moea_pvo_enter_calls, 0, ""); 236SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 237 &moea_pvo_remove_calls, 0, ""); 238SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 239 &moea_pte_spills, 0, ""); 240 241/* 242 * Allocate physical memory for use in moea_bootstrap. 243 */ 244static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 245 246/* 247 * PTE calls. 248 */ 249static int moea_pte_insert(u_int, struct pte *); 250 251/* 252 * PVO calls. 253 */ 254static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 255 vm_offset_t, vm_paddr_t, u_int, int); 256static void moea_pvo_remove(struct pvo_entry *, int); 257static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 258static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 259 260/* 261 * Utility routines. 262 */ 263static int moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 264 vm_prot_t, u_int, int8_t); 265static void moea_syncicache(vm_paddr_t, vm_size_t); 266static boolean_t moea_query_bit(vm_page_t, int); 267static u_int moea_clear_bit(vm_page_t, int); 268static void moea_kremove(mmu_t, vm_offset_t); 269int moea_pte_spill(vm_offset_t); 270 271/* 272 * Kernel MMU interface 273 */ 274void moea_clear_modify(mmu_t, vm_page_t); 275void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 276void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 277 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 278int moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, u_int, 279 int8_t); 280void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 281 vm_prot_t); 282void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 283vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 284vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 285void moea_init(mmu_t); 286boolean_t moea_is_modified(mmu_t, vm_page_t); 287boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 288boolean_t moea_is_referenced(mmu_t, vm_page_t); 289int moea_ts_referenced(mmu_t, vm_page_t); 290vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 291boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 292void moea_page_init(mmu_t, vm_page_t); 293int moea_page_wired_mappings(mmu_t, vm_page_t); 294void moea_pinit(mmu_t, pmap_t); 295void moea_pinit0(mmu_t, pmap_t); 296void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 297void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 298void moea_qremove(mmu_t, vm_offset_t, int); 299void moea_release(mmu_t, pmap_t); 300void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 301void moea_remove_all(mmu_t, vm_page_t); 302void moea_remove_write(mmu_t, vm_page_t); 303void moea_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 304void moea_zero_page(mmu_t, vm_page_t); 305void moea_zero_page_area(mmu_t, vm_page_t, int, int); 306void moea_activate(mmu_t, struct thread *); 307void moea_deactivate(mmu_t, struct thread *); 308void moea_cpu_bootstrap(mmu_t, int); 309void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 310void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t); 311void *moea_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 312void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 313vm_paddr_t moea_kextract(mmu_t, vm_offset_t); 314void moea_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 315void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t); 316void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 317boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 318static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 319void moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va); 320void moea_scan_init(mmu_t mmu); 321vm_offset_t moea_quick_enter_page(mmu_t mmu, vm_page_t m); 322void moea_quick_remove_page(mmu_t mmu, vm_offset_t addr); 323static int moea_map_user_ptr(mmu_t mmu, pmap_t pm, 324 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 325static int moea_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, 326 int *is_user, vm_offset_t *decoded_addr); 327 328 329static mmu_method_t moea_methods[] = { 330 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 331 MMUMETHOD(mmu_copy_page, moea_copy_page), 332 MMUMETHOD(mmu_copy_pages, moea_copy_pages), 333 MMUMETHOD(mmu_enter, moea_enter), 334 MMUMETHOD(mmu_enter_object, moea_enter_object), 335 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 336 MMUMETHOD(mmu_extract, moea_extract), 337 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 338 MMUMETHOD(mmu_init, moea_init), 339 MMUMETHOD(mmu_is_modified, moea_is_modified), 340 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 341 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 342 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 343 MMUMETHOD(mmu_map, moea_map), 344 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 345 MMUMETHOD(mmu_page_init, moea_page_init), 346 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 347 MMUMETHOD(mmu_pinit, moea_pinit), 348 MMUMETHOD(mmu_pinit0, moea_pinit0), 349 MMUMETHOD(mmu_protect, moea_protect), 350 MMUMETHOD(mmu_qenter, moea_qenter), 351 MMUMETHOD(mmu_qremove, moea_qremove), 352 MMUMETHOD(mmu_release, moea_release), 353 MMUMETHOD(mmu_remove, moea_remove), 354 MMUMETHOD(mmu_remove_all, moea_remove_all), 355 MMUMETHOD(mmu_remove_write, moea_remove_write), 356 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 357 MMUMETHOD(mmu_unwire, moea_unwire), 358 MMUMETHOD(mmu_zero_page, moea_zero_page), 359 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 360 MMUMETHOD(mmu_activate, moea_activate), 361 MMUMETHOD(mmu_deactivate, moea_deactivate), 362 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 363 MMUMETHOD(mmu_quick_enter_page, moea_quick_enter_page), 364 MMUMETHOD(mmu_quick_remove_page, moea_quick_remove_page), 365 366 /* Internal interfaces */ 367 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 368 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 369 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 370 MMUMETHOD(mmu_mapdev, moea_mapdev), 371 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 372 MMUMETHOD(mmu_kextract, moea_kextract), 373 MMUMETHOD(mmu_kenter, moea_kenter), 374 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 375 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 376 MMUMETHOD(mmu_scan_init, moea_scan_init), 377 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map), 378 MMUMETHOD(mmu_map_user_ptr, moea_map_user_ptr), 379 MMUMETHOD(mmu_decode_kernel_ptr, moea_decode_kernel_ptr), 380 381 { 0, 0 } 382}; 383 384MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 385 386static __inline uint32_t 387moea_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 388{ 389 uint32_t pte_lo; 390 int i; 391 392 if (ma != VM_MEMATTR_DEFAULT) { 393 switch (ma) { 394 case VM_MEMATTR_UNCACHEABLE: 395 return (PTE_I | PTE_G); 396 case VM_MEMATTR_CACHEABLE: 397 return (PTE_M); 398 case VM_MEMATTR_WRITE_COMBINING: 399 case VM_MEMATTR_WRITE_BACK: 400 case VM_MEMATTR_PREFETCHABLE: 401 return (PTE_I); 402 case VM_MEMATTR_WRITE_THROUGH: 403 return (PTE_W | PTE_M); 404 } 405 } 406 407 /* 408 * Assume the page is cache inhibited and access is guarded unless 409 * it's in our available memory array. 410 */ 411 pte_lo = PTE_I | PTE_G; 412 for (i = 0; i < pregions_sz; i++) { 413 if ((pa >= pregions[i].mr_start) && 414 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 415 pte_lo = PTE_M; 416 break; 417 } 418 } 419 420 return pte_lo; 421} 422 423/* 424 * Translate OFW translations into VM attributes. 425 */ 426static __inline vm_memattr_t 427moea_bootstrap_convert_wimg(uint32_t mode) 428{ 429 430 switch (mode) { 431 case (PTE_I | PTE_G): 432 /* PCI device memory */ 433 return VM_MEMATTR_UNCACHEABLE; 434 case (PTE_M): 435 /* Explicitly coherent */ 436 return VM_MEMATTR_CACHEABLE; 437 case 0: /* Default claim */ 438 case 2: /* Alternate PP bits set by OF for the original payload */ 439 /* "Normal" memory. */ 440 return VM_MEMATTR_DEFAULT; 441 442 default: 443 /* Err on the side of caution for unknowns */ 444 /* XXX should we panic instead? */ 445 return VM_MEMATTR_UNCACHEABLE; 446 } 447} 448 449static void 450tlbie(vm_offset_t va) 451{ 452 453 mtx_lock_spin(&tlbie_mtx); 454 __asm __volatile("ptesync"); 455 __asm __volatile("tlbie %0" :: "r"(va)); 456 __asm __volatile("eieio; tlbsync; ptesync"); 457 mtx_unlock_spin(&tlbie_mtx); 458} 459 460static void 461tlbia(void) 462{ 463 vm_offset_t va; 464 465 for (va = 0; va < 0x00040000; va += 0x00001000) { 466 __asm __volatile("tlbie %0" :: "r"(va)); 467 powerpc_sync(); 468 } 469 __asm __volatile("tlbsync"); 470 powerpc_sync(); 471} 472 473static __inline int 474va_to_sr(u_int *sr, vm_offset_t va) 475{ 476 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 477} 478 479static __inline u_int 480va_to_pteg(u_int sr, vm_offset_t addr) 481{ 482 u_int hash; 483 484 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 485 ADDR_PIDX_SHFT); 486 return (hash & moea_pteg_mask); 487} 488 489static __inline struct pvo_head * 490vm_page_to_pvoh(vm_page_t m) 491{ 492 493 return (&m->md.mdpg_pvoh); 494} 495 496static __inline void 497moea_attr_clear(vm_page_t m, int ptebit) 498{ 499 500 rw_assert(&pvh_global_lock, RA_WLOCKED); 501 m->md.mdpg_attrs &= ~ptebit; 502} 503 504static __inline int 505moea_attr_fetch(vm_page_t m) 506{ 507 508 return (m->md.mdpg_attrs); 509} 510 511static __inline void 512moea_attr_save(vm_page_t m, int ptebit) 513{ 514 515 rw_assert(&pvh_global_lock, RA_WLOCKED); 516 m->md.mdpg_attrs |= ptebit; 517} 518 519static __inline int 520moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 521{ 522 if (pt->pte_hi == pvo_pt->pte_hi) 523 return (1); 524 525 return (0); 526} 527 528static __inline int 529moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 530{ 531 return (pt->pte_hi & ~PTE_VALID) == 532 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 533 ((va >> ADDR_API_SHFT) & PTE_API) | which); 534} 535 536static __inline void 537moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 538{ 539 540 mtx_assert(&moea_table_mutex, MA_OWNED); 541 542 /* 543 * Construct a PTE. Default to IMB initially. Valid bit only gets 544 * set when the real pte is set in memory. 545 * 546 * Note: Don't set the valid bit for correct operation of tlb update. 547 */ 548 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 549 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 550 pt->pte_lo = pte_lo; 551} 552 553static __inline void 554moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 555{ 556 557 mtx_assert(&moea_table_mutex, MA_OWNED); 558 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 559} 560 561static __inline void 562moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 563{ 564 565 mtx_assert(&moea_table_mutex, MA_OWNED); 566 567 /* 568 * As shown in Section 7.6.3.2.3 569 */ 570 pt->pte_lo &= ~ptebit; 571 tlbie(va); 572} 573 574static __inline void 575moea_pte_set(struct pte *pt, struct pte *pvo_pt) 576{ 577 578 mtx_assert(&moea_table_mutex, MA_OWNED); 579 pvo_pt->pte_hi |= PTE_VALID; 580 581 /* 582 * Update the PTE as defined in section 7.6.3.1. 583 * Note that the REF/CHG bits are from pvo_pt and thus should have 584 * been saved so this routine can restore them (if desired). 585 */ 586 pt->pte_lo = pvo_pt->pte_lo; 587 powerpc_sync(); 588 pt->pte_hi = pvo_pt->pte_hi; 589 powerpc_sync(); 590 moea_pte_valid++; 591} 592 593static __inline void 594moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 595{ 596 597 mtx_assert(&moea_table_mutex, MA_OWNED); 598 pvo_pt->pte_hi &= ~PTE_VALID; 599 600 /* 601 * Force the reg & chg bits back into the PTEs. 602 */ 603 powerpc_sync(); 604 605 /* 606 * Invalidate the pte. 607 */ 608 pt->pte_hi &= ~PTE_VALID; 609 610 tlbie(va); 611 612 /* 613 * Save the reg & chg bits. 614 */ 615 moea_pte_synch(pt, pvo_pt); 616 moea_pte_valid--; 617} 618 619static __inline void 620moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 621{ 622 623 /* 624 * Invalidate the PTE 625 */ 626 moea_pte_unset(pt, pvo_pt, va); 627 moea_pte_set(pt, pvo_pt); 628} 629 630/* 631 * Quick sort callout for comparing memory regions. 632 */ 633static int om_cmp(const void *a, const void *b); 634 635static int 636om_cmp(const void *a, const void *b) 637{ 638 const struct ofw_map *mapa; 639 const struct ofw_map *mapb; 640 641 mapa = a; 642 mapb = b; 643 if (mapa->om_pa < mapb->om_pa) 644 return (-1); 645 else if (mapa->om_pa > mapb->om_pa) 646 return (1); 647 else 648 return (0); 649} 650 651void 652moea_cpu_bootstrap(mmu_t mmup, int ap) 653{ 654 u_int sdr; 655 int i; 656 657 if (ap) { 658 powerpc_sync(); 659 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 660 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 661 isync(); 662 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 663 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 664 isync(); 665 } 666 667 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 668 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 669 isync(); 670 671 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 672 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 673 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 674 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 675 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 676 isync(); 677 678 for (i = 0; i < 16; i++) 679 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 680 powerpc_sync(); 681 682 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 683 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 684 isync(); 685 686 tlbia(); 687} 688 689void 690moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 691{ 692 ihandle_t mmui; 693 phandle_t chosen, mmu; 694 int sz; 695 int i, j; 696 vm_size_t size, physsz, hwphyssz; 697 vm_offset_t pa, va, off; 698 void *dpcpu; 699 700 /* 701 * Map PCI memory space. 702 */ 703 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 704 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 705 706 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 707 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 708 709 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 710 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 711 712 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 713 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 714 715 powerpc_sync(); 716 717 /* map pci space */ 718 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 719 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 720 isync(); 721 722 /* set global direct map flag */ 723 hw_direct_map = 1; 724 725 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 726 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 727 728 for (i = 0; i < pregions_sz; i++) { 729 vm_offset_t pa; 730 vm_offset_t end; 731 732 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 733 pregions[i].mr_start, 734 pregions[i].mr_start + pregions[i].mr_size, 735 pregions[i].mr_size); 736 /* 737 * Install entries into the BAT table to allow all 738 * of physmem to be convered by on-demand BAT entries. 739 * The loop will sometimes set the same battable element 740 * twice, but that's fine since they won't be used for 741 * a while yet. 742 */ 743 pa = pregions[i].mr_start & 0xf0000000; 744 end = pregions[i].mr_start + pregions[i].mr_size; 745 do { 746 u_int n = pa >> ADDR_SR_SHFT; 747 748 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 749 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 750 pa += SEGMENT_LENGTH; 751 } while (pa < end); 752 } 753 754 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 755 panic("moea_bootstrap: phys_avail too small"); 756 757 phys_avail_count = 0; 758 physsz = 0; 759 hwphyssz = 0; 760 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 761 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 762 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 763 regions[i].mr_start + regions[i].mr_size, 764 regions[i].mr_size); 765 if (hwphyssz != 0 && 766 (physsz + regions[i].mr_size) >= hwphyssz) { 767 if (physsz < hwphyssz) { 768 phys_avail[j] = regions[i].mr_start; 769 phys_avail[j + 1] = regions[i].mr_start + 770 hwphyssz - physsz; 771 physsz = hwphyssz; 772 phys_avail_count++; 773 } 774 break; 775 } 776 phys_avail[j] = regions[i].mr_start; 777 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 778 phys_avail_count++; 779 physsz += regions[i].mr_size; 780 } 781 782 /* Check for overlap with the kernel and exception vectors */ 783 for (j = 0; j < 2*phys_avail_count; j+=2) { 784 if (phys_avail[j] < EXC_LAST) 785 phys_avail[j] += EXC_LAST; 786 787 if (kernelstart >= phys_avail[j] && 788 kernelstart < phys_avail[j+1]) { 789 if (kernelend < phys_avail[j+1]) { 790 phys_avail[2*phys_avail_count] = 791 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 792 phys_avail[2*phys_avail_count + 1] = 793 phys_avail[j+1]; 794 phys_avail_count++; 795 } 796 797 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 798 } 799 800 if (kernelend >= phys_avail[j] && 801 kernelend < phys_avail[j+1]) { 802 if (kernelstart > phys_avail[j]) { 803 phys_avail[2*phys_avail_count] = phys_avail[j]; 804 phys_avail[2*phys_avail_count + 1] = 805 kernelstart & ~PAGE_MASK; 806 phys_avail_count++; 807 } 808 809 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 810 } 811 } 812 813 physmem = btoc(physsz); 814 815 /* 816 * Allocate PTEG table. 817 */ 818#ifdef PTEGCOUNT 819 moea_pteg_count = PTEGCOUNT; 820#else 821 moea_pteg_count = 0x1000; 822 823 while (moea_pteg_count < physmem) 824 moea_pteg_count <<= 1; 825 826 moea_pteg_count >>= 1; 827#endif /* PTEGCOUNT */ 828 829 size = moea_pteg_count * sizeof(struct pteg); 830 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 831 size); 832 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 833 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 834 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 835 moea_pteg_mask = moea_pteg_count - 1; 836 837 /* 838 * Allocate pv/overflow lists. 839 */ 840 size = sizeof(struct pvo_head) * moea_pteg_count; 841 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 842 PAGE_SIZE); 843 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 844 for (i = 0; i < moea_pteg_count; i++) 845 LIST_INIT(&moea_pvo_table[i]); 846 847 /* 848 * Initialize the lock that synchronizes access to the pteg and pvo 849 * tables. 850 */ 851 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 852 MTX_RECURSE); 853 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 854 855 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 856 857 /* 858 * Initialise the unmanaged pvo pool. 859 */ 860 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 861 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 862 moea_bpvo_pool_index = 0; 863 864 /* 865 * Make sure kernel vsid is allocated as well as VSID 0. 866 */ 867 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 868 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 869 moea_vsid_bitmap[0] |= 1; 870 871 /* 872 * Initialize the kernel pmap (which is statically allocated). 873 */ 874 PMAP_LOCK_INIT(kernel_pmap); 875 for (i = 0; i < 16; i++) 876 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 877 CPU_FILL(&kernel_pmap->pm_active); 878 RB_INIT(&kernel_pmap->pmap_pvo); 879 880 /* 881 * Initialize the global pv list lock. 882 */ 883 rw_init(&pvh_global_lock, "pmap pv global"); 884 885 /* 886 * Set up the Open Firmware mappings 887 */ 888 chosen = OF_finddevice("/chosen"); 889 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 890 (mmu = OF_instance_to_package(mmui)) != -1 && 891 (sz = OF_getproplen(mmu, "translations")) != -1) { 892 translations = NULL; 893 for (i = 0; phys_avail[i] != 0; i += 2) { 894 if (phys_avail[i + 1] >= sz) { 895 translations = (struct ofw_map *)phys_avail[i]; 896 break; 897 } 898 } 899 if (translations == NULL) 900 panic("moea_bootstrap: no space to copy translations"); 901 bzero(translations, sz); 902 if (OF_getprop(mmu, "translations", translations, sz) == -1) 903 panic("moea_bootstrap: can't get ofw translations"); 904 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 905 sz /= sizeof(*translations); 906 qsort(translations, sz, sizeof (*translations), om_cmp); 907 for (i = 0; i < sz; i++) { 908 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 909 translations[i].om_pa, translations[i].om_va, 910 translations[i].om_len); 911 912 /* 913 * If the mapping is 1:1, let the RAM and device 914 * on-demand BAT tables take care of the translation. 915 * 916 * However, always enter mappings for segment 16, 917 * which is mixed-protection and therefore not 918 * compatible with a BAT entry. 919 */ 920 if ((translations[i].om_va >> ADDR_SR_SHFT) != 0xf && 921 translations[i].om_va == translations[i].om_pa) 922 continue; 923 924 /* Enter the pages */ 925 for (off = 0; off < translations[i].om_len; 926 off += PAGE_SIZE) 927 moea_kenter_attr(mmup, 928 translations[i].om_va + off, 929 translations[i].om_pa + off, 930 moea_bootstrap_convert_wimg(translations[i].om_mode)); 931 } 932 } 933 934 /* 935 * Calculate the last available physical address. 936 */ 937 for (i = 0; phys_avail[i + 2] != 0; i += 2) 938 ; 939 Maxmem = powerpc_btop(phys_avail[i + 1]); 940 941 moea_cpu_bootstrap(mmup,0); 942 mtmsr(mfmsr() | PSL_DR | PSL_IR); 943 pmap_bootstrapped++; 944 945 /* 946 * Set the start and end of kva. 947 */ 948 virtual_avail = VM_MIN_KERNEL_ADDRESS; 949 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 950 951 /* 952 * Allocate a kernel stack with a guard page for thread0 and map it 953 * into the kernel page map. 954 */ 955 pa = moea_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 956 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 957 virtual_avail = va + kstack_pages * PAGE_SIZE; 958 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 959 thread0.td_kstack = va; 960 thread0.td_kstack_pages = kstack_pages; 961 for (i = 0; i < kstack_pages; i++) { 962 moea_kenter(mmup, va, pa); 963 pa += PAGE_SIZE; 964 va += PAGE_SIZE; 965 } 966 967 /* 968 * Allocate virtual address space for the message buffer. 969 */ 970 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 971 msgbufp = (struct msgbuf *)virtual_avail; 972 va = virtual_avail; 973 virtual_avail += round_page(msgbufsize); 974 while (va < virtual_avail) { 975 moea_kenter(mmup, va, pa); 976 pa += PAGE_SIZE; 977 va += PAGE_SIZE; 978 } 979 980 /* 981 * Allocate virtual address space for the dynamic percpu area. 982 */ 983 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 984 dpcpu = (void *)virtual_avail; 985 va = virtual_avail; 986 virtual_avail += DPCPU_SIZE; 987 while (va < virtual_avail) { 988 moea_kenter(mmup, va, pa); 989 pa += PAGE_SIZE; 990 va += PAGE_SIZE; 991 } 992 dpcpu_init(dpcpu, 0); 993} 994 995/* 996 * Activate a user pmap. The pmap must be activated before it's address 997 * space can be accessed in any way. 998 */ 999void 1000moea_activate(mmu_t mmu, struct thread *td) 1001{ 1002 pmap_t pm, pmr; 1003 1004 /* 1005 * Load all the data we need up front to encourage the compiler to 1006 * not issue any loads while we have interrupts disabled below. 1007 */ 1008 pm = &td->td_proc->p_vmspace->vm_pmap; 1009 pmr = pm->pmap_phys; 1010 1011 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1012 PCPU_SET(curpmap, pmr); 1013 1014 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1015} 1016 1017void 1018moea_deactivate(mmu_t mmu, struct thread *td) 1019{ 1020 pmap_t pm; 1021 1022 pm = &td->td_proc->p_vmspace->vm_pmap; 1023 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1024 PCPU_SET(curpmap, NULL); 1025} 1026 1027void 1028moea_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1029{ 1030 struct pvo_entry key, *pvo; 1031 1032 PMAP_LOCK(pm); 1033 key.pvo_vaddr = sva; 1034 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1035 pvo != NULL && PVO_VADDR(pvo) < eva; 1036 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1037 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1038 panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo); 1039 pvo->pvo_vaddr &= ~PVO_WIRED; 1040 pm->pm_stats.wired_count--; 1041 } 1042 PMAP_UNLOCK(pm); 1043} 1044 1045void 1046moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1047{ 1048 vm_offset_t dst; 1049 vm_offset_t src; 1050 1051 dst = VM_PAGE_TO_PHYS(mdst); 1052 src = VM_PAGE_TO_PHYS(msrc); 1053 1054 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1055} 1056 1057void 1058moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1059 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1060{ 1061 void *a_cp, *b_cp; 1062 vm_offset_t a_pg_offset, b_pg_offset; 1063 int cnt; 1064 1065 while (xfersize > 0) { 1066 a_pg_offset = a_offset & PAGE_MASK; 1067 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1068 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1069 a_pg_offset; 1070 b_pg_offset = b_offset & PAGE_MASK; 1071 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1072 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1073 b_pg_offset; 1074 bcopy(a_cp, b_cp, cnt); 1075 a_offset += cnt; 1076 b_offset += cnt; 1077 xfersize -= cnt; 1078 } 1079} 1080 1081/* 1082 * Zero a page of physical memory by temporarily mapping it into the tlb. 1083 */ 1084void 1085moea_zero_page(mmu_t mmu, vm_page_t m) 1086{ 1087 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m); 1088 1089 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1090 __asm __volatile("dcbz 0,%0" :: "r"(pa + off)); 1091} 1092 1093void 1094moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1095{ 1096 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1097 void *va = (void *)(pa + off); 1098 1099 bzero(va, size); 1100} 1101 1102vm_offset_t 1103moea_quick_enter_page(mmu_t mmu, vm_page_t m) 1104{ 1105 1106 return (VM_PAGE_TO_PHYS(m)); 1107} 1108 1109void 1110moea_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1111{ 1112} 1113 1114/* 1115 * Map the given physical page at the specified virtual address in the 1116 * target pmap with the protection requested. If specified the page 1117 * will be wired down. 1118 */ 1119int 1120moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1121 u_int flags, int8_t psind) 1122{ 1123 int error; 1124 1125 for (;;) { 1126 rw_wlock(&pvh_global_lock); 1127 PMAP_LOCK(pmap); 1128 error = moea_enter_locked(pmap, va, m, prot, flags, psind); 1129 rw_wunlock(&pvh_global_lock); 1130 PMAP_UNLOCK(pmap); 1131 if (error != ENOMEM) 1132 return (KERN_SUCCESS); 1133 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1134 return (KERN_RESOURCE_SHORTAGE); 1135 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1136 vm_wait(NULL); 1137 } 1138} 1139 1140/* 1141 * Map the given physical page at the specified virtual address in the 1142 * target pmap with the protection requested. If specified the page 1143 * will be wired down. 1144 * 1145 * The global pvh and pmap must be locked. 1146 */ 1147static int 1148moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1149 u_int flags, int8_t psind __unused) 1150{ 1151 struct pvo_head *pvo_head; 1152 uma_zone_t zone; 1153 u_int pte_lo, pvo_flags; 1154 int error; 1155 1156 if (pmap_bootstrapped) 1157 rw_assert(&pvh_global_lock, RA_WLOCKED); 1158 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1159 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1160 VM_OBJECT_ASSERT_LOCKED(m->object); 1161 1162 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea_initialized) { 1163 pvo_head = &moea_pvo_kunmanaged; 1164 zone = moea_upvo_zone; 1165 pvo_flags = 0; 1166 } else { 1167 pvo_head = vm_page_to_pvoh(m); 1168 zone = moea_mpvo_zone; 1169 pvo_flags = PVO_MANAGED; 1170 } 1171 1172 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1173 1174 if (prot & VM_PROT_WRITE) { 1175 pte_lo |= PTE_BW; 1176 if (pmap_bootstrapped && 1177 (m->oflags & VPO_UNMANAGED) == 0) 1178 vm_page_aflag_set(m, PGA_WRITEABLE); 1179 } else 1180 pte_lo |= PTE_BR; 1181 1182 if ((flags & PMAP_ENTER_WIRED) != 0) 1183 pvo_flags |= PVO_WIRED; 1184 1185 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1186 pte_lo, pvo_flags); 1187 1188 /* 1189 * Flush the real page from the instruction cache. This has be done 1190 * for all user mappings to prevent information leakage via the 1191 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1192 * mapping for a page. 1193 */ 1194 if (pmap != kernel_pmap && error == ENOENT && 1195 (pte_lo & (PTE_I | PTE_G)) == 0) 1196 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1197 1198 return (error); 1199} 1200 1201/* 1202 * Maps a sequence of resident pages belonging to the same object. 1203 * The sequence begins with the given page m_start. This page is 1204 * mapped at the given virtual address start. Each subsequent page is 1205 * mapped at a virtual address that is offset from start by the same 1206 * amount as the page is offset from m_start within the object. The 1207 * last page in the sequence is the page with the largest offset from 1208 * m_start that can be mapped at a virtual address less than the given 1209 * virtual address end. Not every virtual page between start and end 1210 * is mapped; only those for which a resident page exists with the 1211 * corresponding offset from m_start are mapped. 1212 */ 1213void 1214moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1215 vm_page_t m_start, vm_prot_t prot) 1216{ 1217 vm_page_t m; 1218 vm_pindex_t diff, psize; 1219 1220 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1221 1222 psize = atop(end - start); 1223 m = m_start; 1224 rw_wlock(&pvh_global_lock); 1225 PMAP_LOCK(pm); 1226 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1227 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1228 (VM_PROT_READ | VM_PROT_EXECUTE), 0, 0); 1229 m = TAILQ_NEXT(m, listq); 1230 } 1231 rw_wunlock(&pvh_global_lock); 1232 PMAP_UNLOCK(pm); 1233} 1234 1235void 1236moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1237 vm_prot_t prot) 1238{ 1239 1240 rw_wlock(&pvh_global_lock); 1241 PMAP_LOCK(pm); 1242 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1243 0, 0); 1244 rw_wunlock(&pvh_global_lock); 1245 PMAP_UNLOCK(pm); 1246} 1247 1248vm_paddr_t 1249moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1250{ 1251 struct pvo_entry *pvo; 1252 vm_paddr_t pa; 1253 1254 PMAP_LOCK(pm); 1255 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1256 if (pvo == NULL) 1257 pa = 0; 1258 else 1259 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1260 PMAP_UNLOCK(pm); 1261 return (pa); 1262} 1263 1264/* 1265 * Atomically extract and hold the physical page with the given 1266 * pmap and virtual address pair if that mapping permits the given 1267 * protection. 1268 */ 1269vm_page_t 1270moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1271{ 1272 struct pvo_entry *pvo; 1273 vm_page_t m; 1274 vm_paddr_t pa; 1275 1276 m = NULL; 1277 pa = 0; 1278 PMAP_LOCK(pmap); 1279retry: 1280 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1281 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1282 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1283 (prot & VM_PROT_WRITE) == 0)) { 1284 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1285 goto retry; 1286 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1287 vm_page_hold(m); 1288 } 1289 PA_UNLOCK_COND(pa); 1290 PMAP_UNLOCK(pmap); 1291 return (m); 1292} 1293 1294void 1295moea_init(mmu_t mmu) 1296{ 1297 1298 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1299 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1300 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1301 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1302 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1303 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1304 moea_initialized = TRUE; 1305} 1306 1307boolean_t 1308moea_is_referenced(mmu_t mmu, vm_page_t m) 1309{ 1310 boolean_t rv; 1311 1312 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1313 ("moea_is_referenced: page %p is not managed", m)); 1314 rw_wlock(&pvh_global_lock); 1315 rv = moea_query_bit(m, PTE_REF); 1316 rw_wunlock(&pvh_global_lock); 1317 return (rv); 1318} 1319 1320boolean_t 1321moea_is_modified(mmu_t mmu, vm_page_t m) 1322{ 1323 boolean_t rv; 1324 1325 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1326 ("moea_is_modified: page %p is not managed", m)); 1327 1328 /* 1329 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1330 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1331 * is clear, no PTEs can have PTE_CHG set. 1332 */ 1333 VM_OBJECT_ASSERT_WLOCKED(m->object); 1334 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1335 return (FALSE); 1336 rw_wlock(&pvh_global_lock); 1337 rv = moea_query_bit(m, PTE_CHG); 1338 rw_wunlock(&pvh_global_lock); 1339 return (rv); 1340} 1341 1342boolean_t 1343moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1344{ 1345 struct pvo_entry *pvo; 1346 boolean_t rv; 1347 1348 PMAP_LOCK(pmap); 1349 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1350 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1351 PMAP_UNLOCK(pmap); 1352 return (rv); 1353} 1354 1355void 1356moea_clear_modify(mmu_t mmu, vm_page_t m) 1357{ 1358 1359 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1360 ("moea_clear_modify: page %p is not managed", m)); 1361 VM_OBJECT_ASSERT_WLOCKED(m->object); 1362 KASSERT(!vm_page_xbusied(m), 1363 ("moea_clear_modify: page %p is exclusive busy", m)); 1364 1365 /* 1366 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG 1367 * set. If the object containing the page is locked and the page is 1368 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1369 */ 1370 if ((m->aflags & PGA_WRITEABLE) == 0) 1371 return; 1372 rw_wlock(&pvh_global_lock); 1373 moea_clear_bit(m, PTE_CHG); 1374 rw_wunlock(&pvh_global_lock); 1375} 1376 1377/* 1378 * Clear the write and modified bits in each of the given page's mappings. 1379 */ 1380void 1381moea_remove_write(mmu_t mmu, vm_page_t m) 1382{ 1383 struct pvo_entry *pvo; 1384 struct pte *pt; 1385 pmap_t pmap; 1386 u_int lo; 1387 1388 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1389 ("moea_remove_write: page %p is not managed", m)); 1390 1391 /* 1392 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1393 * set by another thread while the object is locked. Thus, 1394 * if PGA_WRITEABLE is clear, no page table entries need updating. 1395 */ 1396 VM_OBJECT_ASSERT_WLOCKED(m->object); 1397 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1398 return; 1399 rw_wlock(&pvh_global_lock); 1400 lo = moea_attr_fetch(m); 1401 powerpc_sync(); 1402 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1403 pmap = pvo->pvo_pmap; 1404 PMAP_LOCK(pmap); 1405 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1406 pt = moea_pvo_to_pte(pvo, -1); 1407 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1408 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1409 if (pt != NULL) { 1410 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1411 lo |= pvo->pvo_pte.pte.pte_lo; 1412 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1413 moea_pte_change(pt, &pvo->pvo_pte.pte, 1414 pvo->pvo_vaddr); 1415 mtx_unlock(&moea_table_mutex); 1416 } 1417 } 1418 PMAP_UNLOCK(pmap); 1419 } 1420 if ((lo & PTE_CHG) != 0) { 1421 moea_attr_clear(m, PTE_CHG); 1422 vm_page_dirty(m); 1423 } 1424 vm_page_aflag_clear(m, PGA_WRITEABLE); 1425 rw_wunlock(&pvh_global_lock); 1426} 1427 1428/* 1429 * moea_ts_referenced: 1430 * 1431 * Return a count of reference bits for a page, clearing those bits. 1432 * It is not necessary for every reference bit to be cleared, but it 1433 * is necessary that 0 only be returned when there are truly no 1434 * reference bits set. 1435 * 1436 * XXX: The exact number of bits to check and clear is a matter that 1437 * should be tested and standardized at some point in the future for 1438 * optimal aging of shared pages. 1439 */ 1440int 1441moea_ts_referenced(mmu_t mmu, vm_page_t m) 1442{ 1443 int count; 1444 1445 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1446 ("moea_ts_referenced: page %p is not managed", m)); 1447 rw_wlock(&pvh_global_lock); 1448 count = moea_clear_bit(m, PTE_REF); 1449 rw_wunlock(&pvh_global_lock); 1450 return (count); 1451} 1452 1453/* 1454 * Modify the WIMG settings of all mappings for a page. 1455 */ 1456void 1457moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1458{ 1459 struct pvo_entry *pvo; 1460 struct pvo_head *pvo_head; 1461 struct pte *pt; 1462 pmap_t pmap; 1463 u_int lo; 1464 1465 if ((m->oflags & VPO_UNMANAGED) != 0) { 1466 m->md.mdpg_cache_attrs = ma; 1467 return; 1468 } 1469 1470 rw_wlock(&pvh_global_lock); 1471 pvo_head = vm_page_to_pvoh(m); 1472 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1473 1474 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1475 pmap = pvo->pvo_pmap; 1476 PMAP_LOCK(pmap); 1477 pt = moea_pvo_to_pte(pvo, -1); 1478 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1479 pvo->pvo_pte.pte.pte_lo |= lo; 1480 if (pt != NULL) { 1481 moea_pte_change(pt, &pvo->pvo_pte.pte, 1482 pvo->pvo_vaddr); 1483 if (pvo->pvo_pmap == kernel_pmap) 1484 isync(); 1485 } 1486 mtx_unlock(&moea_table_mutex); 1487 PMAP_UNLOCK(pmap); 1488 } 1489 m->md.mdpg_cache_attrs = ma; 1490 rw_wunlock(&pvh_global_lock); 1491} 1492 1493/* 1494 * Map a wired page into kernel virtual address space. 1495 */ 1496void 1497moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1498{ 1499 1500 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1501} 1502 1503void 1504moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1505{ 1506 u_int pte_lo; 1507 int error; 1508 1509#if 0 1510 if (va < VM_MIN_KERNEL_ADDRESS) 1511 panic("moea_kenter: attempt to enter non-kernel address %#x", 1512 va); 1513#endif 1514 1515 pte_lo = moea_calc_wimg(pa, ma); 1516 1517 PMAP_LOCK(kernel_pmap); 1518 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1519 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1520 1521 if (error != 0 && error != ENOENT) 1522 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1523 pa, error); 1524 1525 PMAP_UNLOCK(kernel_pmap); 1526} 1527 1528/* 1529 * Extract the physical page address associated with the given kernel virtual 1530 * address. 1531 */ 1532vm_paddr_t 1533moea_kextract(mmu_t mmu, vm_offset_t va) 1534{ 1535 struct pvo_entry *pvo; 1536 vm_paddr_t pa; 1537 1538 /* 1539 * Allow direct mappings on 32-bit OEA 1540 */ 1541 if (va < VM_MIN_KERNEL_ADDRESS) { 1542 return (va); 1543 } 1544 1545 PMAP_LOCK(kernel_pmap); 1546 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1547 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1548 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1549 PMAP_UNLOCK(kernel_pmap); 1550 return (pa); 1551} 1552 1553/* 1554 * Remove a wired page from kernel virtual address space. 1555 */ 1556void 1557moea_kremove(mmu_t mmu, vm_offset_t va) 1558{ 1559 1560 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1561} 1562 1563/* 1564 * Provide a kernel pointer corresponding to a given userland pointer. 1565 * The returned pointer is valid until the next time this function is 1566 * called in this thread. This is used internally in copyin/copyout. 1567 */ 1568int 1569moea_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr, 1570 void **kaddr, size_t ulen, size_t *klen) 1571{ 1572 size_t l; 1573 register_t vsid; 1574 1575 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1576 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1577 if (l > ulen) 1578 l = ulen; 1579 if (klen) 1580 *klen = l; 1581 else if (l != ulen) 1582 return (EFAULT); 1583 1584 vsid = va_to_vsid(pm, (vm_offset_t)uaddr); 1585 1586 /* Mark segment no-execute */ 1587 vsid |= SR_N; 1588 1589 /* If we have already set this VSID, we can just return */ 1590 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == vsid) 1591 return (0); 1592 1593 __asm __volatile("isync"); 1594 curthread->td_pcb->pcb_cpu.aim.usr_segm = 1595 (uintptr_t)uaddr >> ADDR_SR_SHFT; 1596 curthread->td_pcb->pcb_cpu.aim.usr_vsid = vsid; 1597 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(vsid)); 1598 1599 return (0); 1600} 1601 1602/* 1603 * Figure out where a given kernel pointer (usually in a fault) points 1604 * to from the VM's perspective, potentially remapping into userland's 1605 * address space. 1606 */ 1607static int 1608moea_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user, 1609 vm_offset_t *decoded_addr) 1610{ 1611 vm_offset_t user_sr; 1612 1613 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 1614 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 1615 addr &= ADDR_PIDX | ADDR_POFF; 1616 addr |= user_sr << ADDR_SR_SHFT; 1617 *decoded_addr = addr; 1618 *is_user = 1; 1619 } else { 1620 *decoded_addr = addr; 1621 *is_user = 0; 1622 } 1623 1624 return (0); 1625} 1626 1627/* 1628 * Map a range of physical addresses into kernel virtual address space. 1629 * 1630 * The value passed in *virt is a suggested virtual address for the mapping. 1631 * Architectures which can support a direct-mapped physical to virtual region 1632 * can return the appropriate address within that region, leaving '*virt' 1633 * unchanged. We cannot and therefore do not; *virt is updated with the 1634 * first usable address after the mapped region. 1635 */ 1636vm_offset_t 1637moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1638 vm_paddr_t pa_end, int prot) 1639{ 1640 vm_offset_t sva, va; 1641 1642 sva = *virt; 1643 va = sva; 1644 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1645 moea_kenter(mmu, va, pa_start); 1646 *virt = va; 1647 return (sva); 1648} 1649 1650/* 1651 * Returns true if the pmap's pv is one of the first 1652 * 16 pvs linked to from this page. This count may 1653 * be changed upwards or downwards in the future; it 1654 * is only necessary that true be returned for a small 1655 * subset of pmaps for proper page aging. 1656 */ 1657boolean_t 1658moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1659{ 1660 int loops; 1661 struct pvo_entry *pvo; 1662 boolean_t rv; 1663 1664 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1665 ("moea_page_exists_quick: page %p is not managed", m)); 1666 loops = 0; 1667 rv = FALSE; 1668 rw_wlock(&pvh_global_lock); 1669 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1670 if (pvo->pvo_pmap == pmap) { 1671 rv = TRUE; 1672 break; 1673 } 1674 if (++loops >= 16) 1675 break; 1676 } 1677 rw_wunlock(&pvh_global_lock); 1678 return (rv); 1679} 1680 1681void 1682moea_page_init(mmu_t mmu __unused, vm_page_t m) 1683{ 1684 1685 m->md.mdpg_attrs = 0; 1686 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 1687 LIST_INIT(&m->md.mdpg_pvoh); 1688} 1689 1690/* 1691 * Return the number of managed mappings to the given physical page 1692 * that are wired. 1693 */ 1694int 1695moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1696{ 1697 struct pvo_entry *pvo; 1698 int count; 1699 1700 count = 0; 1701 if ((m->oflags & VPO_UNMANAGED) != 0) 1702 return (count); 1703 rw_wlock(&pvh_global_lock); 1704 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1705 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1706 count++; 1707 rw_wunlock(&pvh_global_lock); 1708 return (count); 1709} 1710 1711static u_int moea_vsidcontext; 1712 1713void 1714moea_pinit(mmu_t mmu, pmap_t pmap) 1715{ 1716 int i, mask; 1717 u_int entropy; 1718 1719 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1720 RB_INIT(&pmap->pmap_pvo); 1721 1722 entropy = 0; 1723 __asm __volatile("mftb %0" : "=r"(entropy)); 1724 1725 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1726 == NULL) { 1727 pmap->pmap_phys = pmap; 1728 } 1729 1730 1731 mtx_lock(&moea_vsid_mutex); 1732 /* 1733 * Allocate some segment registers for this pmap. 1734 */ 1735 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1736 u_int hash, n; 1737 1738 /* 1739 * Create a new value by mutiplying by a prime and adding in 1740 * entropy from the timebase register. This is to make the 1741 * VSID more random so that the PT hash function collides 1742 * less often. (Note that the prime casues gcc to do shifts 1743 * instead of a multiply.) 1744 */ 1745 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1746 hash = moea_vsidcontext & (NPMAPS - 1); 1747 if (hash == 0) /* 0 is special, avoid it */ 1748 continue; 1749 n = hash >> 5; 1750 mask = 1 << (hash & (VSID_NBPW - 1)); 1751 hash = (moea_vsidcontext & 0xfffff); 1752 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1753 /* anything free in this bucket? */ 1754 if (moea_vsid_bitmap[n] == 0xffffffff) { 1755 entropy = (moea_vsidcontext >> 20); 1756 continue; 1757 } 1758 i = ffs(~moea_vsid_bitmap[n]) - 1; 1759 mask = 1 << i; 1760 hash &= rounddown2(0xfffff, VSID_NBPW); 1761 hash |= i; 1762 } 1763 KASSERT(!(moea_vsid_bitmap[n] & mask), 1764 ("Allocating in-use VSID group %#x\n", hash)); 1765 moea_vsid_bitmap[n] |= mask; 1766 for (i = 0; i < 16; i++) 1767 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1768 mtx_unlock(&moea_vsid_mutex); 1769 return; 1770 } 1771 1772 mtx_unlock(&moea_vsid_mutex); 1773 panic("moea_pinit: out of segments"); 1774} 1775 1776/* 1777 * Initialize the pmap associated with process 0. 1778 */ 1779void 1780moea_pinit0(mmu_t mmu, pmap_t pm) 1781{ 1782 1783 PMAP_LOCK_INIT(pm); 1784 moea_pinit(mmu, pm); 1785 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1786} 1787 1788/* 1789 * Set the physical protection on the specified range of this map as requested. 1790 */ 1791void 1792moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1793 vm_prot_t prot) 1794{ 1795 struct pvo_entry *pvo, *tpvo, key; 1796 struct pte *pt; 1797 1798 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1799 ("moea_protect: non current pmap")); 1800 1801 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1802 moea_remove(mmu, pm, sva, eva); 1803 return; 1804 } 1805 1806 rw_wlock(&pvh_global_lock); 1807 PMAP_LOCK(pm); 1808 key.pvo_vaddr = sva; 1809 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1810 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1811 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1812 1813 /* 1814 * Grab the PTE pointer before we diddle with the cached PTE 1815 * copy. 1816 */ 1817 pt = moea_pvo_to_pte(pvo, -1); 1818 /* 1819 * Change the protection of the page. 1820 */ 1821 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1822 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1823 1824 /* 1825 * If the PVO is in the page table, update that pte as well. 1826 */ 1827 if (pt != NULL) { 1828 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1829 mtx_unlock(&moea_table_mutex); 1830 } 1831 } 1832 rw_wunlock(&pvh_global_lock); 1833 PMAP_UNLOCK(pm); 1834} 1835 1836/* 1837 * Map a list of wired pages into kernel virtual address space. This is 1838 * intended for temporary mappings which do not need page modification or 1839 * references recorded. Existing mappings in the region are overwritten. 1840 */ 1841void 1842moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1843{ 1844 vm_offset_t va; 1845 1846 va = sva; 1847 while (count-- > 0) { 1848 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1849 va += PAGE_SIZE; 1850 m++; 1851 } 1852} 1853 1854/* 1855 * Remove page mappings from kernel virtual address space. Intended for 1856 * temporary mappings entered by moea_qenter. 1857 */ 1858void 1859moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1860{ 1861 vm_offset_t va; 1862 1863 va = sva; 1864 while (count-- > 0) { 1865 moea_kremove(mmu, va); 1866 va += PAGE_SIZE; 1867 } 1868} 1869 1870void 1871moea_release(mmu_t mmu, pmap_t pmap) 1872{ 1873 int idx, mask; 1874 1875 /* 1876 * Free segment register's VSID 1877 */ 1878 if (pmap->pm_sr[0] == 0) 1879 panic("moea_release"); 1880 1881 mtx_lock(&moea_vsid_mutex); 1882 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1883 mask = 1 << (idx % VSID_NBPW); 1884 idx /= VSID_NBPW; 1885 moea_vsid_bitmap[idx] &= ~mask; 1886 mtx_unlock(&moea_vsid_mutex); 1887} 1888 1889/* 1890 * Remove the given range of addresses from the specified map. 1891 */ 1892void 1893moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1894{ 1895 struct pvo_entry *pvo, *tpvo, key; 1896 1897 rw_wlock(&pvh_global_lock); 1898 PMAP_LOCK(pm); 1899 key.pvo_vaddr = sva; 1900 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1901 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1902 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1903 moea_pvo_remove(pvo, -1); 1904 } 1905 PMAP_UNLOCK(pm); 1906 rw_wunlock(&pvh_global_lock); 1907} 1908 1909/* 1910 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1911 * will reflect changes in pte's back to the vm_page. 1912 */ 1913void 1914moea_remove_all(mmu_t mmu, vm_page_t m) 1915{ 1916 struct pvo_head *pvo_head; 1917 struct pvo_entry *pvo, *next_pvo; 1918 pmap_t pmap; 1919 1920 rw_wlock(&pvh_global_lock); 1921 pvo_head = vm_page_to_pvoh(m); 1922 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1923 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1924 1925 pmap = pvo->pvo_pmap; 1926 PMAP_LOCK(pmap); 1927 moea_pvo_remove(pvo, -1); 1928 PMAP_UNLOCK(pmap); 1929 } 1930 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) { 1931 moea_attr_clear(m, PTE_CHG); 1932 vm_page_dirty(m); 1933 } 1934 vm_page_aflag_clear(m, PGA_WRITEABLE); 1935 rw_wunlock(&pvh_global_lock); 1936} 1937 1938/* 1939 * Allocate a physical page of memory directly from the phys_avail map. 1940 * Can only be called from moea_bootstrap before avail start and end are 1941 * calculated. 1942 */ 1943static vm_offset_t 1944moea_bootstrap_alloc(vm_size_t size, u_int align) 1945{ 1946 vm_offset_t s, e; 1947 int i, j; 1948 1949 size = round_page(size); 1950 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1951 if (align != 0) 1952 s = roundup2(phys_avail[i], align); 1953 else 1954 s = phys_avail[i]; 1955 e = s + size; 1956 1957 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1958 continue; 1959 1960 if (s == phys_avail[i]) { 1961 phys_avail[i] += size; 1962 } else if (e == phys_avail[i + 1]) { 1963 phys_avail[i + 1] -= size; 1964 } else { 1965 for (j = phys_avail_count * 2; j > i; j -= 2) { 1966 phys_avail[j] = phys_avail[j - 2]; 1967 phys_avail[j + 1] = phys_avail[j - 1]; 1968 } 1969 1970 phys_avail[i + 3] = phys_avail[i + 1]; 1971 phys_avail[i + 1] = s; 1972 phys_avail[i + 2] = e; 1973 phys_avail_count++; 1974 } 1975 1976 return (s); 1977 } 1978 panic("moea_bootstrap_alloc: could not allocate memory"); 1979} 1980 1981static void 1982moea_syncicache(vm_paddr_t pa, vm_size_t len) 1983{ 1984 __syncicache((void *)pa, len); 1985} 1986 1987static int 1988moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1989 vm_offset_t va, vm_paddr_t pa, u_int pte_lo, int flags) 1990{ 1991 struct pvo_entry *pvo; 1992 u_int sr; 1993 int first; 1994 u_int ptegidx; 1995 int i; 1996 int bootstrap; 1997 1998 moea_pvo_enter_calls++; 1999 first = 0; 2000 bootstrap = 0; 2001 2002 /* 2003 * Compute the PTE Group index. 2004 */ 2005 va &= ~ADDR_POFF; 2006 sr = va_to_sr(pm->pm_sr, va); 2007 ptegidx = va_to_pteg(sr, va); 2008 2009 /* 2010 * Remove any existing mapping for this page. Reuse the pvo entry if 2011 * there is a mapping. 2012 */ 2013 mtx_lock(&moea_table_mutex); 2014 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2015 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2016 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 2017 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 2018 (pte_lo & PTE_PP)) { 2019 /* 2020 * The PTE is not changing. Instead, this may 2021 * be a request to change the mapping's wired 2022 * attribute. 2023 */ 2024 mtx_unlock(&moea_table_mutex); 2025 if ((flags & PVO_WIRED) != 0 && 2026 (pvo->pvo_vaddr & PVO_WIRED) == 0) { 2027 pvo->pvo_vaddr |= PVO_WIRED; 2028 pm->pm_stats.wired_count++; 2029 } else if ((flags & PVO_WIRED) == 0 && 2030 (pvo->pvo_vaddr & PVO_WIRED) != 0) { 2031 pvo->pvo_vaddr &= ~PVO_WIRED; 2032 pm->pm_stats.wired_count--; 2033 } 2034 return (0); 2035 } 2036 moea_pvo_remove(pvo, -1); 2037 break; 2038 } 2039 } 2040 2041 /* 2042 * If we aren't overwriting a mapping, try to allocate. 2043 */ 2044 if (moea_initialized) { 2045 pvo = uma_zalloc(zone, M_NOWAIT); 2046 } else { 2047 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 2048 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 2049 moea_bpvo_pool_index, BPVO_POOL_SIZE, 2050 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2051 } 2052 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 2053 moea_bpvo_pool_index++; 2054 bootstrap = 1; 2055 } 2056 2057 if (pvo == NULL) { 2058 mtx_unlock(&moea_table_mutex); 2059 return (ENOMEM); 2060 } 2061 2062 moea_pvo_entries++; 2063 pvo->pvo_vaddr = va; 2064 pvo->pvo_pmap = pm; 2065 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 2066 pvo->pvo_vaddr &= ~ADDR_POFF; 2067 if (flags & PVO_WIRED) 2068 pvo->pvo_vaddr |= PVO_WIRED; 2069 if (pvo_head != &moea_pvo_kunmanaged) 2070 pvo->pvo_vaddr |= PVO_MANAGED; 2071 if (bootstrap) 2072 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2073 2074 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 2075 2076 /* 2077 * Add to pmap list 2078 */ 2079 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2080 2081 /* 2082 * Remember if the list was empty and therefore will be the first 2083 * item. 2084 */ 2085 if (LIST_FIRST(pvo_head) == NULL) 2086 first = 1; 2087 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2088 2089 if (pvo->pvo_vaddr & PVO_WIRED) 2090 pm->pm_stats.wired_count++; 2091 pm->pm_stats.resident_count++; 2092 2093 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2094 KASSERT(i < 8, ("Invalid PTE index")); 2095 if (i >= 0) { 2096 PVO_PTEGIDX_SET(pvo, i); 2097 } else { 2098 panic("moea_pvo_enter: overflow"); 2099 moea_pte_overflow++; 2100 } 2101 mtx_unlock(&moea_table_mutex); 2102 2103 return (first ? ENOENT : 0); 2104} 2105 2106static void 2107moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2108{ 2109 struct pte *pt; 2110 2111 /* 2112 * If there is an active pte entry, we need to deactivate it (and 2113 * save the ref & cfg bits). 2114 */ 2115 pt = moea_pvo_to_pte(pvo, pteidx); 2116 if (pt != NULL) { 2117 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2118 mtx_unlock(&moea_table_mutex); 2119 PVO_PTEGIDX_CLR(pvo); 2120 } else { 2121 moea_pte_overflow--; 2122 } 2123 2124 /* 2125 * Update our statistics. 2126 */ 2127 pvo->pvo_pmap->pm_stats.resident_count--; 2128 if (pvo->pvo_vaddr & PVO_WIRED) 2129 pvo->pvo_pmap->pm_stats.wired_count--; 2130 2131 /* 2132 * Remove this PVO from the PV and pmap lists. 2133 */ 2134 LIST_REMOVE(pvo, pvo_vlink); 2135 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2136 2137 /* 2138 * Save the REF/CHG bits into their cache if the page is managed. 2139 * Clear PGA_WRITEABLE if all mappings of the page have been removed. 2140 */ 2141 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2142 struct vm_page *pg; 2143 2144 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2145 if (pg != NULL) { 2146 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2147 (PTE_REF | PTE_CHG)); 2148 if (LIST_EMPTY(&pg->md.mdpg_pvoh)) 2149 vm_page_aflag_clear(pg, PGA_WRITEABLE); 2150 } 2151 } 2152 2153 /* 2154 * Remove this from the overflow list and return it to the pool 2155 * if we aren't going to reuse it. 2156 */ 2157 LIST_REMOVE(pvo, pvo_olink); 2158 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2159 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2160 moea_upvo_zone, pvo); 2161 moea_pvo_entries--; 2162 moea_pvo_remove_calls++; 2163} 2164 2165static __inline int 2166moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2167{ 2168 int pteidx; 2169 2170 /* 2171 * We can find the actual pte entry without searching by grabbing 2172 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2173 * noticing the HID bit. 2174 */ 2175 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2176 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2177 pteidx ^= moea_pteg_mask * 8; 2178 2179 return (pteidx); 2180} 2181 2182static struct pvo_entry * 2183moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2184{ 2185 struct pvo_entry *pvo; 2186 int ptegidx; 2187 u_int sr; 2188 2189 va &= ~ADDR_POFF; 2190 sr = va_to_sr(pm->pm_sr, va); 2191 ptegidx = va_to_pteg(sr, va); 2192 2193 mtx_lock(&moea_table_mutex); 2194 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2195 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2196 if (pteidx_p) 2197 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2198 break; 2199 } 2200 } 2201 mtx_unlock(&moea_table_mutex); 2202 2203 return (pvo); 2204} 2205 2206static struct pte * 2207moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2208{ 2209 struct pte *pt; 2210 2211 /* 2212 * If we haven't been supplied the ptegidx, calculate it. 2213 */ 2214 if (pteidx == -1) { 2215 int ptegidx; 2216 u_int sr; 2217 2218 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2219 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2220 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2221 } 2222 2223 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2224 mtx_lock(&moea_table_mutex); 2225 2226 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2227 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2228 "valid pte index", pvo); 2229 } 2230 2231 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2232 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2233 "pvo but no valid pte", pvo); 2234 } 2235 2236 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2237 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2238 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2239 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2240 } 2241 2242 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2243 != 0) { 2244 panic("moea_pvo_to_pte: pvo %p pte does not match " 2245 "pte %p in moea_pteg_table", pvo, pt); 2246 } 2247 2248 mtx_assert(&moea_table_mutex, MA_OWNED); 2249 return (pt); 2250 } 2251 2252 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2253 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2254 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2255 } 2256 2257 mtx_unlock(&moea_table_mutex); 2258 return (NULL); 2259} 2260 2261/* 2262 * XXX: THIS STUFF SHOULD BE IN pte.c? 2263 */ 2264int 2265moea_pte_spill(vm_offset_t addr) 2266{ 2267 struct pvo_entry *source_pvo, *victim_pvo; 2268 struct pvo_entry *pvo; 2269 int ptegidx, i, j; 2270 u_int sr; 2271 struct pteg *pteg; 2272 struct pte *pt; 2273 2274 moea_pte_spills++; 2275 2276 sr = mfsrin(addr); 2277 ptegidx = va_to_pteg(sr, addr); 2278 2279 /* 2280 * Have to substitute some entry. Use the primary hash for this. 2281 * Use low bits of timebase as random generator. 2282 */ 2283 pteg = &moea_pteg_table[ptegidx]; 2284 mtx_lock(&moea_table_mutex); 2285 __asm __volatile("mftb %0" : "=r"(i)); 2286 i &= 7; 2287 pt = &pteg->pt[i]; 2288 2289 source_pvo = NULL; 2290 victim_pvo = NULL; 2291 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2292 /* 2293 * We need to find a pvo entry for this address. 2294 */ 2295 if (source_pvo == NULL && 2296 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2297 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2298 /* 2299 * Now found an entry to be spilled into the pteg. 2300 * The PTE is now valid, so we know it's active. 2301 */ 2302 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2303 2304 if (j >= 0) { 2305 PVO_PTEGIDX_SET(pvo, j); 2306 moea_pte_overflow--; 2307 mtx_unlock(&moea_table_mutex); 2308 return (1); 2309 } 2310 2311 source_pvo = pvo; 2312 2313 if (victim_pvo != NULL) 2314 break; 2315 } 2316 2317 /* 2318 * We also need the pvo entry of the victim we are replacing 2319 * so save the R & C bits of the PTE. 2320 */ 2321 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2322 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2323 victim_pvo = pvo; 2324 if (source_pvo != NULL) 2325 break; 2326 } 2327 } 2328 2329 if (source_pvo == NULL) { 2330 mtx_unlock(&moea_table_mutex); 2331 return (0); 2332 } 2333 2334 if (victim_pvo == NULL) { 2335 if ((pt->pte_hi & PTE_HID) == 0) 2336 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2337 "entry", pt); 2338 2339 /* 2340 * If this is a secondary PTE, we need to search it's primary 2341 * pvo bucket for the matching PVO. 2342 */ 2343 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2344 pvo_olink) { 2345 /* 2346 * We also need the pvo entry of the victim we are 2347 * replacing so save the R & C bits of the PTE. 2348 */ 2349 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2350 victim_pvo = pvo; 2351 break; 2352 } 2353 } 2354 2355 if (victim_pvo == NULL) 2356 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2357 "entry", pt); 2358 } 2359 2360 /* 2361 * We are invalidating the TLB entry for the EA we are replacing even 2362 * though it's valid. If we don't, we lose any ref/chg bit changes 2363 * contained in the TLB entry. 2364 */ 2365 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2366 2367 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2368 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2369 2370 PVO_PTEGIDX_CLR(victim_pvo); 2371 PVO_PTEGIDX_SET(source_pvo, i); 2372 moea_pte_replacements++; 2373 2374 mtx_unlock(&moea_table_mutex); 2375 return (1); 2376} 2377 2378static __inline struct pvo_entry * 2379moea_pte_spillable_ident(u_int ptegidx) 2380{ 2381 struct pte *pt; 2382 struct pvo_entry *pvo_walk, *pvo = NULL; 2383 2384 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) { 2385 if (pvo_walk->pvo_vaddr & PVO_WIRED) 2386 continue; 2387 2388 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID)) 2389 continue; 2390 2391 pt = moea_pvo_to_pte(pvo_walk, -1); 2392 2393 if (pt == NULL) 2394 continue; 2395 2396 pvo = pvo_walk; 2397 2398 mtx_unlock(&moea_table_mutex); 2399 if (!(pt->pte_lo & PTE_REF)) 2400 return (pvo_walk); 2401 } 2402 2403 return (pvo); 2404} 2405 2406static int 2407moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2408{ 2409 struct pte *pt; 2410 struct pvo_entry *victim_pvo; 2411 int i; 2412 int victim_idx; 2413 u_int pteg_bkpidx = ptegidx; 2414 2415 mtx_assert(&moea_table_mutex, MA_OWNED); 2416 2417 /* 2418 * First try primary hash. 2419 */ 2420 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2421 if ((pt->pte_hi & PTE_VALID) == 0) { 2422 pvo_pt->pte_hi &= ~PTE_HID; 2423 moea_pte_set(pt, pvo_pt); 2424 return (i); 2425 } 2426 } 2427 2428 /* 2429 * Now try secondary hash. 2430 */ 2431 ptegidx ^= moea_pteg_mask; 2432 2433 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2434 if ((pt->pte_hi & PTE_VALID) == 0) { 2435 pvo_pt->pte_hi |= PTE_HID; 2436 moea_pte_set(pt, pvo_pt); 2437 return (i); 2438 } 2439 } 2440 2441 /* Try again, but this time try to force a PTE out. */ 2442 ptegidx = pteg_bkpidx; 2443 2444 victim_pvo = moea_pte_spillable_ident(ptegidx); 2445 if (victim_pvo == NULL) { 2446 ptegidx ^= moea_pteg_mask; 2447 victim_pvo = moea_pte_spillable_ident(ptegidx); 2448 } 2449 2450 if (victim_pvo == NULL) { 2451 panic("moea_pte_insert: overflow"); 2452 return (-1); 2453 } 2454 2455 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx); 2456 2457 if (pteg_bkpidx == ptegidx) 2458 pvo_pt->pte_hi &= ~PTE_HID; 2459 else 2460 pvo_pt->pte_hi |= PTE_HID; 2461 2462 /* 2463 * Synchronize the sacrifice PTE with its PVO, then mark both 2464 * invalid. The PVO will be reused when/if the VM system comes 2465 * here after a fault. 2466 */ 2467 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7]; 2468 2469 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi) 2470 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2471 2472 /* 2473 * Set the new PTE. 2474 */ 2475 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2476 PVO_PTEGIDX_CLR(victim_pvo); 2477 moea_pte_overflow++; 2478 moea_pte_set(pt, pvo_pt); 2479 2480 return (victim_idx & 7); 2481} 2482 2483static boolean_t 2484moea_query_bit(vm_page_t m, int ptebit) 2485{ 2486 struct pvo_entry *pvo; 2487 struct pte *pt; 2488 2489 rw_assert(&pvh_global_lock, RA_WLOCKED); 2490 if (moea_attr_fetch(m) & ptebit) 2491 return (TRUE); 2492 2493 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2494 2495 /* 2496 * See if we saved the bit off. If so, cache it and return 2497 * success. 2498 */ 2499 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2500 moea_attr_save(m, ptebit); 2501 return (TRUE); 2502 } 2503 } 2504 2505 /* 2506 * No luck, now go through the hard part of looking at the PTEs 2507 * themselves. Sync so that any pending REF/CHG bits are flushed to 2508 * the PTEs. 2509 */ 2510 powerpc_sync(); 2511 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2512 2513 /* 2514 * See if this pvo has a valid PTE. if so, fetch the 2515 * REF/CHG bits from the valid PTE. If the appropriate 2516 * ptebit is set, cache it and return success. 2517 */ 2518 pt = moea_pvo_to_pte(pvo, -1); 2519 if (pt != NULL) { 2520 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2521 mtx_unlock(&moea_table_mutex); 2522 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2523 moea_attr_save(m, ptebit); 2524 return (TRUE); 2525 } 2526 } 2527 } 2528 2529 return (FALSE); 2530} 2531 2532static u_int 2533moea_clear_bit(vm_page_t m, int ptebit) 2534{ 2535 u_int count; 2536 struct pvo_entry *pvo; 2537 struct pte *pt; 2538 2539 rw_assert(&pvh_global_lock, RA_WLOCKED); 2540 2541 /* 2542 * Clear the cached value. 2543 */ 2544 moea_attr_clear(m, ptebit); 2545 2546 /* 2547 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2548 * we can reset the right ones). note that since the pvo entries and 2549 * list heads are accessed via BAT0 and are never placed in the page 2550 * table, we don't have to worry about further accesses setting the 2551 * REF/CHG bits. 2552 */ 2553 powerpc_sync(); 2554 2555 /* 2556 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2557 * valid pte clear the ptebit from the valid pte. 2558 */ 2559 count = 0; 2560 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2561 pt = moea_pvo_to_pte(pvo, -1); 2562 if (pt != NULL) { 2563 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2564 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2565 count++; 2566 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2567 } 2568 mtx_unlock(&moea_table_mutex); 2569 } 2570 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2571 } 2572 2573 return (count); 2574} 2575 2576/* 2577 * Return true if the physical range is encompassed by the battable[idx] 2578 */ 2579static int 2580moea_bat_mapped(int idx, vm_paddr_t pa, vm_size_t size) 2581{ 2582 u_int prot; 2583 u_int32_t start; 2584 u_int32_t end; 2585 u_int32_t bat_ble; 2586 2587 /* 2588 * Return immediately if not a valid mapping 2589 */ 2590 if (!(battable[idx].batu & BAT_Vs)) 2591 return (EINVAL); 2592 2593 /* 2594 * The BAT entry must be cache-inhibited, guarded, and r/w 2595 * so it can function as an i/o page 2596 */ 2597 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2598 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2599 return (EPERM); 2600 2601 /* 2602 * The address should be within the BAT range. Assume that the 2603 * start address in the BAT has the correct alignment (thus 2604 * not requiring masking) 2605 */ 2606 start = battable[idx].batl & BAT_PBS; 2607 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2608 end = start | (bat_ble << 15) | 0x7fff; 2609 2610 if ((pa < start) || ((pa + size) > end)) 2611 return (ERANGE); 2612 2613 return (0); 2614} 2615 2616boolean_t 2617moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2618{ 2619 int i; 2620 2621 /* 2622 * This currently does not work for entries that 2623 * overlap 256M BAT segments. 2624 */ 2625 2626 for(i = 0; i < 16; i++) 2627 if (moea_bat_mapped(i, pa, size) == 0) 2628 return (0); 2629 2630 return (EFAULT); 2631} 2632 2633/* 2634 * Map a set of physical memory pages into the kernel virtual 2635 * address space. Return a pointer to where it is mapped. This 2636 * routine is intended to be used for mapping device memory, 2637 * NOT real memory. 2638 */ 2639void * 2640moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2641{ 2642 2643 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2644} 2645 2646void * 2647moea_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2648{ 2649 vm_offset_t va, tmpva, ppa, offset; 2650 int i; 2651 2652 ppa = trunc_page(pa); 2653 offset = pa & PAGE_MASK; 2654 size = roundup(offset + size, PAGE_SIZE); 2655 2656 /* 2657 * If the physical address lies within a valid BAT table entry, 2658 * return the 1:1 mapping. This currently doesn't work 2659 * for regions that overlap 256M BAT segments. 2660 */ 2661 for (i = 0; i < 16; i++) { 2662 if (moea_bat_mapped(i, pa, size) == 0) 2663 return ((void *) pa); 2664 } 2665 2666 va = kva_alloc(size); 2667 if (!va) 2668 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2669 2670 for (tmpva = va; size > 0;) { 2671 moea_kenter_attr(mmu, tmpva, ppa, ma); 2672 tlbie(tmpva); 2673 size -= PAGE_SIZE; 2674 tmpva += PAGE_SIZE; 2675 ppa += PAGE_SIZE; 2676 } 2677 2678 return ((void *)(va + offset)); 2679} 2680 2681void 2682moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2683{ 2684 vm_offset_t base, offset; 2685 2686 /* 2687 * If this is outside kernel virtual space, then it's a 2688 * battable entry and doesn't require unmapping 2689 */ 2690 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2691 base = trunc_page(va); 2692 offset = va & PAGE_MASK; 2693 size = roundup(offset + size, PAGE_SIZE); 2694 moea_qremove(mmu, base, atop(size)); 2695 kva_free(base, size); 2696 } 2697} 2698 2699static void 2700moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2701{ 2702 struct pvo_entry *pvo; 2703 vm_offset_t lim; 2704 vm_paddr_t pa; 2705 vm_size_t len; 2706 2707 PMAP_LOCK(pm); 2708 while (sz > 0) { 2709 lim = round_page(va); 2710 len = MIN(lim - va, sz); 2711 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2712 if (pvo != NULL) { 2713 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2714 (va & ADDR_POFF); 2715 moea_syncicache(pa, len); 2716 } 2717 va += len; 2718 sz -= len; 2719 } 2720 PMAP_UNLOCK(pm); 2721} 2722 2723void 2724moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2725{ 2726 2727 *va = (void *)pa; 2728} 2729 2730extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2731 2732void 2733moea_scan_init(mmu_t mmu) 2734{ 2735 struct pvo_entry *pvo; 2736 vm_offset_t va; 2737 int i; 2738 2739 if (!do_minidump) { 2740 /* Initialize phys. segments for dumpsys(). */ 2741 memset(&dump_map, 0, sizeof(dump_map)); 2742 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2743 for (i = 0; i < pregions_sz; i++) { 2744 dump_map[i].pa_start = pregions[i].mr_start; 2745 dump_map[i].pa_size = pregions[i].mr_size; 2746 } 2747 return; 2748 } 2749 2750 /* Virtual segments for minidumps: */ 2751 memset(&dump_map, 0, sizeof(dump_map)); 2752 2753 /* 1st: kernel .data and .bss. */ 2754 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2755 dump_map[0].pa_size = 2756 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2757 2758 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2759 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2760 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2761 2762 /* 3rd: kernel VM. */ 2763 va = dump_map[1].pa_start + dump_map[1].pa_size; 2764 /* Find start of next chunk (from va). */ 2765 while (va < virtual_end) { 2766 /* Don't dump the buffer cache. */ 2767 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2768 va = kmi.buffer_eva; 2769 continue; 2770 } 2771 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 2772 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2773 break; 2774 va += PAGE_SIZE; 2775 } 2776 if (va < virtual_end) { 2777 dump_map[2].pa_start = va; 2778 va += PAGE_SIZE; 2779 /* Find last page in chunk. */ 2780 while (va < virtual_end) { 2781 /* Don't run into the buffer cache. */ 2782 if (va == kmi.buffer_sva) 2783 break; 2784 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, 2785 NULL); 2786 if (pvo == NULL || 2787 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2788 break; 2789 va += PAGE_SIZE; 2790 } 2791 dump_map[2].pa_size = va - dump_map[2].pa_start; 2792 } 2793} 2794