1/*- 2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0 3 * 4 * Copyright (c) 2014 Intel Corporation. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 * 34 * $FreeBSD$ 35 */ 36 37#if !defined(OPA_PORT_INFO_H) 38#define OPA_PORT_INFO_H 39 40#define OPA_PORT_LINK_MODE_NOP 0 /* No change */ 41#define OPA_PORT_LINK_MODE_OPA 4 /* Port mode is OPA */ 42 43#define OPA_PORT_PACKET_FORMAT_NOP 0 /* No change */ 44#define OPA_PORT_PACKET_FORMAT_8B 1 /* Format 8B */ 45#define OPA_PORT_PACKET_FORMAT_9B 2 /* Format 9B */ 46#define OPA_PORT_PACKET_FORMAT_10B 4 /* Format 10B */ 47#define OPA_PORT_PACKET_FORMAT_16B 8 /* Format 16B */ 48 49#define OPA_PORT_LTP_CRC_MODE_NONE 0 /* No change */ 50#define OPA_PORT_LTP_CRC_MODE_14 1 /* 14-bit LTP CRC mode (optional) */ 51#define OPA_PORT_LTP_CRC_MODE_16 2 /* 16-bit LTP CRC mode */ 52#define OPA_PORT_LTP_CRC_MODE_48 4 /* 48-bit LTP CRC mode (optional) */ 53#define OPA_PORT_LTP_CRC_MODE_PER_LANE 8 /* 12/16-bit per lane LTP CRC mode */ 54 55/* Link Down / Neighbor Link Down Reason; indicated as follows: */ 56#define OPA_LINKDOWN_REASON_NONE 0 /* No specified reason */ 57#define OPA_LINKDOWN_REASON_RCV_ERROR_0 1 58#define OPA_LINKDOWN_REASON_BAD_PKT_LEN 2 59#define OPA_LINKDOWN_REASON_PKT_TOO_LONG 3 60#define OPA_LINKDOWN_REASON_PKT_TOO_SHORT 4 61#define OPA_LINKDOWN_REASON_BAD_SLID 5 62#define OPA_LINKDOWN_REASON_BAD_DLID 6 63#define OPA_LINKDOWN_REASON_BAD_L2 7 64#define OPA_LINKDOWN_REASON_BAD_SC 8 65#define OPA_LINKDOWN_REASON_RCV_ERROR_8 9 66#define OPA_LINKDOWN_REASON_BAD_MID_TAIL 10 67#define OPA_LINKDOWN_REASON_RCV_ERROR_10 11 68#define OPA_LINKDOWN_REASON_PREEMPT_ERROR 12 69#define OPA_LINKDOWN_REASON_PREEMPT_VL15 13 70#define OPA_LINKDOWN_REASON_BAD_VL_MARKER 14 71#define OPA_LINKDOWN_REASON_RCV_ERROR_14 15 72#define OPA_LINKDOWN_REASON_RCV_ERROR_15 16 73#define OPA_LINKDOWN_REASON_BAD_HEAD_DIST 17 74#define OPA_LINKDOWN_REASON_BAD_TAIL_DIST 18 75#define OPA_LINKDOWN_REASON_BAD_CTRL_DIST 19 76#define OPA_LINKDOWN_REASON_BAD_CREDIT_ACK 20 77#define OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER 21 78#define OPA_LINKDOWN_REASON_BAD_PREEMPT 22 79#define OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT 23 80#define OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT 24 81#define OPA_LINKDOWN_REASON_RCV_ERROR_24 25 82#define OPA_LINKDOWN_REASON_RCV_ERROR_25 26 83#define OPA_LINKDOWN_REASON_RCV_ERROR_26 27 84#define OPA_LINKDOWN_REASON_RCV_ERROR_27 28 85#define OPA_LINKDOWN_REASON_RCV_ERROR_28 29 86#define OPA_LINKDOWN_REASON_RCV_ERROR_29 30 87#define OPA_LINKDOWN_REASON_RCV_ERROR_30 31 88#define OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN 32 89#define OPA_LINKDOWN_REASON_UNKNOWN 33 90/* 34 -reserved */ 91#define OPA_LINKDOWN_REASON_REBOOT 35 92#define OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN 36 93/* 37-38 reserved */ 94#define OPA_LINKDOWN_REASON_FM_BOUNCE 39 95#define OPA_LINKDOWN_REASON_SPEED_POLICY 40 96#define OPA_LINKDOWN_REASON_WIDTH_POLICY 41 97/* 42-48 reserved */ 98#define OPA_LINKDOWN_REASON_DISCONNECTED 49 99#define OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED 50 100#define OPA_LINKDOWN_REASON_NOT_INSTALLED 51 101#define OPA_LINKDOWN_REASON_CHASSIS_CONFIG 52 102/* 53 reserved */ 103#define OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED 54 104/* 55 reserved */ 105#define OPA_LINKDOWN_REASON_POWER_POLICY 56 106#define OPA_LINKDOWN_REASON_LINKSPEED_POLICY 57 107#define OPA_LINKDOWN_REASON_LINKWIDTH_POLICY 58 108/* 59 reserved */ 109#define OPA_LINKDOWN_REASON_SWITCH_MGMT 60 110#define OPA_LINKDOWN_REASON_SMA_DISABLED 61 111/* 62 reserved */ 112#define OPA_LINKDOWN_REASON_TRANSIENT 63 113/* 64-255 reserved */ 114 115/* OPA Link Init reason; indicated as follows: */ 116/* 3-7; 11-15 reserved; 8-15 cleared on Polling->LinkUp */ 117#define OPA_LINKINIT_REASON_NOP 0 118#define OPA_LINKINIT_REASON_LINKUP (1 << 4) 119#define OPA_LINKINIT_REASON_FLAPPING (2 << 4) 120#define OPA_LINKINIT_REASON_CLEAR (8 << 4) 121#define OPA_LINKINIT_OUTSIDE_POLICY (8 << 4) 122#define OPA_LINKINIT_QUARANTINED (9 << 4) 123#define OPA_LINKINIT_INSUFIC_CAPABILITY (10 << 4) 124 125#define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */ 126#define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */ 127#define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */ 128 129#define OPA_LINK_WIDTH_1X 0x0001 130#define OPA_LINK_WIDTH_2X 0x0002 131#define OPA_LINK_WIDTH_3X 0x0004 132#define OPA_LINK_WIDTH_4X 0x0008 133 134#define OPA_CAP_MASK3_IsSnoopSupported (1 << 7) 135#define OPA_CAP_MASK3_IsAsyncSC2VLSupported (1 << 6) 136#define OPA_CAP_MASK3_IsAddrRangeConfigSupported (1 << 5) 137#define OPA_CAP_MASK3_IsPassThroughSupported (1 << 4) 138#define OPA_CAP_MASK3_IsSharedSpaceSupported (1 << 3) 139/* reserved (1 << 2) */ 140#define OPA_CAP_MASK3_IsVLMarkerSupported (1 << 1) 141#define OPA_CAP_MASK3_IsVLrSupported (1 << 0) 142 143/** 144 * new MTU values 145 */ 146enum { 147 OPA_MTU_8192 = 6, 148 OPA_MTU_10240 = 7, 149}; 150 151enum { 152 OPA_PORT_PHYS_CONF_DISCONNECTED = 0, 153 OPA_PORT_PHYS_CONF_STANDARD = 1, 154 OPA_PORT_PHYS_CONF_FIXED = 2, 155 OPA_PORT_PHYS_CONF_VARIABLE = 3, 156 OPA_PORT_PHYS_CONF_SI_PHOTO = 4 157}; 158 159enum port_info_field_masks { 160 /* vl.cap */ 161 OPA_PI_MASK_VL_CAP = 0x1F, 162 /* port_states.ledenable_offlinereason */ 163 OPA_PI_MASK_OFFLINE_REASON = 0x0F, 164 OPA_PI_MASK_LED_ENABLE = 0x40, 165 /* port_states.unsleepstate_downdefstate */ 166 OPA_PI_MASK_UNSLEEP_STATE = 0xF0, 167 OPA_PI_MASK_DOWNDEF_STATE = 0x0F, 168 /* port_states.portphysstate_portstate */ 169 OPA_PI_MASK_PORT_PHYSICAL_STATE = 0xF0, 170 OPA_PI_MASK_PORT_STATE = 0x0F, 171 /* port_phys_conf */ 172 OPA_PI_MASK_PORT_PHYSICAL_CONF = 0x0F, 173 /* collectivemask_multicastmask */ 174 OPA_PI_MASK_COLLECT_MASK = 0x38, 175 OPA_PI_MASK_MULTICAST_MASK = 0x07, 176 /* mkeyprotect_lmc */ 177 OPA_PI_MASK_MKEY_PROT_BIT = 0xC0, 178 OPA_PI_MASK_LMC = 0x0F, 179 /* smsl */ 180 OPA_PI_MASK_SMSL = 0x1F, 181 /* partenforce_filterraw */ 182 /* Filter Raw In/Out bits 1 and 2 were removed */ 183 OPA_PI_MASK_LINKINIT_REASON = 0xF0, 184 OPA_PI_MASK_PARTITION_ENFORCE_IN = 0x08, 185 OPA_PI_MASK_PARTITION_ENFORCE_OUT = 0x04, 186 /* operational_vls */ 187 OPA_PI_MASK_OPERATIONAL_VL = 0x1F, 188 /* sa_qp */ 189 OPA_PI_MASK_SA_QP = 0x00FFFFFF, 190 /* sm_trap_qp */ 191 OPA_PI_MASK_SM_TRAP_QP = 0x00FFFFFF, 192 /* localphy_overrun_errors */ 193 OPA_PI_MASK_LOCAL_PHY_ERRORS = 0xF0, 194 OPA_PI_MASK_OVERRUN_ERRORS = 0x0F, 195 /* clientrereg_subnettimeout */ 196 OPA_PI_MASK_CLIENT_REREGISTER = 0x80, 197 OPA_PI_MASK_SUBNET_TIMEOUT = 0x1F, 198 /* port_link_mode */ 199 OPA_PI_MASK_PORT_LINK_SUPPORTED = (0x001F << 10), 200 OPA_PI_MASK_PORT_LINK_ENABLED = (0x001F << 5), 201 OPA_PI_MASK_PORT_LINK_ACTIVE = (0x001F << 0), 202 /* port_link_crc_mode */ 203 OPA_PI_MASK_PORT_LINK_CRC_SUPPORTED = 0x0F00, 204 OPA_PI_MASK_PORT_LINK_CRC_ENABLED = 0x00F0, 205 OPA_PI_MASK_PORT_LINK_CRC_ACTIVE = 0x000F, 206 /* port_mode */ 207 OPA_PI_MASK_PORT_MODE_SECURITY_CHECK = 0x0001, 208 OPA_PI_MASK_PORT_MODE_16B_TRAP_QUERY = 0x0002, 209 OPA_PI_MASK_PORT_MODE_PKEY_CONVERT = 0x0004, 210 OPA_PI_MASK_PORT_MODE_SC2SC_MAPPING = 0x0008, 211 OPA_PI_MASK_PORT_MODE_VL_MARKER = 0x0010, 212 OPA_PI_MASK_PORT_PASS_THROUGH = 0x0020, 213 OPA_PI_MASK_PORT_ACTIVE_OPTOMIZE = 0x0040, 214 /* flit_control.interleave */ 215 OPA_PI_MASK_INTERLEAVE_DIST_SUP = (0x0003 << 12), 216 OPA_PI_MASK_INTERLEAVE_DIST_ENABLE = (0x0003 << 10), 217 OPA_PI_MASK_INTERLEAVE_MAX_NEST_TX = (0x001F << 5), 218 OPA_PI_MASK_INTERLEAVE_MAX_NEST_RX = (0x001F << 0), 219 220 /* port_error_action */ 221 OPA_PI_MASK_EX_BUFFER_OVERRUN = 0x80000000, 222 /* 7 bits reserved */ 223 OPA_PI_MASK_FM_CFG_ERR_EXCEED_MULTICAST_LIMIT = 0x00800000, 224 OPA_PI_MASK_FM_CFG_BAD_CONTROL_FLIT = 0x00400000, 225 OPA_PI_MASK_FM_CFG_BAD_PREEMPT = 0x00200000, 226 OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER = 0x00100000, 227 OPA_PI_MASK_FM_CFG_BAD_CRDT_ACK = 0x00080000, 228 OPA_PI_MASK_FM_CFG_BAD_CTRL_DIST = 0x00040000, 229 OPA_PI_MASK_FM_CFG_BAD_TAIL_DIST = 0x00020000, 230 OPA_PI_MASK_FM_CFG_BAD_HEAD_DIST = 0x00010000, 231 /* 2 bits reserved */ 232 OPA_PI_MASK_PORT_RCV_BAD_VL_MARKER = 0x00002000, 233 OPA_PI_MASK_PORT_RCV_PREEMPT_VL15 = 0x00001000, 234 OPA_PI_MASK_PORT_RCV_PREEMPT_ERROR = 0x00000800, 235 /* 1 bit reserved */ 236 OPA_PI_MASK_PORT_RCV_BAD_MidTail = 0x00000200, 237 /* 1 bit reserved */ 238 OPA_PI_MASK_PORT_RCV_BAD_SC = 0x00000080, 239 OPA_PI_MASK_PORT_RCV_BAD_L2 = 0x00000040, 240 OPA_PI_MASK_PORT_RCV_BAD_DLID = 0x00000020, 241 OPA_PI_MASK_PORT_RCV_BAD_SLID = 0x00000010, 242 OPA_PI_MASK_PORT_RCV_PKTLEN_TOOSHORT = 0x00000008, 243 OPA_PI_MASK_PORT_RCV_PKTLEN_TOOLONG = 0x00000004, 244 OPA_PI_MASK_PORT_RCV_BAD_PKTLEN = 0x00000002, 245 OPA_PI_MASK_PORT_RCV_BAD_LT = 0x00000001, 246 247 /* pass_through.res_drctl */ 248 OPA_PI_MASK_PASS_THROUGH_DR_CONTROL = 0x01, 249 250 /* buffer_units */ 251 OPA_PI_MASK_BUF_UNIT_VL15_INIT = (0x00000FFF << 11), 252 OPA_PI_MASK_BUF_UNIT_VL15_CREDIT_RATE = (0x0000001F << 6), 253 OPA_PI_MASK_BUF_UNIT_CREDIT_ACK = (0x00000003 << 3), 254 OPA_PI_MASK_BUF_UNIT_BUF_ALLOC = (0x00000003 << 0), 255 256 /* neigh_mtu.pvlx_to_mtu */ 257 OPA_PI_MASK_NEIGH_MTU_PVL0 = 0xF0, 258 OPA_PI_MASK_NEIGH_MTU_PVL1 = 0x0F, 259 260 /* neigh_mtu.vlstall_hoq_life */ 261 OPA_PI_MASK_VL_STALL = (0x03 << 5), 262 OPA_PI_MASK_HOQ_LIFE = (0x1F << 0), 263 264 /* port_neigh_mode */ 265 OPA_PI_MASK_NEIGH_MGMT_ALLOWED = (0x01 << 3), 266 OPA_PI_MASK_NEIGH_FW_AUTH_BYPASS = (0x01 << 2), 267 OPA_PI_MASK_NEIGH_NODE_TYPE = (0x03 << 0), 268 269 /* resptime_value */ 270 OPA_PI_MASK_RESPONSE_TIME_VALUE = 0x1F, 271 272 /* mtucap */ 273 OPA_PI_MASK_MTU_CAP = 0x0F, 274}; 275 276struct opa_port_states { 277 u8 reserved; 278 u8 ledenable_offlinereason; /* 1 res, 1 bit, 6 bits */ 279 u8 reserved2; 280 u8 portphysstate_portstate; /* 4 bits, 4 bits */ 281}; 282 283struct opa_port_state_info { 284 struct opa_port_states port_states; 285 __be16 link_width_downgrade_tx_active; 286 __be16 link_width_downgrade_rx_active; 287}; 288 289struct opa_port_info { 290 __be32 lid; 291 __be32 flow_control_mask; 292 293 struct { 294 u8 res; /* was inittype */ 295 u8 cap; /* 3 res, 5 bits */ 296 __be16 high_limit; 297 __be16 preempt_limit; 298 u8 arb_high_cap; 299 u8 arb_low_cap; 300 } vl; 301 302 struct opa_port_states port_states; 303 u8 port_phys_conf; /* 4 res, 4 bits */ 304 u8 collectivemask_multicastmask; /* 2 res, 3, 3 */ 305 u8 mkeyprotect_lmc; /* 2 bits, 2 res, 4 bits */ 306 u8 smsl; /* 3 res, 5 bits */ 307 308 u8 partenforce_filterraw; /* bit fields */ 309 u8 operational_vls; /* 3 res, 5 bits */ 310 __be16 pkey_8b; 311 __be16 pkey_10b; 312 __be16 mkey_violations; 313 314 __be16 pkey_violations; 315 __be16 qkey_violations; 316 __be32 sm_trap_qp; /* 8 bits, 24 bits */ 317 318 __be32 sa_qp; /* 8 bits, 24 bits */ 319 u8 neigh_port_num; 320 u8 link_down_reason; 321 u8 neigh_link_down_reason; 322 u8 clientrereg_subnettimeout; /* 1 bit, 2 bits, 5 */ 323 324 struct { 325 __be16 supported; 326 __be16 enabled; 327 __be16 active; 328 } link_speed; 329 struct { 330 __be16 supported; 331 __be16 enabled; 332 __be16 active; 333 } link_width; 334 struct { 335 __be16 supported; 336 __be16 enabled; 337 __be16 tx_active; 338 __be16 rx_active; 339 } link_width_downgrade; 340 __be16 port_link_mode; /* 1 res, 5 bits, 5 bits, 5 bits */ 341 __be16 port_ltp_crc_mode; /* 4 res, 4 bits, 4 bits, 4 bits */ 342 343 __be16 port_mode; /* 9 res, bit fields */ 344 struct { 345 __be16 supported; 346 __be16 enabled; 347 } port_packet_format; 348 struct { 349 __be16 interleave; /* 2 res, 2,2,5,5 */ 350 struct { 351 __be16 min_initial; 352 __be16 min_tail; 353 u8 large_pkt_limit; 354 u8 small_pkt_limit; 355 u8 max_small_pkt_limit; 356 u8 preemption_limit; 357 } preemption; 358 } flit_control; 359 360 __be32 reserved4; 361 __be32 port_error_action; /* bit field */ 362 363 struct { 364 u8 egress_port; 365 u8 res_drctl; /* 7 res, 1 */ 366 } pass_through; 367 __be16 mkey_lease_period; 368 __be32 buffer_units; /* 9 res, 12, 5, 3, 3 */ 369 370 __be32 reserved5; 371 __be32 sm_lid; 372 373 __be64 mkey; 374 375 __be64 subnet_prefix; 376 377 struct { 378 u8 pvlx_to_mtu[OPA_MAX_VLS/2]; /* 4 bits, 4 bits */ 379 } neigh_mtu; 380 381 struct { 382 u8 vlstall_hoqlife; /* 3 bits, 5 bits */ 383 } xmit_q[OPA_MAX_VLS]; 384 385 struct { 386 u8 addr[16]; 387 } ipaddr_ipv6; 388 389 struct { 390 u8 addr[4]; 391 } ipaddr_ipv4; 392 393 u32 reserved6; 394 u32 reserved7; 395 u32 reserved8; 396 397 __be64 neigh_node_guid; 398 399 __be32 ib_cap_mask; 400 __be16 reserved9; /* was ib_cap_mask2 */ 401 __be16 opa_cap_mask; 402 403 __be32 reserved10; /* was link_roundtrip_latency */ 404 __be16 overall_buffer_space; 405 __be16 reserved11; /* was max_credit_hint */ 406 407 __be16 diag_code; 408 struct { 409 u8 buffer; 410 u8 wire; 411 } replay_depth; 412 u8 port_neigh_mode; 413 u8 mtucap; /* 4 res, 4 bits */ 414 415 u8 resptimevalue; /* 3 res, 5 bits */ 416 u8 local_port_num; 417 u8 reserved12; 418 u8 reserved13; /* was guid_cap */ 419} __attribute__ ((packed)); 420 421#endif /* OPA_PORT_INFO_H */ 422