1/***********************license start*************** 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 5 * reserved. 6 * 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are 10 * met: 11 * 12 * * Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 15 * * Redistributions in binary form must reproduce the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer in the documentation and/or other materials provided 18 * with the distribution. 19 20 * * Neither the name of Cavium Networks nor the names of 21 * its contributors may be used to endorse or promote products 22 * derived from this software without specific prior written 23 * permission. 24 25 * This Software, including technical data, may be subject to U.S. export control 26 * laws, including the U.S. Export Administration Act and its associated 27 * regulations, and may be subject to export or import regulations in other 28 * countries. 29 30 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 31 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 32 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 33 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 34 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 35 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 36 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 37 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 38 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 39 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 40 ***********************license end**************************************/ 41 42#ifndef __OCTEON_IRQ_H__ 43#define __OCTEON_IRQ_H__ 44 45/* 46 * $FreeBSD$ 47 */ 48 49/** 50 * Enumeration of Interrupt numbers 51 */ 52typedef enum 53{ 54 /* 0 - 7 represent the 8 MIPS standard interrupt sources */ 55 OCTEON_IRQ_SW0 = 0, 56 OCTEON_IRQ_SW1 = 1, 57 OCTEON_IRQ_CIU0 = 2, 58 OCTEON_IRQ_CIU1 = 3, 59 OCTEON_IRQ_4 = 4, 60 OCTEON_IRQ_5 = 5, 61 OCTEON_IRQ_6 = 6, 62 OCTEON_IRQ_7 = 7, 63 64 /* 8 - 71 represent the sources in CIU_INTX_EN0 */ 65 OCTEON_IRQ_WORKQ0 = 8, 66 OCTEON_IRQ_WORKQ1 = 9, 67 OCTEON_IRQ_WORKQ2 = 10, 68 OCTEON_IRQ_WORKQ3 = 11, 69 OCTEON_IRQ_WORKQ4 = 12, 70 OCTEON_IRQ_WORKQ5 = 13, 71 OCTEON_IRQ_WORKQ6 = 14, 72 OCTEON_IRQ_WORKQ7 = 15, 73 OCTEON_IRQ_WORKQ8 = 16, 74 OCTEON_IRQ_WORKQ9 = 17, 75 OCTEON_IRQ_WORKQ10 = 18, 76 OCTEON_IRQ_WORKQ11 = 19, 77 OCTEON_IRQ_WORKQ12 = 20, 78 OCTEON_IRQ_WORKQ13 = 21, 79 OCTEON_IRQ_WORKQ14 = 22, 80 OCTEON_IRQ_WORKQ15 = 23, 81 OCTEON_IRQ_GPIO0 = 24, 82 OCTEON_IRQ_GPIO1 = 25, 83 OCTEON_IRQ_GPIO2 = 26, 84 OCTEON_IRQ_GPIO3 = 27, 85 OCTEON_IRQ_GPIO4 = 28, 86 OCTEON_IRQ_GPIO5 = 29, 87 OCTEON_IRQ_GPIO6 = 30, 88 OCTEON_IRQ_GPIO7 = 31, 89 OCTEON_IRQ_GPIO8 = 32, 90 OCTEON_IRQ_GPIO9 = 33, 91 OCTEON_IRQ_GPIO10 = 34, 92 OCTEON_IRQ_GPIO11 = 35, 93 OCTEON_IRQ_GPIO12 = 36, 94 OCTEON_IRQ_GPIO13 = 37, 95 OCTEON_IRQ_GPIO14 = 38, 96 OCTEON_IRQ_GPIO15 = 39, 97 OCTEON_IRQ_MBOX0 = 40, 98 OCTEON_IRQ_MBOX1 = 41, 99 OCTEON_IRQ_UART0 = 42, 100 OCTEON_IRQ_UART1 = 43, 101 OCTEON_IRQ_PCI_INT0 = 44, 102 OCTEON_IRQ_PCI_INT1 = 45, 103 OCTEON_IRQ_PCI_INT2 = 46, 104 OCTEON_IRQ_PCI_INT3 = 47, 105 OCTEON_IRQ_PCI_MSI0 = 48, 106 OCTEON_IRQ_PCI_MSI1 = 49, 107 OCTEON_IRQ_PCI_MSI2 = 50, 108 OCTEON_IRQ_PCI_MSI3 = 51, 109 OCTEON_IRQ_RESERVED44 = 52, 110 OCTEON_IRQ_TWSI = 53, 111 OCTEON_IRQ_RML = 54, 112 OCTEON_IRQ_TRACE = 55, 113 OCTEON_IRQ_GMX_DRP0 = 56, 114 OCTEON_IRQ_GMX_DRP1 = 57, /* Doesn't apply on CN52XX or CN63XX */ 115 OCTEON_IRQ_IPD_DRP = 58, 116 OCTEON_IRQ_KEY_ZERO = 59, /* Doesn't apply on CN52XX or CN63XX */ 117 OCTEON_IRQ_TIMER0 = 60, 118 OCTEON_IRQ_TIMER1 = 61, 119 OCTEON_IRQ_TIMER2 = 62, 120 OCTEON_IRQ_TIMER3 = 63, 121 OCTEON_IRQ_USB0 = 64, /* Doesn't apply on CN38XX or CN58XX */ 122 OCTEON_IRQ_PCM = 65, /* Doesn't apply on CN52XX or CN63XX */ 123 OCTEON_IRQ_MPI = 66, /* Doesn't apply on CN52XX or CN63XX */ 124 OCTEON_IRQ_TWSI2 = 67, /* Added in CN56XX */ 125 OCTEON_IRQ_POWIQ = 68, /* Added in CN56XX */ 126 OCTEON_IRQ_IPDPPTHR = 69, /* Added in CN56XX */ 127 OCTEON_IRQ_MII = 70, /* Added in CN56XX */ 128 OCTEON_IRQ_BOOTDMA = 71, /* Added in CN56XX */ 129 130 /* 72 - 135 represent the sources in CIU_INTX_EN1 */ 131 OCTEON_IRQ_WDOG0 = 72, 132 OCTEON_IRQ_WDOG1 = 73, 133 OCTEON_IRQ_WDOG2 = 74, 134 OCTEON_IRQ_WDOG3 = 75, 135 OCTEON_IRQ_WDOG4 = 76, 136 OCTEON_IRQ_WDOG5 = 77, 137 OCTEON_IRQ_WDOG6 = 78, 138 OCTEON_IRQ_WDOG7 = 79, 139 OCTEON_IRQ_WDOG8 = 80, 140 OCTEON_IRQ_WDOG9 = 81, 141 OCTEON_IRQ_WDOG10= 82, 142 OCTEON_IRQ_WDOG11= 83, 143 OCTEON_IRQ_WDOG12= 84, 144 OCTEON_IRQ_WDOG13= 85, 145 OCTEON_IRQ_WDOG14= 86, 146 OCTEON_IRQ_WDOG15= 87, 147 OCTEON_IRQ_UART2 = 88, /* Added in CN52XX */ 148 OCTEON_IRQ_USB1 = 89, /* Added in CN52XX */ 149 OCTEON_IRQ_MII1 = 90, /* Added in CN52XX */ 150 OCTEON_IRQ_NAND = 91, /* Added in CN52XX */ 151 OCTEON_IRQ_MIO = 92, /* Added in CN63XX */ 152 OCTEON_IRQ_IOB = 93, /* Added in CN63XX */ 153 OCTEON_IRQ_FPA = 94, /* Added in CN63XX */ 154 OCTEON_IRQ_POW = 95, /* Added in CN63XX */ 155 OCTEON_IRQ_L2C = 96, /* Added in CN63XX */ 156 OCTEON_IRQ_IPD = 97, /* Added in CN63XX */ 157 OCTEON_IRQ_PIP = 98, /* Added in CN63XX */ 158 OCTEON_IRQ_PKO = 99, /* Added in CN63XX */ 159 OCTEON_IRQ_ZIP = 100, /* Added in CN63XX */ 160 OCTEON_IRQ_TIM = 101, /* Added in CN63XX */ 161 OCTEON_IRQ_RAD = 102, /* Added in CN63XX */ 162 OCTEON_IRQ_KEY = 103, /* Added in CN63XX */ 163 OCTEON_IRQ_DFA = 104, /* Added in CN63XX */ 164 OCTEON_IRQ_USB = 105, /* Added in CN63XX */ 165 OCTEON_IRQ_SLI = 106, /* Added in CN63XX */ 166 OCTEON_IRQ_DPI = 107, /* Added in CN63XX */ 167 OCTEON_IRQ_AGX0 = 108, /* Added in CN63XX */ 168 /* 109 - 117 are reserved */ 169 OCTEON_IRQ_AGL = 118, /* Added in CN63XX */ 170 OCTEON_IRQ_PTP = 119, /* Added in CN63XX */ 171 OCTEON_IRQ_PEM0 = 120, /* Added in CN63XX */ 172 OCTEON_IRQ_PEM1 = 121, /* Added in CN63XX */ 173 OCTEON_IRQ_SRIO0 = 122, /* Added in CN63XX */ 174 OCTEON_IRQ_SRIO1 = 123, /* Added in CN63XX */ 175 OCTEON_IRQ_LMC0 = 124, /* Added in CN63XX */ 176 /* Interrupts 125 - 127 are reserved */ 177 OCTEON_IRQ_DFM = 128, /* Added in CN63XX */ 178 /* Interrupts 129 - 135 are reserved */ 179} octeon_irq_t; 180 181#define OCTEON_PMC_IRQ OCTEON_IRQ_4 182 183#endif 184