1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright 2015 Endless Mobile, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 */
6
7#include <dt-bindings/clock/meson8-ddr-clkc.h>
8#include <dt-bindings/clock/meson8b-clkc.h>
9#include <dt-bindings/gpio/meson8b-gpio.h>
10#include <dt-bindings/reset/amlogic,meson8b-reset.h>
11#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
12#include "meson.dtsi"
13
14/ {
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18
19		cpu0: cpu@200 {
20			device_type = "cpu";
21			compatible = "arm,cortex-a5";
22			next-level-cache = <&L2>;
23			reg = <0x200>;
24			enable-method = "amlogic,meson8b-smp";
25			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
26			operating-points-v2 = <&cpu_opp_table>;
27			clocks = <&clkc CLKID_CPUCLK>;
28		};
29
30		cpu1: cpu@201 {
31			device_type = "cpu";
32			compatible = "arm,cortex-a5";
33			next-level-cache = <&L2>;
34			reg = <0x201>;
35			enable-method = "amlogic,meson8b-smp";
36			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
37			operating-points-v2 = <&cpu_opp_table>;
38			clocks = <&clkc CLKID_CPUCLK>;
39		};
40
41		cpu2: cpu@202 {
42			device_type = "cpu";
43			compatible = "arm,cortex-a5";
44			next-level-cache = <&L2>;
45			reg = <0x202>;
46			enable-method = "amlogic,meson8b-smp";
47			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
48			operating-points-v2 = <&cpu_opp_table>;
49			clocks = <&clkc CLKID_CPUCLK>;
50		};
51
52		cpu3: cpu@203 {
53			device_type = "cpu";
54			compatible = "arm,cortex-a5";
55			next-level-cache = <&L2>;
56			reg = <0x203>;
57			enable-method = "amlogic,meson8b-smp";
58			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
59			operating-points-v2 = <&cpu_opp_table>;
60			clocks = <&clkc CLKID_CPUCLK>;
61		};
62	};
63
64	cpu_opp_table: opp-table {
65		compatible = "operating-points-v2";
66		opp-shared;
67
68		opp-96000000 {
69			opp-hz = /bits/ 64 <96000000>;
70			opp-microvolt = <860000>;
71		};
72		opp-192000000 {
73			opp-hz = /bits/ 64 <192000000>;
74			opp-microvolt = <860000>;
75		};
76		opp-312000000 {
77			opp-hz = /bits/ 64 <312000000>;
78			opp-microvolt = <860000>;
79		};
80		opp-408000000 {
81			opp-hz = /bits/ 64 <408000000>;
82			opp-microvolt = <860000>;
83		};
84		opp-504000000 {
85			opp-hz = /bits/ 64 <504000000>;
86			opp-microvolt = <860000>;
87		};
88		opp-600000000 {
89			opp-hz = /bits/ 64 <600000000>;
90			opp-microvolt = <860000>;
91		};
92		opp-720000000 {
93			opp-hz = /bits/ 64 <720000000>;
94			opp-microvolt = <860000>;
95		};
96		opp-816000000 {
97			opp-hz = /bits/ 64 <816000000>;
98			opp-microvolt = <900000>;
99		};
100		opp-1008000000 {
101			opp-hz = /bits/ 64 <1008000000>;
102			opp-microvolt = <1140000>;
103		};
104		opp-1200000000 {
105			opp-hz = /bits/ 64 <1200000000>;
106			opp-microvolt = <1140000>;
107		};
108		opp-1320000000 {
109			opp-hz = /bits/ 64 <1320000000>;
110			opp-microvolt = <1140000>;
111		};
112		opp-1488000000 {
113			opp-hz = /bits/ 64 <1488000000>;
114			opp-microvolt = <1140000>;
115		};
116		opp-1536000000 {
117			opp-hz = /bits/ 64 <1536000000>;
118			opp-microvolt = <1140000>;
119		};
120	};
121
122	gpu_opp_table: gpu-opp-table {
123		compatible = "operating-points-v2";
124
125		opp-255000000 {
126			opp-hz = /bits/ 64 <255000000>;
127			opp-microvolt = <1100000>;
128		};
129		opp-364285714 {
130			opp-hz = /bits/ 64 <364285714>;
131			opp-microvolt = <1100000>;
132		};
133		opp-425000000 {
134			opp-hz = /bits/ 64 <425000000>;
135			opp-microvolt = <1100000>;
136		};
137		opp-510000000 {
138			opp-hz = /bits/ 64 <510000000>;
139			opp-microvolt = <1100000>;
140		};
141		opp-637500000 {
142			opp-hz = /bits/ 64 <637500000>;
143			opp-microvolt = <1100000>;
144			turbo-mode;
145		};
146	};
147
148	pmu {
149		compatible = "arm,cortex-a5-pmu";
150		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
151			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
152			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
153			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
154		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
155	};
156
157	reserved-memory {
158		#address-cells = <1>;
159		#size-cells = <1>;
160		ranges;
161
162		/* 2 MiB reserved for Hardware ROM Firmware? */
163		hwrom@0 {
164			reg = <0x0 0x200000>;
165			no-map;
166		};
167	};
168
169	mmcbus: bus@c8000000 {
170		compatible = "simple-bus";
171		reg = <0xc8000000 0x8000>;
172		#address-cells = <1>;
173		#size-cells = <1>;
174		ranges = <0x0 0xc8000000 0x8000>;
175
176		ddr_clkc: clock-controller@400 {
177			compatible = "amlogic,meson8b-ddr-clkc";
178			reg = <0x400 0x20>;
179			clocks = <&xtal>;
180			clock-names = "xtal";
181			#clock-cells = <1>;
182		};
183
184		dmcbus: bus@6000 {
185			compatible = "simple-bus";
186			reg = <0x6000 0x400>;
187			#address-cells = <1>;
188			#size-cells = <1>;
189			ranges = <0x0 0x6000 0x400>;
190
191			canvas: video-lut@48 {
192				compatible = "amlogic,meson8b-canvas",
193					     "amlogic,canvas";
194				reg = <0x48 0x14>;
195			};
196		};
197	};
198
199	apb: bus@d0000000 {
200		compatible = "simple-bus";
201		reg = <0xd0000000 0x200000>;
202		#address-cells = <1>;
203		#size-cells = <1>;
204		ranges = <0x0 0xd0000000 0x200000>;
205
206		mali: gpu@c0000 {
207			compatible = "amlogic,meson8b-mali", "arm,mali-450";
208			reg = <0xc0000 0x40000>;
209			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
210				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
211				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
212				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
213				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
214				     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
215				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
216				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
217			interrupt-names = "gp", "gpmmu", "pp", "pmu",
218					  "pp0", "ppmmu0", "pp1", "ppmmu1";
219			resets = <&reset RESET_MALI>;
220			clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
221			clock-names = "bus", "core";
222			operating-points-v2 = <&gpu_opp_table>;
223		};
224	};
225}; /* end of / */
226
227&aobus {
228	pmu: pmu@e0 {
229		compatible = "amlogic,meson8b-pmu", "syscon";
230		reg = <0xe0 0x18>;
231	};
232
233	pinctrl_aobus: pinctrl@84 {
234		compatible = "amlogic,meson8b-aobus-pinctrl";
235		reg = <0x84 0xc>;
236		#address-cells = <1>;
237		#size-cells = <1>;
238		ranges;
239
240		gpio_ao: ao-bank@14 {
241			reg = <0x14 0x4>,
242				<0x2c 0x4>,
243				<0x24 0x8>;
244			reg-names = "mux", "pull", "gpio";
245			gpio-controller;
246			#gpio-cells = <2>;
247			gpio-ranges = <&pinctrl_aobus 0 0 16>;
248		};
249
250		uart_ao_a_pins: uart_ao_a {
251			mux {
252				groups = "uart_tx_ao_a", "uart_rx_ao_a";
253				function = "uart_ao";
254				bias-disable;
255			};
256		};
257
258		ir_recv_pins: remote {
259			mux {
260				groups = "remote_input";
261				function = "remote";
262				bias-disable;
263			};
264		};
265	};
266};
267
268&cbus {
269	reset: reset-controller@4404 {
270		compatible = "amlogic,meson8b-reset";
271		reg = <0x4404 0x9c>;
272		#reset-cells = <1>;
273	};
274
275	analog_top: analog-top@81a8 {
276		compatible = "amlogic,meson8b-analog-top", "syscon";
277		reg = <0x81a8 0x14>;
278	};
279
280	pwm_ef: pwm@86c0 {
281		compatible = "amlogic,meson8b-pwm";
282		reg = <0x86c0 0x10>;
283		#pwm-cells = <3>;
284		status = "disabled";
285	};
286
287	clock-measure@8758 {
288		compatible = "amlogic,meson8b-clk-measure";
289		reg = <0x8758 0x1c>;
290	};
291
292	pinctrl_cbus: pinctrl@9880 {
293		compatible = "amlogic,meson8b-cbus-pinctrl";
294		reg = <0x9880 0x10>;
295		#address-cells = <1>;
296		#size-cells = <1>;
297		ranges;
298
299		gpio: banks@80b0 {
300			reg = <0x80b0 0x28>,
301				<0x80e8 0x18>,
302				<0x8120 0x18>,
303				<0x8030 0x38>;
304			reg-names = "mux", "pull", "pull-enable", "gpio";
305			gpio-controller;
306			#gpio-cells = <2>;
307			gpio-ranges = <&pinctrl_cbus 0 0 83>;
308		};
309
310		eth_rgmii_pins: eth-rgmii {
311			mux {
312				groups = "eth_tx_clk",
313					 "eth_tx_en",
314					 "eth_txd1_0",
315					 "eth_txd0_0",
316					 "eth_rx_clk",
317					 "eth_rx_dv",
318					 "eth_rxd1",
319					 "eth_rxd0",
320					 "eth_mdio_en",
321					 "eth_mdc",
322					 "eth_ref_clk",
323					 "eth_txd2",
324					 "eth_txd3",
325					 "eth_rxd3",
326					 "eth_rxd2";
327				function = "ethernet";
328				bias-disable;
329			};
330		};
331
332		eth_rmii_pins: eth-rmii {
333			mux {
334				groups = "eth_tx_en",
335					 "eth_txd1_0",
336					 "eth_txd0_0",
337					 "eth_rx_clk",
338					 "eth_rx_dv",
339					 "eth_rxd1",
340					 "eth_rxd0",
341					 "eth_mdio_en",
342					 "eth_mdc";
343				function = "ethernet";
344				bias-disable;
345			};
346		};
347
348		i2c_a_pins: i2c-a {
349			mux {
350				groups = "i2c_sda_a", "i2c_sck_a";
351				function = "i2c_a";
352				bias-disable;
353			};
354		};
355
356		sd_b_pins: sd-b {
357			mux {
358				groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
359					"sd_d3_b", "sd_clk_b", "sd_cmd_b";
360				function = "sd_b";
361				bias-disable;
362			};
363		};
364
365		pwm_c1_pins: pwm-c1 {
366			mux {
367				groups = "pwm_c1";
368				function = "pwm_c";
369				bias-disable;
370			};
371		};
372
373		pwm_d_pins: pwm-d {
374			mux {
375				groups = "pwm_d";
376				function = "pwm_d";
377				bias-disable;
378			};
379		};
380
381		uart_b0_pins: uart-b0 {
382			mux {
383				groups = "uart_tx_b0",
384				       "uart_rx_b0";
385				function = "uart_b";
386				bias-disable;
387			};
388		};
389
390		uart_b0_cts_rts_pins: uart-b0-cts-rts {
391			mux {
392				groups = "uart_cts_b0",
393				       "uart_rts_b0";
394				function = "uart_b";
395				bias-disable;
396			};
397		};
398	};
399};
400
401&ahb_sram {
402	smp-sram@1ff80 {
403		compatible = "amlogic,meson8b-smp-sram";
404		reg = <0x1ff80 0x8>;
405	};
406};
407
408
409&efuse {
410	compatible = "amlogic,meson8b-efuse";
411	clocks = <&clkc CLKID_EFUSE>;
412	clock-names = "core";
413
414	temperature_calib: calib@1f4 {
415		/* only the upper two bytes are relevant */
416		reg = <0x1f4 0x4>;
417	};
418};
419
420&ethmac {
421	compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
422
423	reg = <0xc9410000 0x10000
424	       0xc1108140 0x4>;
425
426	clocks = <&clkc CLKID_ETH>,
427		 <&clkc CLKID_MPLL2>,
428		 <&clkc CLKID_MPLL2>;
429	clock-names = "stmmaceth", "clkin0", "clkin1";
430	rx-fifo-depth = <4096>;
431	tx-fifo-depth = <2048>;
432
433	resets = <&reset RESET_ETHERNET>;
434	reset-names = "stmmaceth";
435};
436
437&gpio_intc {
438	compatible = "amlogic,meson-gpio-intc",
439		     "amlogic,meson8b-gpio-intc";
440	status = "okay";
441};
442
443&hhi {
444	clkc: clock-controller {
445		compatible = "amlogic,meson8b-clkc";
446		clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
447		clock-names = "xtal", "ddr_pll";
448		#clock-cells = <1>;
449		#reset-cells = <1>;
450	};
451};
452
453&hwrng {
454	compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
455	clocks = <&clkc CLKID_RNG0>;
456	clock-names = "core";
457};
458
459&i2c_AO {
460	clocks = <&clkc CLKID_CLK81>;
461};
462
463&i2c_A {
464	clocks = <&clkc CLKID_I2C>;
465};
466
467&i2c_B {
468	clocks = <&clkc CLKID_I2C>;
469};
470
471&L2 {
472	arm,data-latency = <3 3 3>;
473	arm,tag-latency = <2 2 2>;
474	arm,filter-ranges = <0x100000 0xc0000000>;
475	prefetch-data = <1>;
476	prefetch-instr = <1>;
477	arm,shared-override;
478};
479
480&periph {
481	scu@0 {
482		compatible = "arm,cortex-a5-scu";
483		reg = <0x0 0x100>;
484	};
485
486	timer@200 {
487		compatible = "arm,cortex-a5-global-timer";
488		reg = <0x200 0x20>;
489		interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
490		clocks = <&clkc CLKID_PERIPH>;
491
492		/*
493		 * the arm_global_timer driver currently does not handle clock
494		 * rate changes. Keep it disabled for now.
495		 */
496		status = "disabled";
497	};
498
499	timer@600 {
500		compatible = "arm,cortex-a5-twd-timer";
501		reg = <0x600 0x20>;
502		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
503		clocks = <&clkc CLKID_PERIPH>;
504	};
505};
506
507&pwm_ab {
508	compatible = "amlogic,meson8b-pwm";
509};
510
511&pwm_cd {
512	compatible = "amlogic,meson8b-pwm";
513};
514
515&rtc {
516	compatible = "amlogic,meson8b-rtc";
517	resets = <&reset RESET_RTC>;
518};
519
520&saradc {
521	compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
522	clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
523	clock-names = "clkin", "core";
524	amlogic,hhi-sysctrl = <&hhi>;
525	nvmem-cells = <&temperature_calib>;
526	nvmem-cell-names = "temperature_calib";
527};
528
529&sdio {
530	compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
531	clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
532	clock-names = "core", "clkin";
533};
534
535&timer_abcde {
536	clocks = <&xtal>, <&clkc CLKID_CLK81>;
537	clock-names = "xtal", "pclk";
538};
539
540&uart_AO {
541	compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
542	clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;
543	clock-names = "baud", "xtal", "pclk";
544};
545
546&uart_A {
547	compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
548	clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;
549	clock-names = "baud", "xtal", "pclk";
550};
551
552&uart_B {
553	compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
554	clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;
555	clock-names = "baud", "xtal", "pclk";
556};
557
558&uart_C {
559	compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
560	clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;
561	clock-names = "baud", "xtal", "pclk";
562};
563
564&usb0 {
565	compatible = "amlogic,meson8b-usb", "snps,dwc2";
566	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
567	clock-names = "otg";
568};
569
570&usb1 {
571	compatible = "amlogic,meson8b-usb", "snps,dwc2";
572	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
573	clock-names = "otg";
574};
575
576&usb0_phy {
577	compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
578	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
579	clock-names = "usb_general", "usb";
580	resets = <&reset RESET_USB_OTG>;
581};
582
583&usb1_phy {
584	compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
585	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
586	clock-names = "usb_general", "usb";
587	resets = <&reset RESET_USB_OTG>;
588};
589
590&wdt {
591	compatible = "amlogic,meson8b-wdt";
592};
593