1/*- 2 * Copyright (c) 2015 John Wehle <john@feith.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29/include/ "meson.dtsi" 30 31/ { 32 model = "Amlogic Meson8b SoC"; 33 compatible = "amlogic,meson8b"; 34 35 interrupt-parent = <&gic>; 36 37 cpus { 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 cpu@200 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a5"; 44 next-level-cache = <&L2>; 45 reg = <0x200>; 46 }; 47 48 cpu@201 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a5"; 51 next-level-cache = <&L2>; 52 reg = <0x201>; 53 }; 54 55 cpu@202 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a5"; 58 next-level-cache = <&L2>; 59 reg = <0x202>; 60 }; 61 62 cpu@203 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a5"; 65 next-level-cache = <&L2>; 66 reg = <0x203>; 67 }; 68 }; 69 70 clk81: clk@0 { 71 #clock-cells = <0>; 72 compatible = "fixed-clock"; 73 clock-frequency = <0>; 74 }; 75}; 76 77&L2 { 78 interrupts = <0 143 1>; 79}; 80