1/* $FreeBSD$ */ 2 3/*- 4 * Copyright (c) 2006,2007 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#define WPI_TX_RING_COUNT 256 21#define WPI_TX_RING_LOMARK 192 22#define WPI_TX_RING_HIMARK 224 23 24#ifdef DIAGNOSTIC 25#define WPI_RX_RING_COUNT_LOG 8 26#else 27#define WPI_RX_RING_COUNT_LOG 6 28#endif 29 30#define WPI_RX_RING_COUNT (1 << WPI_RX_RING_COUNT_LOG) 31 32#define WPI_NTXQUEUES 8 33#define WPI_DRV_NTXQUEUES 5 34#define WPI_CMD_QUEUE_NUM 4 35 36#define WPI_NDMACHNLS 6 37 38/* Maximum scatter/gather. */ 39#define WPI_MAX_SCATTER 4 40 41/* 42 * Rings must be aligned on a 16K boundary. 43 */ 44#define WPI_RING_DMA_ALIGN 0x4000 45 46/* Maximum Rx buffer size. */ 47#define WPI_RBUF_SIZE ( 3 * 1024 ) /* XXX 3000 but must be aligned */ 48 49/* 50 * Control and status registers. 51 */ 52#define WPI_HW_IF_CONFIG 0x000 53#define WPI_INT 0x008 54#define WPI_INT_MASK 0x00c 55#define WPI_FH_INT 0x010 56#define WPI_GPIO_IN 0x018 57#define WPI_RESET 0x020 58#define WPI_GP_CNTRL 0x024 59#define WPI_EEPROM 0x02c 60#define WPI_EEPROM_GP 0x030 61#define WPI_GIO 0x03c 62#define WPI_UCODE_GP1 0x054 63#define WPI_UCODE_GP1_SET 0x058 64#define WPI_UCODE_GP1_CLR 0x05c 65#define WPI_UCODE_GP2 0x060 66#define WPI_GIO_CHICKEN 0x100 67#define WPI_ANA_PLL 0x20c 68#define WPI_DBG_HPET_MEM 0x240 69#define WPI_MEM_RADDR 0x40c 70#define WPI_MEM_WADDR 0x410 71#define WPI_MEM_WDATA 0x418 72#define WPI_MEM_RDATA 0x41c 73#define WPI_PRPH_WADDR 0x444 74#define WPI_PRPH_RADDR 0x448 75#define WPI_PRPH_WDATA 0x44c 76#define WPI_PRPH_RDATA 0x450 77#define WPI_HBUS_TARG_WRPTR 0x460 78 79/* 80 * Flow-Handler registers. 81 */ 82#define WPI_FH_CBBC_CTRL(qid) (0x940 + (qid) * 8) 83#define WPI_FH_CBBC_BASE(qid) (0x944 + (qid) * 8) 84#define WPI_FH_RX_CONFIG 0xc00 85#define WPI_FH_RX_BASE 0xc04 86#define WPI_FH_RX_WPTR 0xc20 87#define WPI_FH_RX_RPTR_ADDR 0xc24 88#define WPI_FH_RSSR_TBL 0xcc0 89#define WPI_FH_RX_STATUS 0xcc4 90#define WPI_FH_TX_CONFIG(qid) (0xd00 + (qid) * 32) 91#define WPI_FH_TX_BASE 0xe80 92#define WPI_FH_MSG_CONFIG 0xe88 93#define WPI_FH_TX_STATUS 0xe90 94 95/* 96 * NIC internal memory offsets. 97 */ 98#define WPI_ALM_SCHED_MODE 0x2e00 99#define WPI_ALM_SCHED_ARASTAT 0x2e04 100#define WPI_ALM_SCHED_TXFACT 0x2e10 101#define WPI_ALM_SCHED_TXF4MF 0x2e14 102#define WPI_ALM_SCHED_TXF5MF 0x2e20 103#define WPI_ALM_SCHED_SBYPASS_MODE1 0x2e2c 104#define WPI_ALM_SCHED_SBYPASS_MODE2 0x2e30 105#define WPI_APMG_CLK_CTRL 0x3000 106#define WPI_APMG_CLK_EN 0x3004 107#define WPI_APMG_CLK_DIS 0x3008 108#define WPI_APMG_PS 0x300c 109#define WPI_APMG_PCI_STT 0x3010 110#define WPI_APMG_RFKILL 0x3014 111#define WPI_BSM_WR_CTRL 0x3400 112#define WPI_BSM_WR_MEM_SRC 0x3404 113#define WPI_BSM_WR_MEM_DST 0x3408 114#define WPI_BSM_WR_DWCOUNT 0x340c 115#define WPI_BSM_DRAM_TEXT_ADDR 0x3490 116#define WPI_BSM_DRAM_TEXT_SIZE 0x3494 117#define WPI_BSM_DRAM_DATA_ADDR 0x3498 118#define WPI_BSM_DRAM_DATA_SIZE 0x349c 119#define WPI_BSM_SRAM_BASE 0x3800 120 121/* Possible flags for register WPI_HW_IF_CONFIG. */ 122#define WPI_HW_IF_CONFIG_ALM_MB (1 << 8) 123#define WPI_HW_IF_CONFIG_ALM_MM (1 << 9) 124#define WPI_HW_IF_CONFIG_SKU_MRC (1 << 10) 125#define WPI_HW_IF_CONFIG_REV_D (1 << 11) 126#define WPI_HW_IF_CONFIG_TYPE_B (1 << 12) 127 128/* Possible flags for registers WPI_PRPH_RADDR/WPI_PRPH_WADDR. */ 129#define WPI_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 130 131/* Possible values for WPI_BSM_WR_MEM_DST. */ 132#define WPI_FW_TEXT_BASE 0x00000000 133#define WPI_FW_DATA_BASE 0x00800000 134 135/* Possible flags for WPI_GPIO_IN. */ 136#define WPI_GPIO_IN_VMAIN (1 << 9) 137 138/* Possible flags for register WPI_RESET. */ 139#define WPI_RESET_NEVO (1 << 0) 140#define WPI_RESET_SW (1 << 7) 141#define WPI_RESET_MASTER_DISABLED (1 << 8) 142#define WPI_RESET_STOP_MASTER (1 << 9) 143 144/* Possible flags for register WPI_GP_CNTRL. */ 145#define WPI_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 146#define WPI_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 147#define WPI_GP_CNTRL_INIT_DONE (1 << 2) 148#define WPI_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 149#define WPI_GP_CNTRL_SLEEP (1 << 4) 150#define WPI_GP_CNTRL_PS_MASK (7 << 24) 151#define WPI_GP_CNTRL_MAC_PS (4 << 24) 152#define WPI_GP_CNTRL_RFKILL (1 << 27) 153 154/* Possible flags for register WPI_GIO_CHICKEN. */ 155#define WPI_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 156#define WPI_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 157 158/* Possible flags for register WPI_GIO. */ 159#define WPI_GIO_L0S_ENA (1 << 1) 160 161/* Possible flags for register WPI_FH_RX_CONFIG. */ 162#define WPI_FH_RX_CONFIG_DMA_ENA (1U << 31) 163#define WPI_FH_RX_CONFIG_RDRBD_ENA (1 << 29) 164#define WPI_FH_RX_CONFIG_WRSTATUS_ENA (1 << 27) 165#define WPI_FH_RX_CONFIG_MAXFRAG (1 << 24) 166#define WPI_FH_RX_CONFIG_NRBD(x) ((x) << 20) 167#define WPI_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 168#define WPI_FH_RX_CONFIG_IRQ_TIMEOUT(x) ((x) << 4) 169 170/* Possible flags for register WPI_ANA_PLL. */ 171#define WPI_ANA_PLL_INIT (1 << 24) 172 173/* Possible flags for register WPI_UCODE_GP1*. */ 174#define WPI_UCODE_GP1_MAC_SLEEP (1 << 0) 175#define WPI_UCODE_GP1_RFKILL (1 << 1) 176#define WPI_UCODE_GP1_CMD_BLOCKED (1 << 2) 177 178/* Possible flags for register WPI_FH_RX_STATUS. */ 179#define WPI_FH_RX_STATUS_IDLE (1 << 24) 180 181/* Possible flags for register WPI_BSM_WR_CTRL. */ 182#define WPI_BSM_WR_CTRL_START_EN (1 << 30) 183#define WPI_BSM_WR_CTRL_START (1U << 31) 184 185/* Possible flags for register WPI_INT. */ 186#define WPI_INT_ALIVE (1 << 0) 187#define WPI_INT_WAKEUP (1 << 1) 188#define WPI_INT_SW_RX (1 << 3) 189#define WPI_INT_SW_ERR (1 << 25) 190#define WPI_INT_FH_TX (1 << 27) 191#define WPI_INT_HW_ERR (1 << 29) 192#define WPI_INT_FH_RX (1U << 31) 193 194/* Shortcut. */ 195#define WPI_INT_MASK_DEF \ 196 (WPI_INT_SW_ERR | WPI_INT_HW_ERR | WPI_INT_FH_TX | \ 197 WPI_INT_FH_RX | WPI_INT_ALIVE | WPI_INT_WAKEUP | \ 198 WPI_INT_SW_RX) 199 200/* Possible flags for register WPI_FH_INT. */ 201#define WPI_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 202#define WPI_FH_INT_HI_PRIOR (1 << 30) 203/* Shortcuts for the above. */ 204#define WPI_FH_INT_RX \ 205 (WPI_FH_INT_RX_CHNL(0) | \ 206 WPI_FH_INT_RX_CHNL(1) | \ 207 WPI_FH_INT_RX_CHNL(2) | \ 208 WPI_FH_INT_HI_PRIOR) 209 210/* Possible flags for register WPI_FH_TX_STATUS. */ 211#define WPI_FH_TX_STATUS_IDLE(qid) \ 212 (1 << ((qid) + 24) | 1 << ((qid) + 16)) 213 214/* Possible flags for register WPI_EEPROM. */ 215#define WPI_EEPROM_READ_VALID (1 << 0) 216 217/* Possible flags for register WPI_EEPROM_GP. */ 218#define WPI_EEPROM_VERSION 0x00000007 219#define WPI_EEPROM_GP_IF_OWNER 0x00000180 220 221/* Possible flags for register WPI_APMG_PS. */ 222#define WPI_APMG_PS_PWR_SRC_MASK (3 << 24) 223 224/* Possible flags for registers WPI_APMG_CLK_*. */ 225#define WPI_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 226#define WPI_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 227 228/* Possible flags for register WPI_APMG_PCI_STT. */ 229#define WPI_APMG_PCI_STT_L1A_DIS (1 << 11) 230 231struct wpi_shared { 232 uint32_t txbase[WPI_NTXQUEUES]; 233 uint32_t next; 234 uint32_t reserved[2]; 235} __packed; 236 237#define WPI_MAX_SEG_LEN 65520 238struct wpi_tx_desc { 239 uint8_t reserved1[3]; 240 uint8_t nsegs; 241#define WPI_PAD32(x) (roundup2(x, 4) - (x)) 242 243 struct { 244 uint32_t addr; 245 uint32_t len; 246 } __packed segs[WPI_MAX_SCATTER]; 247 uint8_t reserved2[28]; 248} __packed; 249 250struct wpi_tx_stat { 251 uint8_t rtsfailcnt; 252 uint8_t ackfailcnt; 253 uint8_t btkillcnt; 254 uint8_t rate; 255 uint32_t duration; 256 uint32_t status; 257#define WPI_TX_STATUS_SUCCESS 0x01 258#define WPI_TX_STATUS_DIRECT_DONE 0x02 259#define WPI_TX_STATUS_FAIL 0x80 260#define WPI_TX_STATUS_FAIL_SHORT_LIMIT 0x82 261#define WPI_TX_STATUS_FAIL_LONG_LIMIT 0x83 262#define WPI_TX_STATUS_FAIL_FIFO_UNDERRUN 0x84 263#define WPI_TX_STATUS_FAIL_MGMNT_ABORT 0x85 264#define WPI_TX_STATUS_FAIL_NEXT_FRAG 0x86 265#define WPI_TX_STATUS_FAIL_LIFE_EXPIRE 0x87 266#define WPI_TX_STATUS_FAIL_NODE_PS 0x88 267#define WPI_TX_STATUS_FAIL_ABORTED 0x89 268#define WPI_TX_STATUS_FAIL_BT_RETRY 0x8a 269#define WPI_TX_STATUS_FAIL_NODE_INVALID 0x8b 270#define WPI_TX_STATUS_FAIL_FRAG_DROPPED 0x8c 271#define WPI_TX_STATUS_FAIL_TID_DISABLE 0x8d 272#define WPI_TX_STATUS_FAIL_FRAME_FLUSHED 0x8e 273#define WPI_TX_STATUS_FAIL_INSUFFICIENT_CF_POLL 0x8f 274#define WPI_TX_STATUS_FAIL_TX_LOCKED 0x90 275#define WPI_TX_STATUS_FAIL_NO_BEACON_ON_RADAR 0x91 276 277} __packed; 278 279struct wpi_rx_desc { 280 uint32_t len; 281 uint8_t type; 282#define WPI_UC_READY 1 283#define WPI_RX_DONE 27 284#define WPI_TX_DONE 28 285#define WPI_START_SCAN 130 286#define WPI_SCAN_RESULTS 131 287#define WPI_STOP_SCAN 132 288#define WPI_BEACON_SENT 144 289#define WPI_RX_STATISTICS 156 290#define WPI_BEACON_STATISTICS 157 291#define WPI_STATE_CHANGED 161 292#define WPI_BEACON_MISSED 162 293 294 uint8_t flags; 295 uint8_t idx; 296 uint8_t qid; 297} __packed; 298 299#define WPI_RX_DESC_QID_MSK 0x07 300#define WPI_UNSOLICITED_RX_NOTIF 0x80 301 302struct wpi_rx_stat { 303 uint8_t len; 304#define WPI_STAT_MAXLEN 20 305 306 uint8_t id; 307 uint8_t rssi; /* received signal strength */ 308#define WPI_RSSI_OFFSET -95 309 310 uint8_t agc; /* access gain control */ 311 uint16_t signal; 312 uint16_t noise; 313} __packed; 314 315struct wpi_rx_head { 316 uint16_t chan; 317 uint16_t flags; 318#define WPI_STAT_FLAG_SHPREAMBLE (1 << 2) 319 320 uint8_t reserved; 321 uint8_t plcp; 322 uint16_t len; 323} __packed; 324 325struct wpi_rx_tail { 326 uint32_t flags; 327#define WPI_RX_NO_CRC_ERR (1 << 0) 328#define WPI_RX_NO_OVFL_ERR (1 << 1) 329/* shortcut for the above */ 330#define WPI_RX_NOERROR (WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR) 331#define WPI_RX_CIPHER_MASK (7 << 8) 332#define WPI_RX_CIPHER_CCMP (2 << 8) 333#define WPI_RX_DECRYPT_MASK (3 << 11) 334#define WPI_RX_DECRYPT_OK (3 << 11) 335 336 uint64_t tstamp; 337 uint32_t tbeacon; 338} __packed; 339 340struct wpi_tx_cmd { 341 uint8_t code; 342#define WPI_CMD_RXON 16 343#define WPI_CMD_RXON_ASSOC 17 344#define WPI_CMD_EDCA_PARAMS 19 345#define WPI_CMD_TIMING 20 346#define WPI_CMD_ADD_NODE 24 347#define WPI_CMD_DEL_NODE 25 348#define WPI_CMD_TX_DATA 28 349#define WPI_CMD_MRR_SETUP 71 350#define WPI_CMD_SET_LED 72 351#define WPI_CMD_SET_POWER_MODE 119 352#define WPI_CMD_SCAN 128 353#define WPI_CMD_SCAN_ABORT 129 354#define WPI_CMD_SET_BEACON 145 355#define WPI_CMD_TXPOWER 151 356#define WPI_CMD_BT_COEX 155 357#define WPI_CMD_GET_STATISTICS 156 358 359 uint8_t flags; 360 uint8_t idx; 361 uint8_t qid; 362 uint8_t data[124]; 363} __packed; 364 365/* Structure for command WPI_CMD_RXON. */ 366struct wpi_rxon { 367 uint8_t myaddr[IEEE80211_ADDR_LEN]; 368 uint16_t reserved1; 369 uint8_t bssid[IEEE80211_ADDR_LEN]; 370 uint16_t reserved2; 371 uint8_t wlap[IEEE80211_ADDR_LEN]; 372 uint16_t reserved3; 373 uint8_t mode; 374#define WPI_MODE_HOSTAP 1 375#define WPI_MODE_STA 3 376#define WPI_MODE_IBSS 4 377#define WPI_MODE_MONITOR 6 378 379 uint8_t air; 380 uint16_t reserved4; 381 uint8_t ofdm_mask; 382 uint8_t cck_mask; 383 uint16_t associd; 384 uint32_t flags; 385#define WPI_RXON_24GHZ (1 << 0) 386#define WPI_RXON_CCK (1 << 1) 387#define WPI_RXON_AUTO (1 << 2) 388#define WPI_RXON_SHSLOT (1 << 4) 389#define WPI_RXON_SHPREAMBLE (1 << 5) 390#define WPI_RXON_NODIVERSITY (1 << 7) 391#define WPI_RXON_ANTENNA_A (1 << 8) 392#define WPI_RXON_ANTENNA_B (1 << 9) 393#define WPI_RXON_TSF (1 << 15) 394#define WPI_RXON_CTS_TO_SELF (1 << 30) 395 396 uint32_t filter; 397#define WPI_FILTER_PROMISC (1 << 0) 398#define WPI_FILTER_CTL (1 << 1) 399#define WPI_FILTER_MULTICAST (1 << 2) 400#define WPI_FILTER_NODECRYPT (1 << 3) 401#define WPI_FILTER_BSS (1 << 5) 402#define WPI_FILTER_BEACON (1 << 6) 403#define WPI_FILTER_ASSOC (1 << 7) /* Accept associaton requests. */ 404 405 uint8_t chan; 406 uint16_t reserved5; 407} __packed; 408 409/* Structure for command WPI_CMD_RXON_ASSOC. */ 410struct wpi_assoc { 411 uint32_t flags; 412 uint32_t filter; 413 uint8_t ofdm_mask; 414 uint8_t cck_mask; 415 uint16_t reserved; 416} __packed; 417 418/* Structure for command WPI_CMD_EDCA_PARAMS. */ 419struct wpi_edca_params { 420 uint32_t flags; 421#define WPI_EDCA_UPDATE (1 << 0) 422 423 struct { 424 uint16_t cwmin; 425 uint16_t cwmax; 426 uint8_t aifsn; 427 uint8_t reserved; 428 uint16_t txoplimit; 429 } __packed ac[WME_NUM_AC]; 430} __packed; 431 432/* Structure for command WPI_CMD_TIMING. */ 433struct wpi_cmd_timing { 434 uint64_t tstamp; 435 uint16_t bintval; 436 uint16_t atim; 437 uint32_t binitval; 438 uint16_t lintval; 439 uint16_t reserved; 440} __packed; 441 442/* Structure for command WPI_CMD_ADD_NODE. */ 443struct wpi_node_info { 444 uint8_t control; 445#define WPI_NODE_UPDATE (1 << 0) 446 447 uint8_t reserved1[3]; 448 uint8_t macaddr[IEEE80211_ADDR_LEN]; 449 uint16_t reserved2; 450 uint8_t id; 451#define WPI_ID_BSS 0 452#define WPI_ID_IBSS_MIN 2 453#define WPI_ID_IBSS_MAX 23 454#define WPI_ID_BROADCAST 24 455#define WPI_ID_UNDEFINED (uint8_t)-1 456 457 uint8_t flags; 458#define WPI_FLAG_KEY_SET (1 << 0) 459 460 uint16_t reserved3; 461 uint16_t kflags; 462#define WPI_KFLAG_CCMP (1 << 1) 463#define WPI_KFLAG_KID(kid) ((kid) << 8) 464#define WPI_KFLAG_MULTICAST (1 << 14) 465 466 uint8_t tsc2; 467 uint8_t reserved4; 468 uint16_t ttak[5]; 469 uint16_t reserved5; 470 uint8_t key[IEEE80211_KEYBUF_SIZE]; 471 uint32_t action; 472#define WPI_ACTION_SET_RATE (1 << 2) 473 474 uint32_t mask; 475 uint16_t tid; 476 uint8_t plcp; 477 uint8_t antenna; 478#define WPI_ANTENNA_A (1 << 6) 479#define WPI_ANTENNA_B (1 << 7) 480#define WPI_ANTENNA_BOTH (WPI_ANTENNA_A | WPI_ANTENNA_B) 481 482 uint8_t add_imm; 483 uint8_t del_imm; 484 uint16_t add_imm_start; 485} __packed; 486 487/* Structure for command WPI_CMD_DEL_NODE. */ 488struct wpi_cmd_del_node { 489 uint8_t count; 490 uint8_t reserved1[3]; 491 uint8_t macaddr[IEEE80211_ADDR_LEN]; 492 uint16_t reserved2; 493} __packed; 494 495/* Structure for command WPI_CMD_TX_DATA. */ 496struct wpi_cmd_data { 497 uint16_t len; 498 uint16_t lnext; 499 uint32_t flags; 500#define WPI_TX_NEED_RTS (1 << 1) 501#define WPI_TX_NEED_CTS (1 << 2) 502#define WPI_TX_NEED_ACK (1 << 3) 503#define WPI_TX_FULL_TXOP (1 << 7) 504#define WPI_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 505#define WPI_TX_AUTO_SEQ (1 << 13) 506#define WPI_TX_MORE_FRAG (1 << 14) 507#define WPI_TX_INSERT_TSTAMP (1 << 16) 508 509 uint8_t plcp; 510 uint8_t id; 511 uint8_t tid; 512 uint8_t security; 513#define WPI_CIPHER_WEP 1 514#define WPI_CIPHER_CCMP 2 515#define WPI_CIPHER_TKIP 3 516#define WPI_CIPHER_WEP104 9 517 518 uint8_t key[IEEE80211_KEYBUF_SIZE]; 519 uint8_t tkip[IEEE80211_WEP_MICLEN]; 520 uint32_t fnext; 521#define WPI_NEXT_STA_ID(id) ((id) << 8) 522 523 uint32_t lifetime; 524#define WPI_LIFETIME_INFINITE 0xffffffff 525 526 uint8_t ofdm_mask; 527 uint8_t cck_mask; 528 uint8_t rts_ntries; 529 uint8_t data_ntries; 530 uint16_t timeout; 531 uint16_t txop; 532} __packed; 533 534/* Structure for command WPI_CMD_SET_BEACON. */ 535struct wpi_cmd_beacon { 536 uint16_t len; 537 uint16_t reserved1; 538 uint32_t flags; /* same as wpi_cmd_data */ 539 uint8_t plcp; 540 uint8_t id; 541 uint8_t reserved2[30]; 542 uint32_t lifetime; 543 uint8_t ofdm_mask; 544 uint8_t cck_mask; 545 uint16_t reserved3[3]; 546 uint16_t tim; 547 uint8_t timsz; 548 uint8_t reserved4; 549} __packed; 550 551/* Structure for notification WPI_BEACON_MISSED. */ 552struct wpi_beacon_missed { 553 uint32_t consecutive; 554 uint32_t total; 555 uint32_t expected; 556 uint32_t received; 557} __packed; 558 559/* Structure for command WPI_CMD_MRR_SETUP. */ 560#define WPI_RIDX_MAX 11 561struct wpi_mrr_setup { 562 uint32_t which; 563#define WPI_MRR_CTL 0 564#define WPI_MRR_DATA 1 565 566 struct { 567 uint8_t plcp; 568 uint8_t flags; 569 uint8_t ntries; 570#define WPI_NTRIES_DEFAULT 2 571 572 uint8_t next; 573 } __packed rates[WPI_RIDX_MAX + 1]; 574} __packed; 575 576/* Structure for command WPI_CMD_SET_LED. */ 577struct wpi_cmd_led { 578 uint32_t unit; /* multiplier (in usecs) */ 579 uint8_t which; 580#define WPI_LED_ACTIVITY 1 581#define WPI_LED_LINK 2 582 583 uint8_t off; 584 uint8_t on; 585 uint8_t reserved; 586} __packed; 587 588/* Structure for command WPI_CMD_SET_POWER_MODE. */ 589struct wpi_pmgt_cmd { 590 uint16_t flags; 591#define WPI_PS_ALLOW_SLEEP (1 << 0) 592#define WPI_PS_NOTIFY (1 << 1) 593#define WPI_PS_SLEEP_OVER_DTIM (1 << 2) 594#define WPI_PS_PCI_PMGT (1 << 3) 595 596 uint8_t reserved[2]; 597 uint32_t rxtimeout; 598 uint32_t txtimeout; 599 uint32_t intval[5]; 600} __packed; 601 602/* Structures for command WPI_CMD_SCAN. */ 603#define WPI_SCAN_MAX_ESSIDS 4 604struct wpi_scan_essid { 605 uint8_t id; 606 uint8_t len; 607 uint8_t data[IEEE80211_NWID_LEN]; 608} __packed; 609 610struct wpi_scan_hdr { 611 uint16_t len; 612 uint8_t reserved1; 613 uint8_t nchan; 614 uint16_t quiet_time; /* timeout in milliseconds */ 615#define WPI_QUIET_TIME_DEFAULT 10 616 617 uint16_t quiet_threshold; /* min # of packets */ 618 uint16_t crc_threshold; 619 uint16_t reserved2; 620 uint32_t max_svc; /* background scans */ 621 uint32_t pause_svc; /* background scans */ 622#define WPI_PAUSE_MAX_TIME ((1 << 20) - 1) 623#define WPI_PAUSE_SCAN(nbeacons, time) ((nbeacons << 24) | time) 624 625 uint32_t flags; 626 uint32_t filter; 627 628 /* Followed by a struct wpi_cmd_data. */ 629 /* Followed by an array of 4 structs wpi_scan_essid. */ 630 /* Followed by probe request body. */ 631 /* Followed by an array of ``nchan'' structs wpi_scan_chan. */ 632} __packed; 633 634struct wpi_scan_chan { 635 uint8_t flags; 636#define WPI_CHAN_ACTIVE (1 << 0) 637#define WPI_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 638 639 uint8_t chan; 640 uint8_t rf_gain; 641 uint8_t dsp_gain; 642 uint16_t active; /* msecs */ 643 uint16_t passive; /* msecs */ 644} __packed; 645 646#define WPI_SCAN_CRC_TH_DEFAULT htole16(1) 647#define WPI_SCAN_CRC_TH_NEVER htole16(0xffff) 648 649/* Maximum size of a scan command. */ 650#define WPI_SCAN_MAXSZ (MCLBYTES - 4) 651 652#define WPI_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 653#define WPI_ACTIVE_DWELL_TIME_5GHZ (20) 654#define WPI_ACTIVE_DWELL_FACTOR_2GHZ ( 3) 655#define WPI_ACTIVE_DWELL_FACTOR_5GHZ ( 2) 656 657#define WPI_PASSIVE_DWELL_TIME_2GHZ ( 20) 658#define WPI_PASSIVE_DWELL_TIME_5GHZ ( 10) 659#define WPI_PASSIVE_DWELL_BASE (100) 660#define WPI_CHANNEL_TUNE_TIME ( 6) 661 662/* Structure for command WPI_CMD_TXPOWER. */ 663struct wpi_cmd_txpower { 664 uint8_t band; 665#define WPI_BAND_5GHZ 0 666#define WPI_BAND_2GHZ 1 667 668 uint8_t reserved; 669 uint16_t chan; 670 671 struct { 672 uint8_t plcp; 673 uint8_t rf_gain; 674 uint8_t dsp_gain; 675 uint8_t reserved; 676 } __packed rates[WPI_RIDX_MAX + 1]; 677 678} __packed; 679 680/* Structure for command WPI_CMD_BT_COEX. */ 681struct wpi_bluetooth { 682 uint8_t flags; 683#define WPI_BT_COEX_DISABLE 0 684#define WPI_BT_COEX_MODE_2WIRE 1 685#define WPI_BT_COEX_MODE_3WIRE 2 686#define WPI_BT_COEX_MODE_4WIRE 3 687 688 uint8_t lead_time; 689#define WPI_BT_LEAD_TIME_DEF 30 690 691 uint8_t max_kill; 692#define WPI_BT_MAX_KILL_DEF 5 693 694 uint8_t reserved; 695 uint32_t kill_ack; 696 uint32_t kill_cts; 697} __packed; 698 699/* Structure for WPI_UC_READY notification. */ 700struct wpi_ucode_info { 701 uint8_t minor; 702 uint8_t major; 703 uint16_t reserved1; 704 uint8_t revision[8]; 705 uint8_t type; 706 uint8_t subtype; 707 uint16_t reserved2; 708 uint32_t logptr; 709 uint32_t errptr; 710 uint32_t tstamp; 711 uint32_t valid; 712} __packed; 713 714/* Structure for WPI_START_SCAN notification. */ 715struct wpi_start_scan { 716 uint64_t tstamp; 717 uint32_t tbeacon; 718 uint8_t chan; 719 uint8_t band; 720 uint16_t reserved; 721 uint32_t status; 722} __packed; 723 724/* Structure for WPI_STOP_SCAN notification. */ 725struct wpi_stop_scan { 726 uint8_t nchan; 727 uint8_t status; 728#define WPI_SCAN_COMPLETED 1 729#define WPI_SCAN_ABORTED 2 730 731 uint8_t reserved; 732 uint8_t chan; 733 uint64_t tsf; 734} __packed; 735 736/* Structures for WPI_{RX,BEACON}_STATISTICS notification. */ 737struct wpi_rx_phy_stats { 738 uint32_t ina; 739 uint32_t fina; 740 uint32_t bad_plcp; 741 uint32_t bad_crc32; 742 uint32_t overrun; 743 uint32_t eoverrun; 744 uint32_t good_crc32; 745 uint32_t fa; 746 uint32_t bad_fina_sync; 747 uint32_t sfd_timeout; 748 uint32_t fina_timeout; 749 uint32_t no_rts_ack; 750 uint32_t rxe_limit; 751 uint32_t ack; 752 uint32_t cts; 753} __packed; 754 755struct wpi_rx_general_stats { 756 uint32_t bad_cts; 757 uint32_t bad_ack; 758 uint32_t not_bss; 759 uint32_t filtered; 760 uint32_t bad_chan; 761} __packed; 762 763struct wpi_rx_stats { 764 struct wpi_rx_phy_stats ofdm; 765 struct wpi_rx_phy_stats cck; 766 struct wpi_rx_general_stats general; 767} __packed; 768 769struct wpi_tx_stats { 770 uint32_t preamble; 771 uint32_t rx_detected; 772 uint32_t bt_defer; 773 uint32_t bt_kill; 774 uint32_t short_len; 775 uint32_t cts_timeout; 776 uint32_t ack_timeout; 777 uint32_t exp_ack; 778 uint32_t ack; 779} __packed; 780 781struct wpi_general_stats { 782 uint32_t temp; 783 uint32_t burst_check; 784 uint32_t burst; 785 uint32_t reserved[4]; 786 uint32_t sleep; 787 uint32_t slot_out; 788 uint32_t slot_idle; 789 uint32_t ttl_tstamp; 790 uint32_t tx_ant_a; 791 uint32_t tx_ant_b; 792 uint32_t exec; 793 uint32_t probe; 794} __packed; 795 796struct wpi_stats { 797 uint32_t flags; 798 struct wpi_rx_stats rx; 799 struct wpi_tx_stats tx; 800 struct wpi_general_stats general; 801} __packed; 802 803/* Possible flags for command WPI_CMD_GET_STATISTICS. */ 804#define WPI_STATISTICS_BEACON_DISABLE (1 << 1) 805 806/* Firmware error dump entry. */ 807struct wpi_fw_dump { 808 uint32_t desc; 809 uint32_t time; 810 uint32_t blink[2]; 811 uint32_t ilink[2]; 812 uint32_t data; 813} __packed; 814 815/* Firmware image file header. */ 816struct wpi_firmware_hdr { 817#define WPI_FW_MINVERSION 2144 818#define WPI_FW_NAME "wpifw" 819 820 uint16_t driver; 821 uint8_t minor; 822 uint8_t major; 823 uint32_t rtextsz; 824 uint32_t rdatasz; 825 uint32_t itextsz; 826 uint32_t idatasz; 827 uint32_t btextsz; 828} __packed; 829 830#define WPI_FW_TEXT_MAXSZ ( 80 * 1024 ) 831#define WPI_FW_DATA_MAXSZ ( 32 * 1024 ) 832#define WPI_FW_BOOT_TEXT_MAXSZ 1024 833 834#define WPI_FW_UPDATED (1U << 31 ) 835 836/* 837 * Offsets into EEPROM. 838 */ 839#define WPI_EEPROM_MAC 0x015 840#define WPI_EEPROM_REVISION 0x035 841#define WPI_EEPROM_SKU_CAP 0x045 842#define WPI_EEPROM_TYPE 0x04a 843#define WPI_EEPROM_DOMAIN 0x060 844#define WPI_EEPROM_BAND1 0x063 845#define WPI_EEPROM_BAND2 0x072 846#define WPI_EEPROM_BAND3 0x080 847#define WPI_EEPROM_BAND4 0x08d 848#define WPI_EEPROM_BAND5 0x099 849#define WPI_EEPROM_POWER_GRP 0x100 850 851struct wpi_eeprom_chan { 852 uint8_t flags; 853#define WPI_EEPROM_CHAN_VALID (1 << 0) 854#define WPI_EEPROM_CHAN_IBSS (1 << 1) 855#define WPI_EEPROM_CHAN_ACTIVE (1 << 3) 856#define WPI_EEPROM_CHAN_RADAR (1 << 4) 857 858 int8_t maxpwr; 859} __packed; 860 861struct wpi_eeprom_sample { 862 uint8_t index; 863 int8_t power; 864 uint16_t volt; 865} __packed; 866 867#define WPI_POWER_GROUPS_COUNT 5 868struct wpi_eeprom_group { 869 struct wpi_eeprom_sample samples[5]; 870 int32_t coef[5]; 871 int32_t corr[5]; 872 int8_t maxpwr; 873 uint8_t chan; 874 int16_t temp; 875} __packed; 876 877#define WPI_CHAN_BANDS_COUNT 5 878#define WPI_MAX_CHAN_PER_BAND 14 879static const struct wpi_chan_band { 880 uint32_t addr; /* offset in EEPROM */ 881 uint8_t nchan; 882 uint8_t chan[WPI_MAX_CHAN_PER_BAND]; 883} wpi_bands[] = { 884 /* 20MHz channels, 2GHz band. */ 885 { WPI_EEPROM_BAND1, 14, 886 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 887 /* 20MHz channels, 5GHz band. */ 888 { WPI_EEPROM_BAND2, 13, 889 { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 890 { WPI_EEPROM_BAND3, 12, 891 { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 892 { WPI_EEPROM_BAND4, 11, 893 { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 894 { WPI_EEPROM_BAND5, 6, 895 { 145, 149, 153, 157, 161, 165 } } 896}; 897 898/* HW rate indices. */ 899#define WPI_RIDX_OFDM6 0 900#define WPI_RIDX_OFDM36 5 901#define WPI_RIDX_OFDM48 6 902#define WPI_RIDX_OFDM54 7 903#define WPI_RIDX_CCK1 8 904#define WPI_RIDX_CCK2 9 905#define WPI_RIDX_CCK11 11 906 907static const uint8_t wpi_ridx_to_plcp[] = { 908 /* OFDM: IEEE Std 802.11a-1999, pp. 14 Table 80 */ 909 /* R1-R4 (ral/ural is R4-R1) */ 910 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, 911 /* CCK: device-dependent */ 912 10, 20, 55, 110 913}; 914 915#define WPI_MAX_PWR_INDEX 77 916 917/* 918 * RF Tx gain values from highest to lowest power (values obtained from 919 * the reference driver.) 920 */ 921static const uint8_t wpi_rf_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 922 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xbb, 0xbb, 0xbb, 923 0xbb, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3, 0xd3, 0xd3, 0xb3, 0xb3, 0xb3, 924 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x73, 0xeb, 0xeb, 0xeb, 925 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xab, 0xab, 0xab, 0x8b, 926 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xc3, 0xc3, 0xc3, 0xc3, 0xa3, 927 0xa3, 0xa3, 0xa3, 0x83, 0x83, 0x83, 0x83, 0x63, 0x63, 0x63, 0x63, 928 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 0x03, 0x03, 0x03, 929 0x03 930}; 931 932static const uint8_t wpi_rf_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 933 0xfb, 0xfb, 0xfb, 0xdb, 0xdb, 0xbb, 0xbb, 0x9b, 0x9b, 0x7b, 0x7b, 934 0x7b, 0x7b, 0x5b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x1b, 0x1b, 935 0x1b, 0x73, 0x73, 0x73, 0x53, 0x53, 0x53, 0x53, 0x53, 0x33, 0x33, 936 0x33, 0x33, 0x13, 0x13, 0x13, 0x13, 0x13, 0xab, 0xab, 0xab, 0x8b, 937 0x8b, 0x8b, 0x8b, 0x6b, 0x6b, 0x6b, 0x6b, 0x4b, 0x4b, 0x4b, 0x4b, 938 0x2b, 0x2b, 0x2b, 0x2b, 0x0b, 0x0b, 0x0b, 0x0b, 0x83, 0x83, 0x63, 939 0x63, 0x63, 0x63, 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 940 0x03 941}; 942 943/* 944 * DSP pre-DAC gain values from highest to lowest power (values obtained 945 * from the reference driver.) 946 */ 947static const uint8_t wpi_dsp_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 948 0x7f, 0x7f, 0x7f, 0x7f, 0x7d, 0x6e, 0x69, 0x62, 0x7d, 0x73, 0x6c, 949 0x63, 0x77, 0x6f, 0x69, 0x61, 0x5c, 0x6a, 0x64, 0x78, 0x71, 0x6b, 950 0x7d, 0x77, 0x70, 0x6a, 0x65, 0x61, 0x5b, 0x6b, 0x79, 0x73, 0x6d, 951 0x7f, 0x79, 0x73, 0x6c, 0x66, 0x60, 0x5c, 0x6e, 0x68, 0x62, 0x74, 952 0x7d, 0x77, 0x71, 0x6b, 0x65, 0x60, 0x71, 0x6a, 0x66, 0x5f, 0x71, 953 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 954 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 955 0x5f 956}; 957 958static const uint8_t wpi_dsp_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 959 0x7f, 0x78, 0x72, 0x77, 0x65, 0x71, 0x66, 0x72, 0x67, 0x75, 0x6b, 960 0x63, 0x5c, 0x6c, 0x7d, 0x76, 0x6d, 0x66, 0x60, 0x5a, 0x68, 0x62, 961 0x5c, 0x76, 0x6f, 0x68, 0x7e, 0x79, 0x71, 0x69, 0x63, 0x76, 0x6f, 962 0x68, 0x62, 0x74, 0x6d, 0x66, 0x62, 0x5d, 0x71, 0x6b, 0x63, 0x78, 963 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 964 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x6b, 0x63, 0x78, 965 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 966 0x78 967}; 968 969/* 970 * Power saving settings (values obtained from the reference driver.) 971 */ 972#define WPI_NDTIMRANGES 2 973#define WPI_NPOWERLEVELS 6 974static const struct wpi_pmgt { 975 uint32_t rxtimeout; 976 uint32_t txtimeout; 977 uint32_t intval[5]; 978 uint8_t skip_dtim; 979} wpi_pmgt[WPI_NDTIMRANGES][WPI_NPOWERLEVELS] = { 980 /* DTIM <= 10 */ 981 { 982 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 983 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 984 { 200, 300, { 2, 4, 6, 7, 7 }, 0 }, /* PS level 2 */ 985 { 50, 100, { 2, 6, 9, 9, 10 }, 0 }, /* PS level 3 */ 986 { 50, 25, { 2, 7, 9, 9, 10 }, 1 }, /* PS level 4 */ 987 { 25, 25, { 4, 7, 10, 10, 10 }, 1 } /* PS level 5 */ 988 }, 989 /* DTIM >= 11 */ 990 { 991 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 992 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 993 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 994 { 50, 100, { 2, 6, 9, 9, -1 }, 0 }, /* PS level 3 */ 995 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 996 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 997 } 998}; 999 1000/* Firmware errors. */ 1001static const char * const wpi_fw_errmsg[] = { 1002 "OK", 1003 "FAIL", 1004 "BAD_PARAM", 1005 "BAD_CHECKSUM", 1006 "NMI_INTERRUPT", 1007 "SYSASSERT", 1008 "FATAL_ERROR" 1009}; 1010 1011#define WPI_READ(sc, reg) \ 1012 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1013 1014#define WPI_WRITE(sc, reg, val) \ 1015 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1016 1017#define WPI_WRITE_REGION_4(sc, offset, datap, count) \ 1018 bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 1019 (datap), (count)) 1020 1021#define WPI_SETBITS(sc, reg, mask) \ 1022 WPI_WRITE(sc, reg, WPI_READ(sc, reg) | (mask)) 1023 1024#define WPI_CLRBITS(sc, reg, mask) \ 1025 WPI_WRITE(sc, reg, WPI_READ(sc, reg) & ~(mask)) 1026 1027#define WPI_BARRIER_WRITE(sc) \ 1028 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1029 BUS_SPACE_BARRIER_WRITE) 1030 1031#define WPI_BARRIER_READ_WRITE(sc) \ 1032 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1033 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1034