1/* $FreeBSD$ */ 2/*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 6 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 7 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 8 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32/* 33 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 34 * 35 * The EHCI 0.96 spec can be found at 36 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 37 * The EHCI 1.0 spec can be found at 38 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/usb_20.zip 41 * 42 */ 43 44/* 45 * TODO: 46 * 1) command failures are not recovered correctly 47 */ 48 49#ifdef USB_GLOBAL_INCLUDE_FILE 50#include USB_GLOBAL_INCLUDE_FILE 51#else 52#include <sys/stdint.h> 53#include <sys/stddef.h> 54#include <sys/param.h> 55#include <sys/queue.h> 56#include <sys/types.h> 57#include <sys/systm.h> 58#include <sys/kernel.h> 59#include <sys/bus.h> 60#include <sys/module.h> 61#include <sys/lock.h> 62#include <sys/mutex.h> 63#include <sys/condvar.h> 64#include <sys/sysctl.h> 65#include <sys/sx.h> 66#include <sys/unistd.h> 67#include <sys/callout.h> 68#include <sys/malloc.h> 69#include <sys/priv.h> 70 71#include <dev/usb/usb.h> 72#include <dev/usb/usbdi.h> 73 74#define USB_DEBUG_VAR ehcidebug 75 76#include <dev/usb/usb_core.h> 77#include <dev/usb/usb_debug.h> 78#include <dev/usb/usb_busdma.h> 79#include <dev/usb/usb_process.h> 80#include <dev/usb/usb_transfer.h> 81#include <dev/usb/usb_device.h> 82#include <dev/usb/usb_hub.h> 83#include <dev/usb/usb_util.h> 84 85#include <dev/usb/usb_controller.h> 86#include <dev/usb/usb_bus.h> 87#endif /* USB_GLOBAL_INCLUDE_FILE */ 88 89#include <dev/usb/controller/ehci.h> 90#include <dev/usb/controller/ehcireg.h> 91 92#define EHCI_BUS2SC(bus) \ 93 ((ehci_softc_t *)(((uint8_t *)(bus)) - \ 94 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus)))) 95 96#ifdef USB_DEBUG 97static int ehcidebug = 0; 98static int ehcinohighspeed = 0; 99static int ehciiaadbug = 0; 100static int ehcilostintrbug = 0; 101 102static SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 103SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RWTUN, 104 &ehcidebug, 0, "Debug level"); 105SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RWTUN, 106 &ehcinohighspeed, 0, "Disable High Speed USB"); 107SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RWTUN, 108 &ehciiaadbug, 0, "Enable doorbell bug workaround"); 109SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RWTUN, 110 &ehcilostintrbug, 0, "Enable lost interrupt bug workaround"); 111 112static void ehci_dump_regs(ehci_softc_t *sc); 113static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh); 114 115#endif 116 117#define EHCI_INTR_ENDPT 1 118 119static const struct usb_bus_methods ehci_bus_methods; 120static const struct usb_pipe_methods ehci_device_bulk_methods; 121static const struct usb_pipe_methods ehci_device_ctrl_methods; 122static const struct usb_pipe_methods ehci_device_intr_methods; 123static const struct usb_pipe_methods ehci_device_isoc_fs_methods; 124static const struct usb_pipe_methods ehci_device_isoc_hs_methods; 125 126static void ehci_do_poll(struct usb_bus *); 127static void ehci_device_done(struct usb_xfer *, usb_error_t); 128static uint8_t ehci_check_transfer(struct usb_xfer *); 129static void ehci_timeout(void *); 130static void ehci_poll_timeout(void *); 131 132static void ehci_root_intr(ehci_softc_t *sc); 133 134struct ehci_std_temp { 135 ehci_softc_t *sc; 136 struct usb_page_cache *pc; 137 ehci_qtd_t *td; 138 ehci_qtd_t *td_next; 139 uint32_t average; 140 uint32_t qtd_status; 141 uint32_t len; 142 uint16_t max_frame_size; 143 uint8_t shortpkt; 144 uint8_t auto_data_toggle; 145 uint8_t setup_alt_next; 146 uint8_t last_frame; 147}; 148 149void 150ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 151{ 152 ehci_softc_t *sc = EHCI_BUS2SC(bus); 153 uint32_t i; 154 155 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 156 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 157 158 cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg, 159 sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN); 160 161 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 162 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 163 164 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 165 cb(bus, sc->sc_hw.intr_start_pc + i, 166 sc->sc_hw.intr_start_pg + i, 167 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 168 } 169 170 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 171 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 172 sc->sc_hw.isoc_hs_start_pg + i, 173 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 174 } 175 176 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 177 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 178 sc->sc_hw.isoc_fs_start_pg + i, 179 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 180 } 181} 182 183usb_error_t 184ehci_reset(ehci_softc_t *sc) 185{ 186 uint32_t hcr; 187 int i; 188 189 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 190 for (i = 0; i < 100; i++) { 191 usb_pause_mtx(NULL, hz / 128); 192 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 193 if (!hcr) { 194 if (sc->sc_vendor_post_reset != NULL) 195 sc->sc_vendor_post_reset(sc); 196 return (0); 197 } 198 } 199 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 200 return (USB_ERR_IOERROR); 201} 202 203static usb_error_t 204ehci_hcreset(ehci_softc_t *sc) 205{ 206 uint32_t hcr; 207 int i; 208 209 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 210 for (i = 0; i < 100; i++) { 211 usb_pause_mtx(NULL, hz / 128); 212 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 213 if (hcr) 214 break; 215 } 216 if (!hcr) 217 /* 218 * Fall through and try reset anyway even though 219 * Table 2-9 in the EHCI spec says this will result 220 * in undefined behavior. 221 */ 222 device_printf(sc->sc_bus.bdev, "stop timeout\n"); 223 224 return (ehci_reset(sc)); 225} 226 227static int 228ehci_init_sub(struct ehci_softc *sc) 229{ 230 struct usb_page_search buf_res; 231 uint32_t cparams; 232 uint32_t hcr; 233 uint8_t i; 234 235 cparams = EREAD4(sc, EHCI_HCCPARAMS); 236 237 DPRINTF("cparams=0x%x\n", cparams); 238 239 if (EHCI_HCC_64BIT(cparams)) { 240 DPRINTF("HCC uses 64-bit structures\n"); 241 242 /* MUST clear segment register if 64 bit capable */ 243 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 244 } 245 246 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 247 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 248 249 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 250 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 251 252 /* enable interrupts */ 253 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 254 255 /* turn on controller */ 256 EOWRITE4(sc, EHCI_USBCMD, 257 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 258 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 259 EHCI_CMD_ASE | 260 EHCI_CMD_PSE | 261 EHCI_CMD_RS); 262 263 /* Take over port ownership */ 264 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 265 266 for (i = 0; i < 100; i++) { 267 usb_pause_mtx(NULL, hz / 128); 268 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 269 if (!hcr) { 270 break; 271 } 272 } 273 if (hcr) { 274 device_printf(sc->sc_bus.bdev, "run timeout\n"); 275 return (USB_ERR_IOERROR); 276 } 277 return (USB_ERR_NORMAL_COMPLETION); 278} 279 280usb_error_t 281ehci_init(ehci_softc_t *sc) 282{ 283 struct usb_page_search buf_res; 284 uint32_t version; 285 uint32_t sparams; 286 uint16_t i; 287 uint16_t x; 288 uint16_t y; 289 uint16_t bit; 290 usb_error_t err = 0; 291 292 DPRINTF("start\n"); 293 294 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0); 295 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0); 296 297 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 298 299#ifdef USB_DEBUG 300 if (ehciiaadbug) 301 sc->sc_flags |= EHCI_SCFLG_IAADBUG; 302 if (ehcilostintrbug) 303 sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG; 304 if (ehcidebug > 2) { 305 ehci_dump_regs(sc); 306 } 307#endif 308 309 version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 310 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 311 version >> 8, version & 0xff); 312 313 sparams = EREAD4(sc, EHCI_HCSPARAMS); 314 DPRINTF("sparams=0x%x\n", sparams); 315 316 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 317 sc->sc_bus.usbrev = USB_REV_2_0; 318 319 if (!(sc->sc_flags & EHCI_SCFLG_DONTRESET)) { 320 /* Reset the controller */ 321 DPRINTF("%s: resetting\n", 322 device_get_nameunit(sc->sc_bus.bdev)); 323 324 err = ehci_hcreset(sc); 325 if (err) { 326 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 327 return (err); 328 } 329 } 330 331 /* 332 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 333 * bytes 2: 256*4 bytes 3: unknown 334 */ 335 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 336 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 337 return (USB_ERR_IOERROR); 338 } 339 /* set up the bus struct */ 340 sc->sc_bus.methods = &ehci_bus_methods; 341 342 sc->sc_eintrs = EHCI_NORMAL_INTRS; 343 344 if (1) { 345 struct ehci_qh_sub *qh; 346 347 usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res); 348 349 qh = buf_res.buffer; 350 351 sc->sc_terminate_self = htohc32(sc, buf_res.physaddr); 352 353 /* init terminate TD */ 354 qh->qtd_next = 355 htohc32(sc, EHCI_LINK_TERMINATE); 356 qh->qtd_altnext = 357 htohc32(sc, EHCI_LINK_TERMINATE); 358 qh->qtd_status = 359 htohc32(sc, EHCI_QTD_HALTED); 360 } 361 362 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 363 ehci_qh_t *qh; 364 365 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 366 367 qh = buf_res.buffer; 368 369 /* initialize page cache pointer */ 370 371 qh->page_cache = sc->sc_hw.intr_start_pc + i; 372 373 /* store a pointer to queue head */ 374 375 sc->sc_intr_p_last[i] = qh; 376 377 qh->qh_self = 378 htohc32(sc, buf_res.physaddr) | 379 htohc32(sc, EHCI_LINK_QH); 380 381 qh->qh_endp = 382 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 383 qh->qh_endphub = 384 htohc32(sc, EHCI_QH_SET_MULT(1)); 385 qh->qh_curqtd = 0; 386 387 qh->qh_qtd.qtd_next = 388 htohc32(sc, EHCI_LINK_TERMINATE); 389 qh->qh_qtd.qtd_altnext = 390 htohc32(sc, EHCI_LINK_TERMINATE); 391 qh->qh_qtd.qtd_status = 392 htohc32(sc, EHCI_QTD_HALTED); 393 } 394 395 /* 396 * the QHs are arranged to give poll intervals that are 397 * powers of 2 times 1ms 398 */ 399 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 400 while (bit) { 401 x = bit; 402 while (x & bit) { 403 ehci_qh_t *qh_x; 404 ehci_qh_t *qh_y; 405 406 y = (x ^ bit) | (bit / 2); 407 408 qh_x = sc->sc_intr_p_last[x]; 409 qh_y = sc->sc_intr_p_last[y]; 410 411 /* 412 * the next QH has half the poll interval 413 */ 414 qh_x->qh_link = qh_y->qh_self; 415 416 x++; 417 } 418 bit >>= 1; 419 } 420 421 if (1) { 422 ehci_qh_t *qh; 423 424 qh = sc->sc_intr_p_last[0]; 425 426 /* the last (1ms) QH terminates */ 427 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE); 428 } 429 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 430 ehci_sitd_t *sitd; 431 ehci_itd_t *itd; 432 433 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 434 435 sitd = buf_res.buffer; 436 437 /* initialize page cache pointer */ 438 439 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 440 441 /* store a pointer to the transfer descriptor */ 442 443 sc->sc_isoc_fs_p_last[i] = sitd; 444 445 /* initialize full speed isochronous */ 446 447 sitd->sitd_self = 448 htohc32(sc, buf_res.physaddr) | 449 htohc32(sc, EHCI_LINK_SITD); 450 451 sitd->sitd_back = 452 htohc32(sc, EHCI_LINK_TERMINATE); 453 454 sitd->sitd_next = 455 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 456 457 458 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 459 460 itd = buf_res.buffer; 461 462 /* initialize page cache pointer */ 463 464 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 465 466 /* store a pointer to the transfer descriptor */ 467 468 sc->sc_isoc_hs_p_last[i] = itd; 469 470 /* initialize high speed isochronous */ 471 472 itd->itd_self = 473 htohc32(sc, buf_res.physaddr) | 474 htohc32(sc, EHCI_LINK_ITD); 475 476 itd->itd_next = 477 sitd->sitd_self; 478 } 479 480 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 481 482 if (1) { 483 uint32_t *pframes; 484 485 pframes = buf_res.buffer; 486 487 /* 488 * execution order: 489 * pframes -> high speed isochronous -> 490 * full speed isochronous -> interrupt QH's 491 */ 492 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 493 pframes[i] = sc->sc_isoc_hs_p_last 494 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 495 } 496 } 497 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 498 499 if (1) { 500 501 ehci_qh_t *qh; 502 503 qh = buf_res.buffer; 504 505 /* initialize page cache pointer */ 506 507 qh->page_cache = &sc->sc_hw.async_start_pc; 508 509 /* store a pointer to the queue head */ 510 511 sc->sc_async_p_last = qh; 512 513 /* init dummy QH that starts the async list */ 514 515 qh->qh_self = 516 htohc32(sc, buf_res.physaddr) | 517 htohc32(sc, EHCI_LINK_QH); 518 519 /* fill the QH */ 520 qh->qh_endp = 521 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 522 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1)); 523 qh->qh_link = qh->qh_self; 524 qh->qh_curqtd = 0; 525 526 /* fill the overlay qTD */ 527 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE); 528 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE); 529 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED); 530 } 531 /* flush all cache into memory */ 532 533 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 534 535#ifdef USB_DEBUG 536 if (ehcidebug) { 537 ehci_dump_sqh(sc, sc->sc_async_p_last); 538 } 539#endif 540 541 /* finial setup */ 542 err = ehci_init_sub(sc); 543 544 if (!err) { 545 /* catch any lost interrupts */ 546 ehci_do_poll(&sc->sc_bus); 547 } 548 return (err); 549} 550 551/* 552 * shut down the controller when the system is going down 553 */ 554void 555ehci_detach(ehci_softc_t *sc) 556{ 557 USB_BUS_LOCK(&sc->sc_bus); 558 559 usb_callout_stop(&sc->sc_tmo_pcd); 560 usb_callout_stop(&sc->sc_tmo_poll); 561 562 EOWRITE4(sc, EHCI_USBINTR, 0); 563 USB_BUS_UNLOCK(&sc->sc_bus); 564 565 if (ehci_hcreset(sc)) { 566 DPRINTF("reset failed!\n"); 567 } 568 569 /* XXX let stray task complete */ 570 usb_pause_mtx(NULL, hz / 20); 571 572 usb_callout_drain(&sc->sc_tmo_pcd); 573 usb_callout_drain(&sc->sc_tmo_poll); 574} 575 576static void 577ehci_suspend(ehci_softc_t *sc) 578{ 579 DPRINTF("stopping the HC\n"); 580 581 /* reset HC */ 582 ehci_hcreset(sc); 583} 584 585static void 586ehci_resume(ehci_softc_t *sc) 587{ 588 /* reset HC */ 589 ehci_hcreset(sc); 590 591 /* setup HC */ 592 ehci_init_sub(sc); 593 594 /* catch any lost interrupts */ 595 ehci_do_poll(&sc->sc_bus); 596} 597 598#ifdef USB_DEBUG 599static void 600ehci_dump_regs(ehci_softc_t *sc) 601{ 602 uint32_t i; 603 604 i = EOREAD4(sc, EHCI_USBCMD); 605 printf("cmd=0x%08x\n", i); 606 607 if (i & EHCI_CMD_ITC_1) 608 printf(" EHCI_CMD_ITC_1\n"); 609 if (i & EHCI_CMD_ITC_2) 610 printf(" EHCI_CMD_ITC_2\n"); 611 if (i & EHCI_CMD_ITC_4) 612 printf(" EHCI_CMD_ITC_4\n"); 613 if (i & EHCI_CMD_ITC_8) 614 printf(" EHCI_CMD_ITC_8\n"); 615 if (i & EHCI_CMD_ITC_16) 616 printf(" EHCI_CMD_ITC_16\n"); 617 if (i & EHCI_CMD_ITC_32) 618 printf(" EHCI_CMD_ITC_32\n"); 619 if (i & EHCI_CMD_ITC_64) 620 printf(" EHCI_CMD_ITC_64\n"); 621 if (i & EHCI_CMD_ASPME) 622 printf(" EHCI_CMD_ASPME\n"); 623 if (i & EHCI_CMD_ASPMC) 624 printf(" EHCI_CMD_ASPMC\n"); 625 if (i & EHCI_CMD_LHCR) 626 printf(" EHCI_CMD_LHCR\n"); 627 if (i & EHCI_CMD_IAAD) 628 printf(" EHCI_CMD_IAAD\n"); 629 if (i & EHCI_CMD_ASE) 630 printf(" EHCI_CMD_ASE\n"); 631 if (i & EHCI_CMD_PSE) 632 printf(" EHCI_CMD_PSE\n"); 633 if (i & EHCI_CMD_FLS_M) 634 printf(" EHCI_CMD_FLS_M\n"); 635 if (i & EHCI_CMD_HCRESET) 636 printf(" EHCI_CMD_HCRESET\n"); 637 if (i & EHCI_CMD_RS) 638 printf(" EHCI_CMD_RS\n"); 639 640 i = EOREAD4(sc, EHCI_USBSTS); 641 642 printf("sts=0x%08x\n", i); 643 644 if (i & EHCI_STS_ASS) 645 printf(" EHCI_STS_ASS\n"); 646 if (i & EHCI_STS_PSS) 647 printf(" EHCI_STS_PSS\n"); 648 if (i & EHCI_STS_REC) 649 printf(" EHCI_STS_REC\n"); 650 if (i & EHCI_STS_HCH) 651 printf(" EHCI_STS_HCH\n"); 652 if (i & EHCI_STS_IAA) 653 printf(" EHCI_STS_IAA\n"); 654 if (i & EHCI_STS_HSE) 655 printf(" EHCI_STS_HSE\n"); 656 if (i & EHCI_STS_FLR) 657 printf(" EHCI_STS_FLR\n"); 658 if (i & EHCI_STS_PCD) 659 printf(" EHCI_STS_PCD\n"); 660 if (i & EHCI_STS_ERRINT) 661 printf(" EHCI_STS_ERRINT\n"); 662 if (i & EHCI_STS_INT) 663 printf(" EHCI_STS_INT\n"); 664 665 printf("ien=0x%08x\n", 666 EOREAD4(sc, EHCI_USBINTR)); 667 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 668 EOREAD4(sc, EHCI_FRINDEX), 669 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 670 EOREAD4(sc, EHCI_PERIODICLISTBASE), 671 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 672 for (i = 1; i <= sc->sc_noport; i++) { 673 printf("port %d status=0x%08x\n", i, 674 EOREAD4(sc, EHCI_PORTSC(i))); 675 } 676} 677 678static void 679ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type) 680{ 681 link = hc32toh(sc, link); 682 printf("0x%08x", link); 683 if (link & EHCI_LINK_TERMINATE) 684 printf("<T>"); 685 else { 686 printf("<"); 687 if (type) { 688 switch (EHCI_LINK_TYPE(link)) { 689 case EHCI_LINK_ITD: 690 printf("ITD"); 691 break; 692 case EHCI_LINK_QH: 693 printf("QH"); 694 break; 695 case EHCI_LINK_SITD: 696 printf("SITD"); 697 break; 698 case EHCI_LINK_FSTN: 699 printf("FSTN"); 700 break; 701 } 702 } 703 printf(">"); 704 } 705} 706 707static void 708ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd) 709{ 710 uint32_t s; 711 712 printf(" next="); 713 ehci_dump_link(sc, qtd->qtd_next, 0); 714 printf(" altnext="); 715 ehci_dump_link(sc, qtd->qtd_altnext, 0); 716 printf("\n"); 717 s = hc32toh(sc, qtd->qtd_status); 718 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 719 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 720 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 721 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 722 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 723 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 724 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 725 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 726 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 727 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 728 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 729 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 730 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 731 732 for (s = 0; s < 5; s++) { 733 printf(" buffer[%d]=0x%08x\n", s, 734 hc32toh(sc, qtd->qtd_buffer[s])); 735 } 736 for (s = 0; s < 5; s++) { 737 printf(" buffer_hi[%d]=0x%08x\n", s, 738 hc32toh(sc, qtd->qtd_buffer_hi[s])); 739 } 740} 741 742static uint8_t 743ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd) 744{ 745 uint8_t temp; 746 747 usb_pc_cpu_invalidate(sqtd->page_cache); 748 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self)); 749 ehci_dump_qtd(sc, sqtd); 750 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0; 751 return (temp); 752} 753 754static void 755ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd) 756{ 757 uint16_t i; 758 uint8_t stop; 759 760 stop = 0; 761 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 762 stop = ehci_dump_sqtd(sc, sqtd); 763 } 764 if (sqtd) { 765 printf("dump aborted, too many TDs\n"); 766 } 767} 768 769static void 770ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh) 771{ 772 uint32_t endp; 773 uint32_t endphub; 774 775 usb_pc_cpu_invalidate(qh->page_cache); 776 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F); 777 printf(" link="); 778 ehci_dump_link(sc, qh->qh_link, 1); 779 printf("\n"); 780 endp = hc32toh(sc, qh->qh_endp); 781 printf(" endp=0x%08x\n", endp); 782 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 783 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 784 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 785 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 786 printf(" mpl=0x%x ctl=%d nrl=%d\n", 787 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 788 EHCI_QH_GET_NRL(endp)); 789 endphub = hc32toh(sc, qh->qh_endphub); 790 printf(" endphub=0x%08x\n", endphub); 791 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 792 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 793 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 794 EHCI_QH_GET_MULT(endphub)); 795 printf(" curqtd="); 796 ehci_dump_link(sc, qh->qh_curqtd, 0); 797 printf("\n"); 798 printf("Overlay qTD:\n"); 799 ehci_dump_qtd(sc, (void *)&qh->qh_qtd); 800} 801 802static void 803ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd) 804{ 805 usb_pc_cpu_invalidate(sitd->page_cache); 806 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F); 807 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next)); 808 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 809 hc32toh(sc, sitd->sitd_portaddr), 810 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN)) 811 ? "in" : "out", 812 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)), 813 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)), 814 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)), 815 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr))); 816 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask)); 817 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status), 818 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 819 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status))); 820 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 821 hc32toh(sc, sitd->sitd_back), 822 hc32toh(sc, sitd->sitd_bp[0]), 823 hc32toh(sc, sitd->sitd_bp[1]), 824 hc32toh(sc, sitd->sitd_bp_hi[0]), 825 hc32toh(sc, sitd->sitd_bp_hi[1])); 826} 827 828static void 829ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd) 830{ 831 usb_pc_cpu_invalidate(itd->page_cache); 832 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F); 833 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next)); 834 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]), 835 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 836 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]), 837 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 838 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]), 839 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 840 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]), 841 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 842 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]), 843 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 844 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]), 845 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 846 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]), 847 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 848 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]), 849 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 850 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0])); 851 printf(" addr=0x%02x; endpt=0x%01x\n", 852 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])), 853 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0]))); 854 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1])); 855 printf(" dir=%s; mpl=0x%02x\n", 856 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 857 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1]))); 858 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 859 hc32toh(sc, itd->itd_bp[2]), 860 hc32toh(sc, itd->itd_bp[3]), 861 hc32toh(sc, itd->itd_bp[4]), 862 hc32toh(sc, itd->itd_bp[5]), 863 hc32toh(sc, itd->itd_bp[6])); 864 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 865 " 0x%08x,0x%08x,0x%08x\n", 866 hc32toh(sc, itd->itd_bp_hi[0]), 867 hc32toh(sc, itd->itd_bp_hi[1]), 868 hc32toh(sc, itd->itd_bp_hi[2]), 869 hc32toh(sc, itd->itd_bp_hi[3]), 870 hc32toh(sc, itd->itd_bp_hi[4]), 871 hc32toh(sc, itd->itd_bp_hi[5]), 872 hc32toh(sc, itd->itd_bp_hi[6])); 873} 874 875static void 876ehci_dump_isoc(ehci_softc_t *sc) 877{ 878 ehci_itd_t *itd; 879 ehci_sitd_t *sitd; 880 uint16_t max = 1000; 881 uint16_t pos; 882 883 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 884 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 885 886 printf("%s: isochronous dump from frame 0x%03x:\n", 887 __FUNCTION__, pos); 888 889 itd = sc->sc_isoc_hs_p_last[pos]; 890 sitd = sc->sc_isoc_fs_p_last[pos]; 891 892 while (itd && max && max--) { 893 ehci_dump_itd(sc, itd); 894 itd = itd->prev; 895 } 896 897 while (sitd && max && max--) { 898 ehci_dump_sitd(sc, sitd); 899 sitd = sitd->prev; 900 } 901} 902 903#endif 904 905static void 906ehci_transfer_intr_enqueue(struct usb_xfer *xfer) 907{ 908 /* check for early completion */ 909 if (ehci_check_transfer(xfer)) { 910 return; 911 } 912 /* put transfer on interrupt queue */ 913 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 914 915 /* start timeout, if any */ 916 if (xfer->timeout != 0) { 917 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 918 } 919} 920 921#define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last) 922static ehci_sitd_t * 923_ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 924{ 925 DPRINTFN(11, "%p to %p\n", std, last); 926 927 /* (sc->sc_bus.mtx) must be locked */ 928 929 std->next = last->next; 930 std->sitd_next = last->sitd_next; 931 932 std->prev = last; 933 934 usb_pc_cpu_flush(std->page_cache); 935 936 /* 937 * the last->next->prev is never followed: std->next->prev = std; 938 */ 939 last->next = std; 940 last->sitd_next = std->sitd_self; 941 942 usb_pc_cpu_flush(last->page_cache); 943 944 return (std); 945} 946 947#define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last) 948static ehci_itd_t * 949_ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) 950{ 951 DPRINTFN(11, "%p to %p\n", std, last); 952 953 /* (sc->sc_bus.mtx) must be locked */ 954 955 std->next = last->next; 956 std->itd_next = last->itd_next; 957 958 std->prev = last; 959 960 usb_pc_cpu_flush(std->page_cache); 961 962 /* 963 * the last->next->prev is never followed: std->next->prev = std; 964 */ 965 last->next = std; 966 last->itd_next = std->itd_self; 967 968 usb_pc_cpu_flush(last->page_cache); 969 970 return (std); 971} 972 973#define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last) 974static ehci_qh_t * 975_ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 976{ 977 DPRINTFN(11, "%p to %p\n", sqh, last); 978 979 if (sqh->prev != NULL) { 980 /* should not happen */ 981 DPRINTFN(0, "QH already linked!\n"); 982 return (last); 983 } 984 /* (sc->sc_bus.mtx) must be locked */ 985 986 sqh->next = last->next; 987 sqh->qh_link = last->qh_link; 988 989 sqh->prev = last; 990 991 usb_pc_cpu_flush(sqh->page_cache); 992 993 /* 994 * the last->next->prev is never followed: sqh->next->prev = sqh; 995 */ 996 997 last->next = sqh; 998 last->qh_link = sqh->qh_self; 999 1000 usb_pc_cpu_flush(last->page_cache); 1001 1002 return (sqh); 1003} 1004 1005#define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last) 1006static ehci_sitd_t * 1007_ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1008{ 1009 DPRINTFN(11, "%p from %p\n", std, last); 1010 1011 /* (sc->sc_bus.mtx) must be locked */ 1012 1013 std->prev->next = std->next; 1014 std->prev->sitd_next = std->sitd_next; 1015 1016 usb_pc_cpu_flush(std->prev->page_cache); 1017 1018 if (std->next) { 1019 std->next->prev = std->prev; 1020 usb_pc_cpu_flush(std->next->page_cache); 1021 } 1022 return ((last == std) ? std->prev : last); 1023} 1024 1025#define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last) 1026static ehci_itd_t * 1027_ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1028{ 1029 DPRINTFN(11, "%p from %p\n", std, last); 1030 1031 /* (sc->sc_bus.mtx) must be locked */ 1032 1033 std->prev->next = std->next; 1034 std->prev->itd_next = std->itd_next; 1035 1036 usb_pc_cpu_flush(std->prev->page_cache); 1037 1038 if (std->next) { 1039 std->next->prev = std->prev; 1040 usb_pc_cpu_flush(std->next->page_cache); 1041 } 1042 return ((last == std) ? std->prev : last); 1043} 1044 1045#define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last) 1046static ehci_qh_t * 1047_ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1048{ 1049 DPRINTFN(11, "%p from %p\n", sqh, last); 1050 1051 /* (sc->sc_bus.mtx) must be locked */ 1052 1053 /* only remove if not removed from a queue */ 1054 if (sqh->prev) { 1055 1056 sqh->prev->next = sqh->next; 1057 sqh->prev->qh_link = sqh->qh_link; 1058 1059 usb_pc_cpu_flush(sqh->prev->page_cache); 1060 1061 if (sqh->next) { 1062 sqh->next->prev = sqh->prev; 1063 usb_pc_cpu_flush(sqh->next->page_cache); 1064 } 1065 last = ((last == sqh) ? sqh->prev : last); 1066 1067 sqh->prev = 0; 1068 1069 usb_pc_cpu_flush(sqh->page_cache); 1070 } 1071 return (last); 1072} 1073 1074static void 1075ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen) 1076{ 1077 uint16_t rem; 1078 uint8_t dt; 1079 1080 /* count number of full packets */ 1081 dt = (actlen / xfer->max_packet_size) & 1; 1082 1083 /* compute remainder */ 1084 rem = actlen % xfer->max_packet_size; 1085 1086 if (rem > 0) 1087 dt ^= 1; /* short packet at the end */ 1088 else if (actlen != xlen) 1089 dt ^= 1; /* zero length packet at the end */ 1090 else if (xlen == 0) 1091 dt ^= 1; /* zero length transfer */ 1092 1093 xfer->endpoint->toggle_next ^= dt; 1094} 1095 1096static usb_error_t 1097ehci_non_isoc_done_sub(struct usb_xfer *xfer) 1098{ 1099 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1100 ehci_qtd_t *td; 1101 ehci_qtd_t *td_alt_next; 1102 uint32_t status; 1103 uint16_t len; 1104 1105 td = xfer->td_transfer_cache; 1106 td_alt_next = td->alt_next; 1107 1108 if (xfer->aframes != xfer->nframes) { 1109 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1110 } 1111 while (1) { 1112 1113 usb_pc_cpu_invalidate(td->page_cache); 1114 status = hc32toh(sc, td->qtd_status); 1115 1116 len = EHCI_QTD_GET_BYTES(status); 1117 1118 /* 1119 * Verify the status length and 1120 * add the length to "frlengths[]": 1121 */ 1122 if (len > td->len) { 1123 /* should not happen */ 1124 DPRINTF("Invalid status length, " 1125 "0x%04x/0x%04x bytes\n", len, td->len); 1126 status |= EHCI_QTD_HALTED; 1127 } else if (xfer->aframes != xfer->nframes) { 1128 xfer->frlengths[xfer->aframes] += td->len - len; 1129 /* manually update data toggle */ 1130 ehci_data_toggle_update(xfer, td->len - len, td->len); 1131 } 1132 1133 /* Check for last transfer */ 1134 if (((void *)td) == xfer->td_transfer_last) { 1135 td = NULL; 1136 break; 1137 } 1138 /* Check for transfer error */ 1139 if (status & EHCI_QTD_HALTED) { 1140 /* the transfer is finished */ 1141 td = NULL; 1142 break; 1143 } 1144 /* Check for short transfer */ 1145 if (len > 0) { 1146 if (xfer->flags_int.short_frames_ok) { 1147 /* follow alt next */ 1148 td = td->alt_next; 1149 } else { 1150 /* the transfer is finished */ 1151 td = NULL; 1152 } 1153 break; 1154 } 1155 td = td->obj_next; 1156 1157 if (td->alt_next != td_alt_next) { 1158 /* this USB frame is complete */ 1159 break; 1160 } 1161 } 1162 1163 /* update transfer cache */ 1164 1165 xfer->td_transfer_cache = td; 1166 1167#ifdef USB_DEBUG 1168 if (status & EHCI_QTD_STATERRS) { 1169 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1170 "status=%s%s%s%s%s%s%s%s\n", 1171 xfer->address, xfer->endpointno, xfer->aframes, 1172 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1173 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1174 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1175 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1176 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1177 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1178 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1179 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1180 } 1181#endif 1182 if (status & EHCI_QTD_HALTED) { 1183 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1184 (xfer->xroot->udev->address != 0)) { 1185 /* try to separate I/O errors from STALL */ 1186 if (EHCI_QTD_GET_CERR(status) == 0) 1187 return (USB_ERR_IOERROR); 1188 } 1189 return (USB_ERR_STALLED); 1190 } 1191 return (USB_ERR_NORMAL_COMPLETION); 1192} 1193 1194static void 1195ehci_non_isoc_done(struct usb_xfer *xfer) 1196{ 1197 ehci_qh_t *qh; 1198 usb_error_t err = 0; 1199 1200 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1201 xfer, xfer->endpoint); 1202 1203#ifdef USB_DEBUG 1204 if (ehcidebug > 10) { 1205 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1206 1207 ehci_dump_sqtds(sc, xfer->td_transfer_first); 1208 } 1209#endif 1210 1211 /* extract data toggle directly from the QH's overlay area */ 1212 1213 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1214 1215 usb_pc_cpu_invalidate(qh->page_cache); 1216 1217 /* reset scanner */ 1218 1219 xfer->td_transfer_cache = xfer->td_transfer_first; 1220 1221 if (xfer->flags_int.control_xfr) { 1222 1223 if (xfer->flags_int.control_hdr) { 1224 1225 err = ehci_non_isoc_done_sub(xfer); 1226 } 1227 xfer->aframes = 1; 1228 1229 if (xfer->td_transfer_cache == NULL) { 1230 goto done; 1231 } 1232 } 1233 while (xfer->aframes != xfer->nframes) { 1234 1235 err = ehci_non_isoc_done_sub(xfer); 1236 xfer->aframes++; 1237 1238 if (xfer->td_transfer_cache == NULL) { 1239 goto done; 1240 } 1241 } 1242 1243 if (xfer->flags_int.control_xfr && 1244 !xfer->flags_int.control_act) { 1245 1246 err = ehci_non_isoc_done_sub(xfer); 1247 } 1248done: 1249 ehci_device_done(xfer, err); 1250} 1251 1252/*------------------------------------------------------------------------* 1253 * ehci_check_transfer 1254 * 1255 * Return values: 1256 * 0: USB transfer is not finished 1257 * Else: USB transfer is finished 1258 *------------------------------------------------------------------------*/ 1259static uint8_t 1260ehci_check_transfer(struct usb_xfer *xfer) 1261{ 1262 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 1263 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1264 1265 uint32_t status; 1266 1267 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1268 1269 if (methods == &ehci_device_isoc_fs_methods) { 1270 ehci_sitd_t *td; 1271 1272 /* isochronous full speed transfer */ 1273 1274 td = xfer->td_transfer_last; 1275 usb_pc_cpu_invalidate(td->page_cache); 1276 status = hc32toh(sc, td->sitd_status); 1277 1278 /* also check if first is complete */ 1279 1280 td = xfer->td_transfer_first; 1281 usb_pc_cpu_invalidate(td->page_cache); 1282 status |= hc32toh(sc, td->sitd_status); 1283 1284 if (!(status & EHCI_SITD_ACTIVE)) { 1285 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1286 goto transferred; 1287 } 1288 } else if (methods == &ehci_device_isoc_hs_methods) { 1289 ehci_itd_t *td; 1290 1291 /* isochronous high speed transfer */ 1292 1293 /* check last transfer */ 1294 td = xfer->td_transfer_last; 1295 usb_pc_cpu_invalidate(td->page_cache); 1296 status = td->itd_status[0]; 1297 status |= td->itd_status[1]; 1298 status |= td->itd_status[2]; 1299 status |= td->itd_status[3]; 1300 status |= td->itd_status[4]; 1301 status |= td->itd_status[5]; 1302 status |= td->itd_status[6]; 1303 status |= td->itd_status[7]; 1304 1305 /* also check first transfer */ 1306 td = xfer->td_transfer_first; 1307 usb_pc_cpu_invalidate(td->page_cache); 1308 status |= td->itd_status[0]; 1309 status |= td->itd_status[1]; 1310 status |= td->itd_status[2]; 1311 status |= td->itd_status[3]; 1312 status |= td->itd_status[4]; 1313 status |= td->itd_status[5]; 1314 status |= td->itd_status[6]; 1315 status |= td->itd_status[7]; 1316 1317 /* if no transactions are active we continue */ 1318 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) { 1319 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1320 goto transferred; 1321 } 1322 } else { 1323 ehci_qtd_t *td; 1324 ehci_qh_t *qh; 1325 1326 /* non-isochronous transfer */ 1327 1328 /* 1329 * check whether there is an error somewhere in the middle, 1330 * or whether there was a short packet (SPD and not ACTIVE) 1331 */ 1332 td = xfer->td_transfer_cache; 1333 1334 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1335 1336 usb_pc_cpu_invalidate(qh->page_cache); 1337 1338 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1339 if (status & EHCI_QTD_ACTIVE) { 1340 /* transfer is pending */ 1341 goto done; 1342 } 1343 1344 while (1) { 1345 usb_pc_cpu_invalidate(td->page_cache); 1346 status = hc32toh(sc, td->qtd_status); 1347 1348 /* 1349 * Check if there is an active TD which 1350 * indicates that the transfer isn't done. 1351 */ 1352 if (status & EHCI_QTD_ACTIVE) { 1353 /* update cache */ 1354 xfer->td_transfer_cache = td; 1355 goto done; 1356 } 1357 /* 1358 * last transfer descriptor makes the transfer done 1359 */ 1360 if (((void *)td) == xfer->td_transfer_last) { 1361 break; 1362 } 1363 /* 1364 * any kind of error makes the transfer done 1365 */ 1366 if (status & EHCI_QTD_HALTED) { 1367 break; 1368 } 1369 /* 1370 * if there is no alternate next transfer, a short 1371 * packet also makes the transfer done 1372 */ 1373 if (EHCI_QTD_GET_BYTES(status)) { 1374 if (xfer->flags_int.short_frames_ok) { 1375 /* follow alt next */ 1376 if (td->alt_next) { 1377 td = td->alt_next; 1378 continue; 1379 } 1380 } 1381 /* transfer is done */ 1382 break; 1383 } 1384 td = td->obj_next; 1385 } 1386 ehci_non_isoc_done(xfer); 1387 goto transferred; 1388 } 1389 1390done: 1391 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1392 return (0); 1393 1394transferred: 1395 return (1); 1396} 1397 1398static void 1399ehci_pcd_enable(ehci_softc_t *sc) 1400{ 1401 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1402 1403 sc->sc_eintrs |= EHCI_STS_PCD; 1404 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1405 1406 /* acknowledge any PCD interrupt */ 1407 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1408 1409 ehci_root_intr(sc); 1410} 1411 1412static void 1413ehci_interrupt_poll(ehci_softc_t *sc) 1414{ 1415 struct usb_xfer *xfer; 1416 1417repeat: 1418 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1419 /* 1420 * check if transfer is transferred 1421 */ 1422 if (ehci_check_transfer(xfer)) { 1423 /* queue has been modified */ 1424 goto repeat; 1425 } 1426 } 1427} 1428 1429/* 1430 * Some EHCI chips from VIA / ATI seem to trigger interrupts before 1431 * writing back the qTD status, or miss signalling occasionally under 1432 * heavy load. If the host machine is too fast, we can miss 1433 * transaction completion - when we scan the active list the 1434 * transaction still seems to be active. This generally exhibits 1435 * itself as a umass stall that never recovers. 1436 * 1437 * We work around this behaviour by setting up this callback after any 1438 * softintr that completes with transactions still pending, giving us 1439 * another chance to check for completion after the writeback has 1440 * taken place. 1441 */ 1442static void 1443ehci_poll_timeout(void *arg) 1444{ 1445 ehci_softc_t *sc = arg; 1446 1447 DPRINTFN(3, "\n"); 1448 ehci_interrupt_poll(sc); 1449} 1450 1451/*------------------------------------------------------------------------* 1452 * ehci_interrupt - EHCI interrupt handler 1453 * 1454 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1455 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1456 * is present ! 1457 *------------------------------------------------------------------------*/ 1458void 1459ehci_interrupt(ehci_softc_t *sc) 1460{ 1461 uint32_t status; 1462 1463 USB_BUS_LOCK(&sc->sc_bus); 1464 1465 DPRINTFN(16, "real interrupt\n"); 1466 1467#ifdef USB_DEBUG 1468 if (ehcidebug > 15) { 1469 ehci_dump_regs(sc); 1470 } 1471#endif 1472 1473 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1474 if (status == 0) { 1475 /* the interrupt was not for us */ 1476 goto done; 1477 } 1478 if (!(status & sc->sc_eintrs)) { 1479 goto done; 1480 } 1481 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1482 1483 status &= sc->sc_eintrs; 1484 1485 if (status & EHCI_STS_HSE) { 1486 printf("%s: unrecoverable error, " 1487 "controller halted\n", __FUNCTION__); 1488#ifdef USB_DEBUG 1489 ehci_dump_regs(sc); 1490 ehci_dump_isoc(sc); 1491#endif 1492 } 1493 if (status & EHCI_STS_PCD) { 1494 /* 1495 * Disable PCD interrupt for now, because it will be 1496 * on until the port has been reset. 1497 */ 1498 sc->sc_eintrs &= ~EHCI_STS_PCD; 1499 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1500 1501 ehci_root_intr(sc); 1502 1503 /* do not allow RHSC interrupts > 1 per second */ 1504 usb_callout_reset(&sc->sc_tmo_pcd, hz, 1505 (void *)&ehci_pcd_enable, sc); 1506 } 1507 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1508 1509 if (status != 0) { 1510 /* block unprocessed interrupts */ 1511 sc->sc_eintrs &= ~status; 1512 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1513 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status); 1514 } 1515 /* poll all the USB transfers */ 1516 ehci_interrupt_poll(sc); 1517 1518 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) { 1519 usb_callout_reset(&sc->sc_tmo_poll, hz / 128, 1520 (void *)&ehci_poll_timeout, sc); 1521 } 1522 1523done: 1524 USB_BUS_UNLOCK(&sc->sc_bus); 1525} 1526 1527/* 1528 * called when a request does not complete 1529 */ 1530static void 1531ehci_timeout(void *arg) 1532{ 1533 struct usb_xfer *xfer = arg; 1534 1535 DPRINTF("xfer=%p\n", xfer); 1536 1537 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1538 1539 /* transfer is transferred */ 1540 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1541} 1542 1543static void 1544ehci_do_poll(struct usb_bus *bus) 1545{ 1546 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1547 1548 USB_BUS_LOCK(&sc->sc_bus); 1549 ehci_interrupt_poll(sc); 1550 USB_BUS_UNLOCK(&sc->sc_bus); 1551} 1552 1553static void 1554ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1555{ 1556 struct usb_page_search buf_res; 1557 ehci_qtd_t *td; 1558 ehci_qtd_t *td_next; 1559 ehci_qtd_t *td_alt_next; 1560 uint32_t buf_offset; 1561 uint32_t average; 1562 uint32_t len_old; 1563 uint32_t terminate; 1564 uint32_t qtd_altnext; 1565 uint8_t shortpkt_old; 1566 uint8_t precompute; 1567 1568 terminate = temp->sc->sc_terminate_self; 1569 qtd_altnext = temp->sc->sc_terminate_self; 1570 td_alt_next = NULL; 1571 buf_offset = 0; 1572 shortpkt_old = temp->shortpkt; 1573 len_old = temp->len; 1574 precompute = 1; 1575 1576restart: 1577 1578 td = temp->td; 1579 td_next = temp->td_next; 1580 1581 while (1) { 1582 1583 if (temp->len == 0) { 1584 1585 if (temp->shortpkt) { 1586 break; 1587 } 1588 /* send a Zero Length Packet, ZLP, last */ 1589 1590 temp->shortpkt = 1; 1591 average = 0; 1592 1593 } else { 1594 1595 average = temp->average; 1596 1597 if (temp->len < average) { 1598 if (temp->len % temp->max_frame_size) { 1599 temp->shortpkt = 1; 1600 } 1601 average = temp->len; 1602 } 1603 } 1604 1605 if (td_next == NULL) { 1606 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__); 1607 } 1608 /* get next TD */ 1609 1610 td = td_next; 1611 td_next = td->obj_next; 1612 1613 /* check if we are pre-computing */ 1614 1615 if (precompute) { 1616 1617 /* update remaining length */ 1618 1619 temp->len -= average; 1620 1621 continue; 1622 } 1623 /* fill out current TD */ 1624 1625 td->qtd_status = 1626 temp->qtd_status | 1627 htohc32(temp->sc, EHCI_QTD_IOC | 1628 EHCI_QTD_SET_BYTES(average)); 1629 1630 if (average == 0) { 1631 1632 if (temp->auto_data_toggle == 0) { 1633 1634 /* update data toggle, ZLP case */ 1635 1636 temp->qtd_status ^= 1637 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1638 } 1639 td->len = 0; 1640 1641 /* properly reset reserved fields */ 1642 td->qtd_buffer[0] = 0; 1643 td->qtd_buffer[1] = 0; 1644 td->qtd_buffer[2] = 0; 1645 td->qtd_buffer[3] = 0; 1646 td->qtd_buffer[4] = 0; 1647 td->qtd_buffer_hi[0] = 0; 1648 td->qtd_buffer_hi[1] = 0; 1649 td->qtd_buffer_hi[2] = 0; 1650 td->qtd_buffer_hi[3] = 0; 1651 td->qtd_buffer_hi[4] = 0; 1652 } else { 1653 1654 uint8_t x; 1655 1656 if (temp->auto_data_toggle == 0) { 1657 1658 /* update data toggle */ 1659 1660 if (howmany(average, temp->max_frame_size) & 1) { 1661 temp->qtd_status ^= 1662 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1663 } 1664 } 1665 td->len = average; 1666 1667 /* update remaining length */ 1668 1669 temp->len -= average; 1670 1671 /* fill out buffer pointers */ 1672 1673 usbd_get_page(temp->pc, buf_offset, &buf_res); 1674 td->qtd_buffer[0] = 1675 htohc32(temp->sc, buf_res.physaddr); 1676 td->qtd_buffer_hi[0] = 0; 1677 1678 x = 1; 1679 1680 while (average > EHCI_PAGE_SIZE) { 1681 average -= EHCI_PAGE_SIZE; 1682 buf_offset += EHCI_PAGE_SIZE; 1683 usbd_get_page(temp->pc, buf_offset, &buf_res); 1684 td->qtd_buffer[x] = 1685 htohc32(temp->sc, 1686 buf_res.physaddr & (~0xFFF)); 1687 td->qtd_buffer_hi[x] = 0; 1688 x++; 1689 } 1690 1691 /* 1692 * NOTE: The "average" variable is never zero after 1693 * exiting the loop above ! 1694 * 1695 * NOTE: We have to subtract one from the offset to 1696 * ensure that we are computing the physical address 1697 * of a valid page ! 1698 */ 1699 buf_offset += average; 1700 usbd_get_page(temp->pc, buf_offset - 1, &buf_res); 1701 td->qtd_buffer[x] = 1702 htohc32(temp->sc, 1703 buf_res.physaddr & (~0xFFF)); 1704 td->qtd_buffer_hi[x] = 0; 1705 1706 /* properly reset reserved fields */ 1707 while (++x < EHCI_QTD_NBUFFERS) { 1708 td->qtd_buffer[x] = 0; 1709 td->qtd_buffer_hi[x] = 0; 1710 } 1711 } 1712 1713 if (td_next) { 1714 /* link the current TD with the next one */ 1715 td->qtd_next = td_next->qtd_self; 1716 } 1717 td->qtd_altnext = qtd_altnext; 1718 td->alt_next = td_alt_next; 1719 1720 usb_pc_cpu_flush(td->page_cache); 1721 } 1722 1723 if (precompute) { 1724 precompute = 0; 1725 1726 /* setup alt next pointer, if any */ 1727 if (temp->last_frame) { 1728 td_alt_next = NULL; 1729 qtd_altnext = terminate; 1730 } else { 1731 /* we use this field internally */ 1732 td_alt_next = td_next; 1733 if (temp->setup_alt_next) { 1734 qtd_altnext = td_next->qtd_self; 1735 } else { 1736 qtd_altnext = terminate; 1737 } 1738 } 1739 1740 /* restore */ 1741 temp->shortpkt = shortpkt_old; 1742 temp->len = len_old; 1743 goto restart; 1744 } 1745 temp->td = td; 1746 temp->td_next = td_next; 1747} 1748 1749static void 1750ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last) 1751{ 1752 struct ehci_std_temp temp; 1753 const struct usb_pipe_methods *methods; 1754 ehci_qh_t *qh; 1755 ehci_qtd_t *td; 1756 uint32_t qh_endp; 1757 uint32_t qh_endphub; 1758 uint32_t x; 1759 1760 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1761 xfer->address, UE_GET_ADDR(xfer->endpointno), 1762 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1763 1764 temp.average = xfer->max_hc_frame_size; 1765 temp.max_frame_size = xfer->max_frame_size; 1766 temp.sc = EHCI_BUS2SC(xfer->xroot->bus); 1767 1768 /* toggle the DMA set we are using */ 1769 xfer->flags_int.curr_dma_set ^= 1; 1770 1771 /* get next DMA set */ 1772 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1773 1774 xfer->td_transfer_first = td; 1775 xfer->td_transfer_cache = td; 1776 1777 temp.td = NULL; 1778 temp.td_next = td; 1779 temp.qtd_status = 0; 1780 temp.last_frame = 0; 1781 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1782 1783 if (xfer->flags_int.control_xfr) { 1784 if (xfer->endpoint->toggle_next) { 1785 /* DATA1 is next */ 1786 temp.qtd_status |= 1787 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1788 } 1789 temp.auto_data_toggle = 0; 1790 } else { 1791 temp.auto_data_toggle = 1; 1792 } 1793 1794 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1795 (xfer->xroot->udev->address != 0)) { 1796 /* max 3 retries */ 1797 temp.qtd_status |= 1798 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1799 } 1800 /* check if we should prepend a setup message */ 1801 1802 if (xfer->flags_int.control_xfr) { 1803 if (xfer->flags_int.control_hdr) { 1804 1805 xfer->endpoint->toggle_next = 0; 1806 1807 temp.qtd_status &= 1808 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1809 temp.qtd_status |= htohc32(temp.sc, 1810 EHCI_QTD_ACTIVE | 1811 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1812 EHCI_QTD_SET_TOGGLE(0)); 1813 1814 temp.len = xfer->frlengths[0]; 1815 temp.pc = xfer->frbuffers + 0; 1816 temp.shortpkt = temp.len ? 1 : 0; 1817 /* check for last frame */ 1818 if (xfer->nframes == 1) { 1819 /* no STATUS stage yet, SETUP is last */ 1820 if (xfer->flags_int.control_act) { 1821 temp.last_frame = 1; 1822 temp.setup_alt_next = 0; 1823 } 1824 } 1825 ehci_setup_standard_chain_sub(&temp); 1826 } 1827 x = 1; 1828 } else { 1829 x = 0; 1830 } 1831 1832 while (x != xfer->nframes) { 1833 1834 /* DATA0 / DATA1 message */ 1835 1836 temp.len = xfer->frlengths[x]; 1837 temp.pc = xfer->frbuffers + x; 1838 1839 x++; 1840 1841 if (x == xfer->nframes) { 1842 if (xfer->flags_int.control_xfr) { 1843 /* no STATUS stage yet, DATA is last */ 1844 if (xfer->flags_int.control_act) { 1845 temp.last_frame = 1; 1846 temp.setup_alt_next = 0; 1847 } 1848 } else { 1849 temp.last_frame = 1; 1850 temp.setup_alt_next = 0; 1851 } 1852 } 1853 /* keep previous data toggle and error count */ 1854 1855 temp.qtd_status &= 1856 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1857 EHCI_QTD_SET_TOGGLE(1)); 1858 1859 if (temp.len == 0) { 1860 1861 /* make sure that we send an USB packet */ 1862 1863 temp.shortpkt = 0; 1864 1865 } else { 1866 1867 /* regular data transfer */ 1868 1869 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1870 } 1871 1872 /* set endpoint direction */ 1873 1874 temp.qtd_status |= 1875 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1876 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1877 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1878 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1879 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1880 1881 ehci_setup_standard_chain_sub(&temp); 1882 } 1883 1884 /* check if we should append a status stage */ 1885 1886 if (xfer->flags_int.control_xfr && 1887 !xfer->flags_int.control_act) { 1888 1889 /* 1890 * Send a DATA1 message and invert the current endpoint 1891 * direction. 1892 */ 1893 1894 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1895 EHCI_QTD_SET_TOGGLE(1)); 1896 temp.qtd_status |= 1897 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1898 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1899 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1900 EHCI_QTD_SET_TOGGLE(1)) : 1901 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1902 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1903 EHCI_QTD_SET_TOGGLE(1)); 1904 1905 temp.len = 0; 1906 temp.pc = NULL; 1907 temp.shortpkt = 0; 1908 temp.last_frame = 1; 1909 temp.setup_alt_next = 0; 1910 1911 ehci_setup_standard_chain_sub(&temp); 1912 } 1913 td = temp.td; 1914 1915 /* the last TD terminates the transfer: */ 1916 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1917 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1918 1919 usb_pc_cpu_flush(td->page_cache); 1920 1921 /* must have at least one frame! */ 1922 1923 xfer->td_transfer_last = td; 1924 1925#ifdef USB_DEBUG 1926 if (ehcidebug > 8) { 1927 DPRINTF("nexttog=%d; data before transfer:\n", 1928 xfer->endpoint->toggle_next); 1929 ehci_dump_sqtds(temp.sc, 1930 xfer->td_transfer_first); 1931 } 1932#endif 1933 1934 methods = xfer->endpoint->methods; 1935 1936 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1937 1938 /* the "qh_link" field is filled when the QH is added */ 1939 1940 qh_endp = 1941 (EHCI_QH_SET_ADDR(xfer->address) | 1942 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 1943 EHCI_QH_SET_MPL(xfer->max_packet_size)); 1944 1945 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 1946 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH); 1947 if (methods != &ehci_device_intr_methods) 1948 qh_endp |= EHCI_QH_SET_NRL(8); 1949 } else { 1950 1951 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) { 1952 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL); 1953 } else { 1954 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW); 1955 } 1956 1957 if (methods == &ehci_device_ctrl_methods) { 1958 qh_endp |= EHCI_QH_CTL; 1959 } 1960 if (methods != &ehci_device_intr_methods) { 1961 /* Only try one time per microframe! */ 1962 qh_endp |= EHCI_QH_SET_NRL(1); 1963 } 1964 } 1965 1966 if (temp.auto_data_toggle == 0) { 1967 /* software computes the data toggle */ 1968 qh_endp |= EHCI_QH_DTC; 1969 } 1970 1971 qh->qh_endp = htohc32(temp.sc, qh_endp); 1972 1973 qh_endphub = 1974 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 1975 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) | 1976 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) | 1977 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 1978 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no)); 1979 1980 qh->qh_endphub = htohc32(temp.sc, qh_endphub); 1981 qh->qh_curqtd = 0; 1982 1983 /* fill the overlay qTD */ 1984 1985 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) { 1986 /* DATA1 is next */ 1987 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1988 } else { 1989 qh->qh_qtd.qtd_status = 0; 1990 } 1991 1992 td = xfer->td_transfer_first; 1993 1994 qh->qh_qtd.qtd_next = td->qtd_self; 1995 qh->qh_qtd.qtd_altnext = 1996 htohc32(temp.sc, EHCI_LINK_TERMINATE); 1997 1998 /* properly reset reserved fields */ 1999 qh->qh_qtd.qtd_buffer[0] = 0; 2000 qh->qh_qtd.qtd_buffer[1] = 0; 2001 qh->qh_qtd.qtd_buffer[2] = 0; 2002 qh->qh_qtd.qtd_buffer[3] = 0; 2003 qh->qh_qtd.qtd_buffer[4] = 0; 2004 qh->qh_qtd.qtd_buffer_hi[0] = 0; 2005 qh->qh_qtd.qtd_buffer_hi[1] = 0; 2006 qh->qh_qtd.qtd_buffer_hi[2] = 0; 2007 qh->qh_qtd.qtd_buffer_hi[3] = 0; 2008 qh->qh_qtd.qtd_buffer_hi[4] = 0; 2009 2010 usb_pc_cpu_flush(qh->page_cache); 2011 2012 if (xfer->xroot->udev->flags.self_suspended == 0) { 2013 EHCI_APPEND_QH(qh, *qh_last); 2014 } 2015} 2016 2017static void 2018ehci_root_intr(ehci_softc_t *sc) 2019{ 2020 uint16_t i; 2021 uint16_t m; 2022 2023 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2024 2025 /* clear any old interrupt data */ 2026 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2027 2028 /* set bits */ 2029 m = (sc->sc_noport + 1); 2030 if (m > (8 * sizeof(sc->sc_hub_idata))) { 2031 m = (8 * sizeof(sc->sc_hub_idata)); 2032 } 2033 for (i = 1; i < m; i++) { 2034 /* pick out CHANGE bits from the status register */ 2035 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 2036 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2037 DPRINTF("port %d changed\n", i); 2038 } 2039 } 2040 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2041 sizeof(sc->sc_hub_idata)); 2042} 2043 2044static void 2045ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2046{ 2047 uint32_t nframes = xfer->nframes; 2048 uint32_t status; 2049 uint32_t *plen = xfer->frlengths; 2050 uint16_t len = 0; 2051 ehci_sitd_t *td = xfer->td_transfer_first; 2052 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 2053 2054 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2055 xfer, xfer->endpoint); 2056 2057 while (nframes--) { 2058 if (td == NULL) { 2059 panic("%s:%d: out of TD's\n", 2060 __FUNCTION__, __LINE__); 2061 } 2062 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2063 pp_last = &sc->sc_isoc_fs_p_last[0]; 2064 } 2065#ifdef USB_DEBUG 2066 if (ehcidebug > 15) { 2067 DPRINTF("isoc FS-TD\n"); 2068 ehci_dump_sitd(sc, td); 2069 } 2070#endif 2071 usb_pc_cpu_invalidate(td->page_cache); 2072 status = hc32toh(sc, td->sitd_status); 2073 2074 len = EHCI_SITD_GET_LEN(status); 2075 2076 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len); 2077 2078 if (*plen >= len) { 2079 len = *plen - len; 2080 } else { 2081 len = 0; 2082 } 2083 2084 *plen = len; 2085 2086 /* remove FS-TD from schedule */ 2087 EHCI_REMOVE_FS_TD(td, *pp_last); 2088 2089 pp_last++; 2090 plen++; 2091 td = td->obj_next; 2092 } 2093 2094 xfer->aframes = xfer->nframes; 2095} 2096 2097static void 2098ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2099{ 2100 uint32_t nframes = xfer->nframes; 2101 uint32_t status; 2102 uint32_t *plen = xfer->frlengths; 2103 uint16_t len = 0; 2104 uint8_t td_no = 0; 2105 ehci_itd_t *td = xfer->td_transfer_first; 2106 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2107 2108 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2109 xfer, xfer->endpoint); 2110 2111 while (nframes) { 2112 if (td == NULL) { 2113 panic("%s:%d: out of TD's\n", 2114 __FUNCTION__, __LINE__); 2115 } 2116 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2117 pp_last = &sc->sc_isoc_hs_p_last[0]; 2118 } 2119#ifdef USB_DEBUG 2120 if (ehcidebug > 15) { 2121 DPRINTF("isoc HS-TD\n"); 2122 ehci_dump_itd(sc, td); 2123 } 2124#endif 2125 2126 usb_pc_cpu_invalidate(td->page_cache); 2127 status = hc32toh(sc, td->itd_status[td_no]); 2128 2129 len = EHCI_ITD_GET_LEN(status); 2130 2131 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len); 2132 2133 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2134 2135 if (*plen >= len) { 2136 /* 2137 * The length is valid. NOTE: The 2138 * complete length is written back 2139 * into the status field, and not the 2140 * remainder like with other transfer 2141 * descriptor types. 2142 */ 2143 } else { 2144 /* Invalid length - truncate */ 2145 len = 0; 2146 } 2147 2148 *plen = len; 2149 plen++; 2150 nframes--; 2151 } 2152 2153 td_no++; 2154 2155 if ((td_no == 8) || (nframes == 0)) { 2156 /* remove HS-TD from schedule */ 2157 EHCI_REMOVE_HS_TD(td, *pp_last); 2158 pp_last++; 2159 2160 td_no = 0; 2161 td = td->obj_next; 2162 } 2163 } 2164 xfer->aframes = xfer->nframes; 2165} 2166 2167/* NOTE: "done" can be run two times in a row, 2168 * from close and from interrupt 2169 */ 2170static void 2171ehci_device_done(struct usb_xfer *xfer, usb_error_t error) 2172{ 2173 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 2174 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2175 2176 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2177 2178 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2179 xfer, xfer->endpoint, error); 2180 2181 if ((methods == &ehci_device_bulk_methods) || 2182 (methods == &ehci_device_ctrl_methods)) { 2183#ifdef USB_DEBUG 2184 if (ehcidebug > 8) { 2185 DPRINTF("nexttog=%d; data after transfer:\n", 2186 xfer->endpoint->toggle_next); 2187 ehci_dump_sqtds(sc, 2188 xfer->td_transfer_first); 2189 } 2190#endif 2191 2192 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2193 sc->sc_async_p_last); 2194 } 2195 if (methods == &ehci_device_intr_methods) { 2196 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2197 sc->sc_intr_p_last[xfer->qh_pos]); 2198 } 2199 /* 2200 * Only finish isochronous transfers once which will update 2201 * "xfer->frlengths". 2202 */ 2203 if (xfer->td_transfer_first && 2204 xfer->td_transfer_last) { 2205 if (methods == &ehci_device_isoc_fs_methods) { 2206 ehci_isoc_fs_done(sc, xfer); 2207 } 2208 if (methods == &ehci_device_isoc_hs_methods) { 2209 ehci_isoc_hs_done(sc, xfer); 2210 } 2211 xfer->td_transfer_first = NULL; 2212 xfer->td_transfer_last = NULL; 2213 } 2214 /* dequeue transfer and start next transfer */ 2215 usbd_transfer_done(xfer, error); 2216} 2217 2218/*------------------------------------------------------------------------* 2219 * ehci bulk support 2220 *------------------------------------------------------------------------*/ 2221static void 2222ehci_device_bulk_open(struct usb_xfer *xfer) 2223{ 2224 return; 2225} 2226 2227static void 2228ehci_device_bulk_close(struct usb_xfer *xfer) 2229{ 2230 ehci_device_done(xfer, USB_ERR_CANCELLED); 2231} 2232 2233static void 2234ehci_device_bulk_enter(struct usb_xfer *xfer) 2235{ 2236 return; 2237} 2238 2239static void 2240ehci_doorbell_async(struct ehci_softc *sc) 2241{ 2242 uint32_t temp; 2243 2244 /* 2245 * XXX Performance quirk: Some Host Controllers have a too low 2246 * interrupt rate. Issue an IAAD to stimulate the Host 2247 * Controller after queueing the BULK transfer. 2248 * 2249 * XXX Force the host controller to refresh any QH caches. 2250 */ 2251 temp = EOREAD4(sc, EHCI_USBCMD); 2252 if (!(temp & EHCI_CMD_IAAD)) 2253 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 2254} 2255 2256static void 2257ehci_device_bulk_start(struct usb_xfer *xfer) 2258{ 2259 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2260 2261 /* setup TD's and QH */ 2262 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2263 2264 /* put transfer on interrupt queue */ 2265 ehci_transfer_intr_enqueue(xfer); 2266 2267 /* 2268 * XXX Certain nVidia chipsets choke when using the IAAD 2269 * feature too frequently. 2270 */ 2271 if (sc->sc_flags & EHCI_SCFLG_IAADBUG) 2272 return; 2273 2274 ehci_doorbell_async(sc); 2275} 2276 2277static const struct usb_pipe_methods ehci_device_bulk_methods = 2278{ 2279 .open = ehci_device_bulk_open, 2280 .close = ehci_device_bulk_close, 2281 .enter = ehci_device_bulk_enter, 2282 .start = ehci_device_bulk_start, 2283}; 2284 2285/*------------------------------------------------------------------------* 2286 * ehci control support 2287 *------------------------------------------------------------------------*/ 2288static void 2289ehci_device_ctrl_open(struct usb_xfer *xfer) 2290{ 2291 return; 2292} 2293 2294static void 2295ehci_device_ctrl_close(struct usb_xfer *xfer) 2296{ 2297 ehci_device_done(xfer, USB_ERR_CANCELLED); 2298} 2299 2300static void 2301ehci_device_ctrl_enter(struct usb_xfer *xfer) 2302{ 2303 return; 2304} 2305 2306static void 2307ehci_device_ctrl_start(struct usb_xfer *xfer) 2308{ 2309 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2310 2311 /* setup TD's and QH */ 2312 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2313 2314 /* put transfer on interrupt queue */ 2315 ehci_transfer_intr_enqueue(xfer); 2316} 2317 2318static const struct usb_pipe_methods ehci_device_ctrl_methods = 2319{ 2320 .open = ehci_device_ctrl_open, 2321 .close = ehci_device_ctrl_close, 2322 .enter = ehci_device_ctrl_enter, 2323 .start = ehci_device_ctrl_start, 2324}; 2325 2326/*------------------------------------------------------------------------* 2327 * ehci interrupt support 2328 *------------------------------------------------------------------------*/ 2329static void 2330ehci_device_intr_open(struct usb_xfer *xfer) 2331{ 2332 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2333 uint16_t best; 2334 uint16_t bit; 2335 uint16_t x; 2336 2337 usb_hs_bandwidth_alloc(xfer); 2338 2339 /* 2340 * Find the best QH position corresponding to the given interval: 2341 */ 2342 2343 best = 0; 2344 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2345 while (bit) { 2346 if (xfer->interval >= bit) { 2347 x = bit; 2348 best = bit; 2349 while (x & bit) { 2350 if (sc->sc_intr_stat[x] < 2351 sc->sc_intr_stat[best]) { 2352 best = x; 2353 } 2354 x++; 2355 } 2356 break; 2357 } 2358 bit >>= 1; 2359 } 2360 2361 sc->sc_intr_stat[best]++; 2362 xfer->qh_pos = best; 2363 2364 DPRINTFN(3, "best=%d interval=%d\n", 2365 best, xfer->interval); 2366} 2367 2368static void 2369ehci_device_intr_close(struct usb_xfer *xfer) 2370{ 2371 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2372 2373 sc->sc_intr_stat[xfer->qh_pos]--; 2374 2375 ehci_device_done(xfer, USB_ERR_CANCELLED); 2376 2377 /* bandwidth must be freed after device done */ 2378 usb_hs_bandwidth_free(xfer); 2379} 2380 2381static void 2382ehci_device_intr_enter(struct usb_xfer *xfer) 2383{ 2384 return; 2385} 2386 2387static void 2388ehci_device_intr_start(struct usb_xfer *xfer) 2389{ 2390 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2391 2392 /* setup TD's and QH */ 2393 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2394 2395 /* put transfer on interrupt queue */ 2396 ehci_transfer_intr_enqueue(xfer); 2397} 2398 2399static const struct usb_pipe_methods ehci_device_intr_methods = 2400{ 2401 .open = ehci_device_intr_open, 2402 .close = ehci_device_intr_close, 2403 .enter = ehci_device_intr_enter, 2404 .start = ehci_device_intr_start, 2405}; 2406 2407/*------------------------------------------------------------------------* 2408 * ehci full speed isochronous support 2409 *------------------------------------------------------------------------*/ 2410static void 2411ehci_device_isoc_fs_open(struct usb_xfer *xfer) 2412{ 2413 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2414 ehci_sitd_t *td; 2415 uint32_t sitd_portaddr; 2416 uint8_t ds; 2417 2418 sitd_portaddr = 2419 EHCI_SITD_SET_ADDR(xfer->address) | 2420 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 2421 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2422 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no); 2423 2424 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 2425 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2426 2427 sitd_portaddr = htohc32(sc, sitd_portaddr); 2428 2429 /* initialize all TD's */ 2430 2431 for (ds = 0; ds != 2; ds++) { 2432 2433 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2434 2435 td->sitd_portaddr = sitd_portaddr; 2436 2437 /* 2438 * TODO: make some kind of automatic 2439 * SMASK/CMASK selection based on micro-frame 2440 * usage 2441 * 2442 * micro-frame usage (8 microframes per 1ms) 2443 */ 2444 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE); 2445 2446 usb_pc_cpu_flush(td->page_cache); 2447 } 2448 } 2449} 2450 2451static void 2452ehci_device_isoc_fs_close(struct usb_xfer *xfer) 2453{ 2454 ehci_device_done(xfer, USB_ERR_CANCELLED); 2455} 2456 2457static void 2458ehci_device_isoc_fs_enter(struct usb_xfer *xfer) 2459{ 2460 struct usb_page_search buf_res; 2461 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2462 ehci_sitd_t *td; 2463 ehci_sitd_t *td_last = NULL; 2464 ehci_sitd_t **pp_last; 2465 uint32_t *plen; 2466 uint32_t buf_offset; 2467 uint32_t nframes; 2468 uint32_t temp; 2469 uint32_t sitd_mask; 2470 uint16_t tlen; 2471 uint8_t sa; 2472 uint8_t sb; 2473 2474#ifdef USB_DEBUG 2475 uint8_t once = 1; 2476 2477#endif 2478 2479 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2480 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2481 2482 /* get the current frame index */ 2483 2484 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2485 2486 /* 2487 * check if the frame index is within the window where the frames 2488 * will be inserted 2489 */ 2490 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2491 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2492 2493 if ((xfer->endpoint->is_synced == 0) || 2494 (buf_offset < xfer->nframes)) { 2495 /* 2496 * If there is data underflow or the pipe queue is empty we 2497 * schedule the transfer a few frames ahead of the current 2498 * frame position. Else two isochronous transfers might 2499 * overlap. 2500 */ 2501 xfer->endpoint->isoc_next = (nframes + 3) & 2502 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2503 xfer->endpoint->is_synced = 1; 2504 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2505 } 2506 /* 2507 * compute how many milliseconds the insertion is ahead of the 2508 * current frame position: 2509 */ 2510 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2511 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2512 2513 /* 2514 * pre-compute when the isochronous transfer will be finished: 2515 */ 2516 xfer->isoc_time_complete = 2517 usb_isoc_time_expand(&sc->sc_bus, nframes) + 2518 buf_offset + xfer->nframes; 2519 2520 /* get the real number of frames */ 2521 2522 nframes = xfer->nframes; 2523 2524 buf_offset = 0; 2525 2526 plen = xfer->frlengths; 2527 2528 /* toggle the DMA set we are using */ 2529 xfer->flags_int.curr_dma_set ^= 1; 2530 2531 /* get next DMA set */ 2532 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2533 xfer->td_transfer_first = td; 2534 2535 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next]; 2536 2537 /* store starting position */ 2538 2539 xfer->qh_pos = xfer->endpoint->isoc_next; 2540 2541 while (nframes--) { 2542 if (td == NULL) { 2543 panic("%s:%d: out of TD's\n", 2544 __FUNCTION__, __LINE__); 2545 } 2546 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) 2547 pp_last = &sc->sc_isoc_fs_p_last[0]; 2548 2549 /* reuse sitd_portaddr and sitd_back from last transfer */ 2550 2551 if (*plen > xfer->max_frame_size) { 2552#ifdef USB_DEBUG 2553 if (once) { 2554 once = 0; 2555 printf("%s: frame length(%d) exceeds %d " 2556 "bytes (frame truncated)\n", 2557 __FUNCTION__, *plen, 2558 xfer->max_frame_size); 2559 } 2560#endif 2561 *plen = xfer->max_frame_size; 2562 } 2563 2564 /* allocate a slot */ 2565 2566 sa = usbd_fs_isoc_schedule_alloc_slot(xfer, 2567 xfer->isoc_time_complete - nframes - 1); 2568 2569 if (sa == 255) { 2570 /* 2571 * Schedule is FULL, set length to zero: 2572 */ 2573 2574 *plen = 0; 2575 sa = USB_FS_ISOC_UFRAME_MAX - 1; 2576 } 2577 if (*plen) { 2578 /* 2579 * only call "usbd_get_page()" when we have a 2580 * non-zero length 2581 */ 2582 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res); 2583 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr); 2584 buf_offset += *plen; 2585 /* 2586 * NOTE: We need to subtract one from the offset so 2587 * that we are on a valid page! 2588 */ 2589 usbd_get_page(xfer->frbuffers, buf_offset - 1, 2590 &buf_res); 2591 temp = buf_res.physaddr & ~0xFFF; 2592 } else { 2593 td->sitd_bp[0] = 0; 2594 temp = 0; 2595 } 2596 2597 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) { 2598 tlen = *plen; 2599 if (tlen <= 188) { 2600 temp |= 1; /* T-count = 1, TP = ALL */ 2601 tlen = 1; 2602 } else { 2603 tlen += 187; 2604 tlen /= 188; 2605 temp |= tlen; /* T-count = [1..6] */ 2606 temp |= 8; /* TP = Begin */ 2607 } 2608 2609 tlen += sa; 2610 2611 if (tlen >= 8) { 2612 sb = 0; 2613 } else { 2614 sb = (1 << tlen); 2615 } 2616 2617 sa = (1 << sa); 2618 sa = (sb - sa) & 0x3F; 2619 sb = 0; 2620 } else { 2621 sb = (-(4 << sa)) & 0xFE; 2622 sa = (1 << sa) & 0x3F; 2623 } 2624 2625 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2626 EHCI_SITD_SET_CMASK(sb)); 2627 2628 td->sitd_bp[1] = htohc32(sc, temp); 2629 2630 td->sitd_mask = htohc32(sc, sitd_mask); 2631 2632 if (nframes == 0) { 2633 td->sitd_status = htohc32(sc, 2634 EHCI_SITD_IOC | 2635 EHCI_SITD_ACTIVE | 2636 EHCI_SITD_SET_LEN(*plen)); 2637 } else { 2638 td->sitd_status = htohc32(sc, 2639 EHCI_SITD_ACTIVE | 2640 EHCI_SITD_SET_LEN(*plen)); 2641 } 2642 usb_pc_cpu_flush(td->page_cache); 2643 2644#ifdef USB_DEBUG 2645 if (ehcidebug > 15) { 2646 DPRINTF("FS-TD %d\n", nframes); 2647 ehci_dump_sitd(sc, td); 2648 } 2649#endif 2650 /* insert TD into schedule */ 2651 EHCI_APPEND_FS_TD(td, *pp_last); 2652 pp_last++; 2653 2654 plen++; 2655 td_last = td; 2656 td = td->obj_next; 2657 } 2658 2659 xfer->td_transfer_last = td_last; 2660 2661 /* update isoc_next */ 2662 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2663 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2664 2665 /* 2666 * We don't allow cancelling of the SPLIT transaction USB FULL 2667 * speed transfer, because it disturbs the bandwidth 2668 * computation algorithm. 2669 */ 2670 xfer->flags_int.can_cancel_immed = 0; 2671} 2672 2673static void 2674ehci_device_isoc_fs_start(struct usb_xfer *xfer) 2675{ 2676 /* 2677 * We don't allow cancelling of the SPLIT transaction USB FULL 2678 * speed transfer, because it disturbs the bandwidth 2679 * computation algorithm. 2680 */ 2681 xfer->flags_int.can_cancel_immed = 0; 2682 2683 /* set a default timeout */ 2684 if (xfer->timeout == 0) 2685 xfer->timeout = 500; /* ms */ 2686 2687 /* put transfer on interrupt queue */ 2688 ehci_transfer_intr_enqueue(xfer); 2689} 2690 2691static const struct usb_pipe_methods ehci_device_isoc_fs_methods = 2692{ 2693 .open = ehci_device_isoc_fs_open, 2694 .close = ehci_device_isoc_fs_close, 2695 .enter = ehci_device_isoc_fs_enter, 2696 .start = ehci_device_isoc_fs_start, 2697}; 2698 2699/*------------------------------------------------------------------------* 2700 * ehci high speed isochronous support 2701 *------------------------------------------------------------------------*/ 2702static void 2703ehci_device_isoc_hs_open(struct usb_xfer *xfer) 2704{ 2705 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2706 ehci_itd_t *td; 2707 uint32_t temp; 2708 uint8_t ds; 2709 2710 usb_hs_bandwidth_alloc(xfer); 2711 2712 /* initialize all TD's */ 2713 2714 for (ds = 0; ds != 2; ds++) { 2715 2716 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2717 2718 /* set TD inactive */ 2719 td->itd_status[0] = 0; 2720 td->itd_status[1] = 0; 2721 td->itd_status[2] = 0; 2722 td->itd_status[3] = 0; 2723 td->itd_status[4] = 0; 2724 td->itd_status[5] = 0; 2725 td->itd_status[6] = 0; 2726 td->itd_status[7] = 0; 2727 2728 /* set endpoint and address */ 2729 td->itd_bp[0] = htohc32(sc, 2730 EHCI_ITD_SET_ADDR(xfer->address) | 2731 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno))); 2732 2733 temp = 2734 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2735 2736 /* set direction */ 2737 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 2738 temp |= EHCI_ITD_SET_DIR_IN; 2739 } 2740 /* set maximum packet size */ 2741 td->itd_bp[1] = htohc32(sc, temp); 2742 2743 /* set transfer multiplier */ 2744 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3); 2745 2746 usb_pc_cpu_flush(td->page_cache); 2747 } 2748 } 2749} 2750 2751static void 2752ehci_device_isoc_hs_close(struct usb_xfer *xfer) 2753{ 2754 ehci_device_done(xfer, USB_ERR_CANCELLED); 2755 2756 /* bandwidth must be freed after device done */ 2757 usb_hs_bandwidth_free(xfer); 2758} 2759 2760static void 2761ehci_device_isoc_hs_enter(struct usb_xfer *xfer) 2762{ 2763 struct usb_page_search buf_res; 2764 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2765 ehci_itd_t *td; 2766 ehci_itd_t *td_last = NULL; 2767 ehci_itd_t **pp_last; 2768 bus_size_t page_addr; 2769 uint32_t *plen; 2770 uint32_t status; 2771 uint32_t buf_offset; 2772 uint32_t nframes; 2773 uint32_t itd_offset[8 + 1]; 2774 uint8_t x; 2775 uint8_t td_no; 2776 uint8_t page_no; 2777 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 2778 2779#ifdef USB_DEBUG 2780 uint8_t once = 1; 2781 2782#endif 2783 2784 DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n", 2785 xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift); 2786 2787 /* get the current frame index */ 2788 2789 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2790 2791 /* 2792 * check if the frame index is within the window where the frames 2793 * will be inserted 2794 */ 2795 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2796 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2797 2798 if ((xfer->endpoint->is_synced == 0) || 2799 (buf_offset < (((xfer->nframes << shift) + 7) / 8))) { 2800 /* 2801 * If there is data underflow or the pipe queue is empty we 2802 * schedule the transfer a few frames ahead of the current 2803 * frame position. Else two isochronous transfers might 2804 * overlap. 2805 */ 2806 xfer->endpoint->isoc_next = (nframes + 3) & 2807 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2808 xfer->endpoint->is_synced = 1; 2809 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2810 } 2811 /* 2812 * compute how many milliseconds the insertion is ahead of the 2813 * current frame position: 2814 */ 2815 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2816 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2817 2818 /* 2819 * pre-compute when the isochronous transfer will be finished: 2820 */ 2821 xfer->isoc_time_complete = 2822 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2823 (((xfer->nframes << shift) + 7) / 8); 2824 2825 /* get the real number of frames */ 2826 2827 nframes = xfer->nframes; 2828 2829 buf_offset = 0; 2830 td_no = 0; 2831 2832 plen = xfer->frlengths; 2833 2834 /* toggle the DMA set we are using */ 2835 xfer->flags_int.curr_dma_set ^= 1; 2836 2837 /* get next DMA set */ 2838 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2839 xfer->td_transfer_first = td; 2840 2841 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next]; 2842 2843 /* store starting position */ 2844 2845 xfer->qh_pos = xfer->endpoint->isoc_next; 2846 2847 while (nframes) { 2848 if (td == NULL) { 2849 panic("%s:%d: out of TD's\n", 2850 __FUNCTION__, __LINE__); 2851 } 2852 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2853 pp_last = &sc->sc_isoc_hs_p_last[0]; 2854 } 2855 /* range check */ 2856 if (*plen > xfer->max_frame_size) { 2857#ifdef USB_DEBUG 2858 if (once) { 2859 once = 0; 2860 printf("%s: frame length(%d) exceeds %d bytes " 2861 "(frame truncated)\n", 2862 __FUNCTION__, *plen, xfer->max_frame_size); 2863 } 2864#endif 2865 *plen = xfer->max_frame_size; 2866 } 2867 2868 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2869 status = (EHCI_ITD_SET_LEN(*plen) | 2870 EHCI_ITD_ACTIVE | 2871 EHCI_ITD_SET_PG(0)); 2872 td->itd_status[td_no] = htohc32(sc, status); 2873 itd_offset[td_no] = buf_offset; 2874 buf_offset += *plen; 2875 plen++; 2876 nframes --; 2877 } else { 2878 td->itd_status[td_no] = 0; /* not active */ 2879 itd_offset[td_no] = buf_offset; 2880 } 2881 2882 td_no++; 2883 2884 if ((td_no == 8) || (nframes == 0)) { 2885 2886 /* the rest of the transfers are not active, if any */ 2887 for (x = td_no; x != 8; x++) { 2888 td->itd_status[x] = 0; /* not active */ 2889 } 2890 2891 /* check if there is any data to be transferred */ 2892 if (itd_offset[0] != buf_offset) { 2893 page_no = 0; 2894 itd_offset[td_no] = buf_offset; 2895 2896 /* get first page offset */ 2897 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2898 /* get page address */ 2899 page_addr = buf_res.physaddr & ~0xFFF; 2900 /* update page address */ 2901 td->itd_bp[0] &= htohc32(sc, 0xFFF); 2902 td->itd_bp[0] |= htohc32(sc, page_addr); 2903 2904 for (x = 0; x != td_no; x++) { 2905 /* set page number and page offset */ 2906 status = (EHCI_ITD_SET_PG(page_no) | 2907 (buf_res.physaddr & 0xFFF)); 2908 td->itd_status[x] |= htohc32(sc, status); 2909 2910 /* get next page offset */ 2911 if (itd_offset[x + 1] == buf_offset) { 2912 /* 2913 * We subtract one so that 2914 * we don't go off the last 2915 * page! 2916 */ 2917 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2918 } else { 2919 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2920 } 2921 2922 /* check if we need a new page */ 2923 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2924 /* new page needed */ 2925 page_addr = buf_res.physaddr & ~0xFFF; 2926 if (page_no == 6) { 2927 panic("%s: too many pages\n", __FUNCTION__); 2928 } 2929 page_no++; 2930 /* update page address */ 2931 td->itd_bp[page_no] &= htohc32(sc, 0xFFF); 2932 td->itd_bp[page_no] |= htohc32(sc, page_addr); 2933 } 2934 } 2935 } 2936 /* set IOC bit if we are complete */ 2937 if (nframes == 0) { 2938 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC); 2939 } 2940 usb_pc_cpu_flush(td->page_cache); 2941#ifdef USB_DEBUG 2942 if (ehcidebug > 15) { 2943 DPRINTF("HS-TD %d\n", nframes); 2944 ehci_dump_itd(sc, td); 2945 } 2946#endif 2947 /* insert TD into schedule */ 2948 EHCI_APPEND_HS_TD(td, *pp_last); 2949 pp_last++; 2950 2951 td_no = 0; 2952 td_last = td; 2953 td = td->obj_next; 2954 } 2955 } 2956 2957 xfer->td_transfer_last = td_last; 2958 2959 /* update isoc_next */ 2960 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 2961 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2962} 2963 2964static void 2965ehci_device_isoc_hs_start(struct usb_xfer *xfer) 2966{ 2967 /* put transfer on interrupt queue */ 2968 ehci_transfer_intr_enqueue(xfer); 2969} 2970 2971static const struct usb_pipe_methods ehci_device_isoc_hs_methods = 2972{ 2973 .open = ehci_device_isoc_hs_open, 2974 .close = ehci_device_isoc_hs_close, 2975 .enter = ehci_device_isoc_hs_enter, 2976 .start = ehci_device_isoc_hs_start, 2977}; 2978 2979/*------------------------------------------------------------------------* 2980 * ehci root control support 2981 *------------------------------------------------------------------------* 2982 * Simulate a hardware hub by handling all the necessary requests. 2983 *------------------------------------------------------------------------*/ 2984 2985static const 2986struct usb_device_descriptor ehci_devd = 2987{ 2988 sizeof(struct usb_device_descriptor), 2989 UDESC_DEVICE, /* type */ 2990 {0x00, 0x02}, /* USB version */ 2991 UDCLASS_HUB, /* class */ 2992 UDSUBCLASS_HUB, /* subclass */ 2993 UDPROTO_HSHUBSTT, /* protocol */ 2994 64, /* max packet */ 2995 {0}, {0}, {0x00, 0x01}, /* device id */ 2996 1, 2, 0, /* string indexes */ 2997 1 /* # of configurations */ 2998}; 2999 3000static const 3001struct usb_device_qualifier ehci_odevd = 3002{ 3003 sizeof(struct usb_device_qualifier), 3004 UDESC_DEVICE_QUALIFIER, /* type */ 3005 {0x00, 0x02}, /* USB version */ 3006 UDCLASS_HUB, /* class */ 3007 UDSUBCLASS_HUB, /* subclass */ 3008 UDPROTO_FSHUB, /* protocol */ 3009 0, /* max packet */ 3010 0, /* # of configurations */ 3011 0 3012}; 3013 3014static const struct ehci_config_desc ehci_confd = { 3015 .confd = { 3016 .bLength = sizeof(struct usb_config_descriptor), 3017 .bDescriptorType = UDESC_CONFIG, 3018 .wTotalLength[0] = sizeof(ehci_confd), 3019 .bNumInterface = 1, 3020 .bConfigurationValue = 1, 3021 .iConfiguration = 0, 3022 .bmAttributes = UC_SELF_POWERED, 3023 .bMaxPower = 0 /* max power */ 3024 }, 3025 .ifcd = { 3026 .bLength = sizeof(struct usb_interface_descriptor), 3027 .bDescriptorType = UDESC_INTERFACE, 3028 .bNumEndpoints = 1, 3029 .bInterfaceClass = UICLASS_HUB, 3030 .bInterfaceSubClass = UISUBCLASS_HUB, 3031 .bInterfaceProtocol = 0, 3032 }, 3033 .endpd = { 3034 .bLength = sizeof(struct usb_endpoint_descriptor), 3035 .bDescriptorType = UDESC_ENDPOINT, 3036 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 3037 .bmAttributes = UE_INTERRUPT, 3038 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 3039 .bInterval = 255, 3040 }, 3041}; 3042 3043static const 3044struct usb_hub_descriptor ehci_hubd = 3045{ 3046 .bDescLength = 0, /* dynamic length */ 3047 .bDescriptorType = UDESC_HUB, 3048}; 3049 3050uint16_t 3051ehci_get_port_speed_portsc(struct ehci_softc *sc, uint16_t index) 3052{ 3053 uint32_t v; 3054 3055 v = EOREAD4(sc, EHCI_PORTSC(index)); 3056 v = (v >> EHCI_PORTSC_PSPD_SHIFT) & EHCI_PORTSC_PSPD_MASK; 3057 3058 if (v == EHCI_PORT_SPEED_HIGH) 3059 return (UPS_HIGH_SPEED); 3060 if (v == EHCI_PORT_SPEED_LOW) 3061 return (UPS_LOW_SPEED); 3062 return (0); 3063} 3064 3065uint16_t 3066ehci_get_port_speed_hostc(struct ehci_softc *sc, uint16_t index) 3067{ 3068 uint32_t v; 3069 3070 v = EOREAD4(sc, EHCI_HOSTC(index)); 3071 v = (v >> EHCI_HOSTC_PSPD_SHIFT) & EHCI_HOSTC_PSPD_MASK; 3072 3073 if (v == EHCI_PORT_SPEED_HIGH) 3074 return (UPS_HIGH_SPEED); 3075 if (v == EHCI_PORT_SPEED_LOW) 3076 return (UPS_LOW_SPEED); 3077 return (0); 3078} 3079 3080static void 3081ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed) 3082{ 3083 uint32_t port; 3084 uint32_t v; 3085 3086 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed); 3087 3088 port = EHCI_PORTSC(index); 3089 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3090 EOWRITE4(sc, port, v | EHCI_PS_PO); 3091} 3092 3093static usb_error_t 3094ehci_roothub_exec(struct usb_device *udev, 3095 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3096{ 3097 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3098 const char *str_ptr; 3099 const void *ptr; 3100 uint32_t port; 3101 uint32_t v; 3102 uint16_t len; 3103 uint16_t i; 3104 uint16_t value; 3105 uint16_t index; 3106 usb_error_t err; 3107 3108 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3109 3110 /* buffer reset */ 3111 ptr = (const void *)&sc->sc_hub_desc; 3112 len = 0; 3113 err = 0; 3114 3115 value = UGETW(req->wValue); 3116 index = UGETW(req->wIndex); 3117 3118 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3119 "wValue=0x%04x wIndex=0x%04x\n", 3120 req->bmRequestType, req->bRequest, 3121 UGETW(req->wLength), value, index); 3122 3123#define C(x,y) ((x) | ((y) << 8)) 3124 switch (C(req->bRequest, req->bmRequestType)) { 3125 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3126 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3127 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3128 /* 3129 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3130 * for the integrated root hub. 3131 */ 3132 break; 3133 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3134 len = 1; 3135 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3136 break; 3137 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3138 switch (value >> 8) { 3139 case UDESC_DEVICE: 3140 if ((value & 0xff) != 0) { 3141 err = USB_ERR_IOERROR; 3142 goto done; 3143 } 3144 len = sizeof(ehci_devd); 3145 ptr = (const void *)&ehci_devd; 3146 break; 3147 /* 3148 * We can't really operate at another speed, 3149 * but the specification says we need this 3150 * descriptor: 3151 */ 3152 case UDESC_DEVICE_QUALIFIER: 3153 if ((value & 0xff) != 0) { 3154 err = USB_ERR_IOERROR; 3155 goto done; 3156 } 3157 len = sizeof(ehci_odevd); 3158 ptr = (const void *)&ehci_odevd; 3159 break; 3160 3161 case UDESC_CONFIG: 3162 if ((value & 0xff) != 0) { 3163 err = USB_ERR_IOERROR; 3164 goto done; 3165 } 3166 len = sizeof(ehci_confd); 3167 ptr = (const void *)&ehci_confd; 3168 break; 3169 3170 case UDESC_STRING: 3171 switch (value & 0xff) { 3172 case 0: /* Language table */ 3173 str_ptr = "\001"; 3174 break; 3175 3176 case 1: /* Vendor */ 3177 str_ptr = sc->sc_vendor; 3178 break; 3179 3180 case 2: /* Product */ 3181 str_ptr = "EHCI root HUB"; 3182 break; 3183 3184 default: 3185 str_ptr = ""; 3186 break; 3187 } 3188 3189 len = usb_make_str_desc( 3190 sc->sc_hub_desc.temp, 3191 sizeof(sc->sc_hub_desc.temp), 3192 str_ptr); 3193 break; 3194 default: 3195 err = USB_ERR_IOERROR; 3196 goto done; 3197 } 3198 break; 3199 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3200 len = 1; 3201 sc->sc_hub_desc.temp[0] = 0; 3202 break; 3203 case C(UR_GET_STATUS, UT_READ_DEVICE): 3204 len = 2; 3205 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3206 break; 3207 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3208 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3209 len = 2; 3210 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3211 break; 3212 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3213 if (value >= EHCI_MAX_DEVICES) { 3214 err = USB_ERR_IOERROR; 3215 goto done; 3216 } 3217 sc->sc_addr = value; 3218 break; 3219 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3220 if ((value != 0) && (value != 1)) { 3221 err = USB_ERR_IOERROR; 3222 goto done; 3223 } 3224 sc->sc_conf = value; 3225 break; 3226 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3227 break; 3228 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3229 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3230 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3231 err = USB_ERR_IOERROR; 3232 goto done; 3233 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3234 break; 3235 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3236 break; 3237 /* Hub requests */ 3238 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3239 break; 3240 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3241 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3242 3243 if ((index < 1) || 3244 (index > sc->sc_noport)) { 3245 err = USB_ERR_IOERROR; 3246 goto done; 3247 } 3248 port = EHCI_PORTSC(index); 3249 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3250 switch (value) { 3251 case UHF_PORT_ENABLE: 3252 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3253 break; 3254 case UHF_PORT_SUSPEND: 3255 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) { 3256 3257 /* 3258 * waking up a High Speed device is rather 3259 * complicated if 3260 */ 3261 EOWRITE4(sc, port, v | EHCI_PS_FPR); 3262 } 3263 /* wait 20ms for resume sequence to complete */ 3264 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3265 3266 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP | 3267 EHCI_PS_FPR | (3 << 10) /* High Speed */ )); 3268 3269 /* 4ms settle time */ 3270 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3271 break; 3272 case UHF_PORT_POWER: 3273 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3274 break; 3275 case UHF_PORT_TEST: 3276 DPRINTFN(3, "clear port test " 3277 "%d\n", index); 3278 break; 3279 case UHF_PORT_INDICATOR: 3280 DPRINTFN(3, "clear port ind " 3281 "%d\n", index); 3282 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3283 break; 3284 case UHF_C_PORT_CONNECTION: 3285 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3286 break; 3287 case UHF_C_PORT_ENABLE: 3288 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3289 break; 3290 case UHF_C_PORT_SUSPEND: 3291 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3292 break; 3293 case UHF_C_PORT_OVER_CURRENT: 3294 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3295 break; 3296 case UHF_C_PORT_RESET: 3297 sc->sc_isreset = 0; 3298 break; 3299 default: 3300 err = USB_ERR_IOERROR; 3301 goto done; 3302 } 3303 break; 3304 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3305 if ((value & 0xff) != 0) { 3306 err = USB_ERR_IOERROR; 3307 goto done; 3308 } 3309 v = EREAD4(sc, EHCI_HCSPARAMS); 3310 3311 sc->sc_hub_desc.hubd = ehci_hubd; 3312 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3313 3314 if (EHCI_HCS_PPC(v)) 3315 i = UHD_PWR_INDIVIDUAL; 3316 else 3317 i = UHD_PWR_NO_SWITCH; 3318 3319 if (EHCI_HCS_P_INDICATOR(v)) 3320 i |= UHD_PORT_IND; 3321 3322 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3323 /* XXX can't find out? */ 3324 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; 3325 /* XXX don't know if ports are removable or not */ 3326 sc->sc_hub_desc.hubd.bDescLength = 3327 8 + ((sc->sc_noport + 7) / 8); 3328 len = sc->sc_hub_desc.hubd.bDescLength; 3329 break; 3330 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3331 len = 16; 3332 memset(sc->sc_hub_desc.temp, 0, 16); 3333 break; 3334 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3335 DPRINTFN(9, "get port status i=%d\n", 3336 index); 3337 if ((index < 1) || 3338 (index > sc->sc_noport)) { 3339 err = USB_ERR_IOERROR; 3340 goto done; 3341 } 3342 v = EOREAD4(sc, EHCI_PORTSC(index)); 3343 DPRINTFN(9, "port status=0x%04x\n", v); 3344 if (sc->sc_flags & EHCI_SCFLG_TT) { 3345 if (sc->sc_vendor_get_port_speed != NULL) { 3346 i = sc->sc_vendor_get_port_speed(sc, index); 3347 } else { 3348 device_printf(sc->sc_bus.bdev, 3349 "EHCI_SCFLG_TT quirk is set but " 3350 "sc_vendor_get_hub_speed() is NULL\n"); 3351 i = UPS_HIGH_SPEED; 3352 } 3353 } else { 3354 i = UPS_HIGH_SPEED; 3355 } 3356 if (v & EHCI_PS_CS) 3357 i |= UPS_CURRENT_CONNECT_STATUS; 3358 if (v & EHCI_PS_PE) 3359 i |= UPS_PORT_ENABLED; 3360 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR)) 3361 i |= UPS_SUSPEND; 3362 if (v & EHCI_PS_OCA) 3363 i |= UPS_OVERCURRENT_INDICATOR; 3364 if (v & EHCI_PS_PR) 3365 i |= UPS_RESET; 3366 if (v & EHCI_PS_PP) 3367 i |= UPS_PORT_POWER; 3368 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3369 i = 0; 3370 if (v & EHCI_PS_CSC) 3371 i |= UPS_C_CONNECT_STATUS; 3372 if (v & EHCI_PS_PEC) 3373 i |= UPS_C_PORT_ENABLED; 3374 if (v & EHCI_PS_OCC) 3375 i |= UPS_C_OVERCURRENT_INDICATOR; 3376 if (v & EHCI_PS_FPR) 3377 i |= UPS_C_SUSPEND; 3378 if (sc->sc_isreset) 3379 i |= UPS_C_PORT_RESET; 3380 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3381 len = sizeof(sc->sc_hub_desc.ps); 3382 break; 3383 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3384 err = USB_ERR_IOERROR; 3385 goto done; 3386 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3387 break; 3388 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3389 if ((index < 1) || 3390 (index > sc->sc_noport)) { 3391 err = USB_ERR_IOERROR; 3392 goto done; 3393 } 3394 port = EHCI_PORTSC(index); 3395 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3396 switch (value) { 3397 case UHF_PORT_ENABLE: 3398 EOWRITE4(sc, port, v | EHCI_PS_PE); 3399 break; 3400 case UHF_PORT_SUSPEND: 3401 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3402 break; 3403 case UHF_PORT_RESET: 3404 DPRINTFN(6, "reset port %d\n", index); 3405#ifdef USB_DEBUG 3406 if (ehcinohighspeed) { 3407 /* 3408 * Connect USB device to companion 3409 * controller. 3410 */ 3411 ehci_disown(sc, index, 1); 3412 break; 3413 } 3414#endif 3415 if (EHCI_PS_IS_LOWSPEED(v) && 3416 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3417 /* Low speed device, give up ownership. */ 3418 ehci_disown(sc, index, 1); 3419 break; 3420 } 3421 /* Start reset sequence. */ 3422 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3423 EOWRITE4(sc, port, v | EHCI_PS_PR); 3424 3425 /* Wait for reset to complete. */ 3426 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3427 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 3428 3429 /* Terminate reset sequence. */ 3430 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3431 EOWRITE4(sc, port, v); 3432 3433 /* Wait for HC to complete reset. */ 3434 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3435 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE)); 3436 3437 v = EOREAD4(sc, port); 3438 DPRINTF("ehci after reset, status=0x%08x\n", v); 3439 if (v & EHCI_PS_PR) { 3440 device_printf(sc->sc_bus.bdev, 3441 "port reset timeout\n"); 3442 err = USB_ERR_TIMEOUT; 3443 goto done; 3444 } 3445 if (!(v & EHCI_PS_PE) && 3446 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3447 /* Not a high speed device, give up ownership.*/ 3448 ehci_disown(sc, index, 0); 3449 break; 3450 } 3451 sc->sc_isreset = 1; 3452 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3453 index, v); 3454 break; 3455 3456 case UHF_PORT_POWER: 3457 DPRINTFN(3, "set port power %d\n", index); 3458 EOWRITE4(sc, port, v | EHCI_PS_PP); 3459 break; 3460 3461 case UHF_PORT_TEST: 3462 DPRINTFN(3, "set port test %d\n", index); 3463 break; 3464 3465 case UHF_PORT_INDICATOR: 3466 DPRINTFN(3, "set port ind %d\n", index); 3467 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3468 break; 3469 3470 default: 3471 err = USB_ERR_IOERROR; 3472 goto done; 3473 } 3474 break; 3475 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3476 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3477 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3478 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3479 break; 3480 default: 3481 err = USB_ERR_IOERROR; 3482 goto done; 3483 } 3484done: 3485 *plength = len; 3486 *pptr = ptr; 3487 return (err); 3488} 3489 3490static void 3491ehci_xfer_setup(struct usb_setup_params *parm) 3492{ 3493 struct usb_page_search page_info; 3494 struct usb_page_cache *pc; 3495 ehci_softc_t *sc; 3496 struct usb_xfer *xfer; 3497 void *last_obj; 3498 uint32_t nqtd; 3499 uint32_t nqh; 3500 uint32_t nsitd; 3501 uint32_t nitd; 3502 uint32_t n; 3503 3504 sc = EHCI_BUS2SC(parm->udev->bus); 3505 xfer = parm->curr_xfer; 3506 3507 nqtd = 0; 3508 nqh = 0; 3509 nsitd = 0; 3510 nitd = 0; 3511 3512 /* 3513 * compute maximum number of some structures 3514 */ 3515 if (parm->methods == &ehci_device_ctrl_methods) { 3516 3517 /* 3518 * The proof for the "nqtd" formula is illustrated like 3519 * this: 3520 * 3521 * +------------------------------------+ 3522 * | | 3523 * | |remainder -> | 3524 * | +-----+---+ | 3525 * | | xxx | x | frm 0 | 3526 * | +-----+---++ | 3527 * | | xxx | xx | frm 1 | 3528 * | +-----+----+ | 3529 * | ... | 3530 * +------------------------------------+ 3531 * 3532 * "xxx" means a completely full USB transfer descriptor 3533 * 3534 * "x" and "xx" means a short USB packet 3535 * 3536 * For the remainder of an USB transfer modulo 3537 * "max_data_length" we need two USB transfer descriptors. 3538 * One to transfer the remaining data and one to finalise 3539 * with a zero length packet in case the "force_short_xfer" 3540 * flag is set. We only need two USB transfer descriptors in 3541 * the case where the transfer length of the first one is a 3542 * factor of "max_frame_size". The rest of the needed USB 3543 * transfer descriptors is given by the buffer size divided 3544 * by the maximum data payload. 3545 */ 3546 parm->hc_max_packet_size = 0x400; 3547 parm->hc_max_packet_count = 1; 3548 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3549 xfer->flags_int.bdma_enable = 1; 3550 3551 usbd_transfer_setup_sub(parm); 3552 3553 nqh = 1; 3554 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3555 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3556 3557 } else if (parm->methods == &ehci_device_bulk_methods) { 3558 3559 parm->hc_max_packet_size = 0x400; 3560 parm->hc_max_packet_count = 1; 3561 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3562 xfer->flags_int.bdma_enable = 1; 3563 3564 usbd_transfer_setup_sub(parm); 3565 3566 nqh = 1; 3567 nqtd = ((2 * xfer->nframes) 3568 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3569 3570 } else if (parm->methods == &ehci_device_intr_methods) { 3571 3572 if (parm->speed == USB_SPEED_HIGH) { 3573 parm->hc_max_packet_size = 0x400; 3574 parm->hc_max_packet_count = 3; 3575 } else if (parm->speed == USB_SPEED_FULL) { 3576 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3577 parm->hc_max_packet_count = 1; 3578 } else { 3579 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3580 parm->hc_max_packet_count = 1; 3581 } 3582 3583 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3584 xfer->flags_int.bdma_enable = 1; 3585 3586 usbd_transfer_setup_sub(parm); 3587 3588 nqh = 1; 3589 nqtd = ((2 * xfer->nframes) 3590 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3591 3592 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3593 3594 parm->hc_max_packet_size = 0x3FF; 3595 parm->hc_max_packet_count = 1; 3596 parm->hc_max_frame_size = 0x3FF; 3597 xfer->flags_int.bdma_enable = 1; 3598 3599 usbd_transfer_setup_sub(parm); 3600 3601 nsitd = xfer->nframes; 3602 3603 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3604 3605 parm->hc_max_packet_size = 0x400; 3606 parm->hc_max_packet_count = 3; 3607 parm->hc_max_frame_size = 0xC00; 3608 xfer->flags_int.bdma_enable = 1; 3609 3610 usbd_transfer_setup_sub(parm); 3611 3612 nitd = ((xfer->nframes + 7) / 8) << 3613 usbd_xfer_get_fps_shift(xfer); 3614 3615 } else { 3616 3617 parm->hc_max_packet_size = 0x400; 3618 parm->hc_max_packet_count = 1; 3619 parm->hc_max_frame_size = 0x400; 3620 3621 usbd_transfer_setup_sub(parm); 3622 } 3623 3624alloc_dma_set: 3625 3626 if (parm->err) { 3627 return; 3628 } 3629 /* 3630 * Allocate queue heads and transfer descriptors 3631 */ 3632 last_obj = NULL; 3633 3634 if (usbd_transfer_setup_sub_malloc( 3635 parm, &pc, sizeof(ehci_itd_t), 3636 EHCI_ITD_ALIGN, nitd)) { 3637 parm->err = USB_ERR_NOMEM; 3638 return; 3639 } 3640 if (parm->buf) { 3641 for (n = 0; n != nitd; n++) { 3642 ehci_itd_t *td; 3643 3644 usbd_get_page(pc + n, 0, &page_info); 3645 3646 td = page_info.buffer; 3647 3648 /* init TD */ 3649 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD); 3650 td->obj_next = last_obj; 3651 td->page_cache = pc + n; 3652 3653 last_obj = td; 3654 3655 usb_pc_cpu_flush(pc + n); 3656 } 3657 } 3658 if (usbd_transfer_setup_sub_malloc( 3659 parm, &pc, sizeof(ehci_sitd_t), 3660 EHCI_SITD_ALIGN, nsitd)) { 3661 parm->err = USB_ERR_NOMEM; 3662 return; 3663 } 3664 if (parm->buf) { 3665 for (n = 0; n != nsitd; n++) { 3666 ehci_sitd_t *td; 3667 3668 usbd_get_page(pc + n, 0, &page_info); 3669 3670 td = page_info.buffer; 3671 3672 /* init TD */ 3673 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD); 3674 td->obj_next = last_obj; 3675 td->page_cache = pc + n; 3676 3677 last_obj = td; 3678 3679 usb_pc_cpu_flush(pc + n); 3680 } 3681 } 3682 if (usbd_transfer_setup_sub_malloc( 3683 parm, &pc, sizeof(ehci_qtd_t), 3684 EHCI_QTD_ALIGN, nqtd)) { 3685 parm->err = USB_ERR_NOMEM; 3686 return; 3687 } 3688 if (parm->buf) { 3689 for (n = 0; n != nqtd; n++) { 3690 ehci_qtd_t *qtd; 3691 3692 usbd_get_page(pc + n, 0, &page_info); 3693 3694 qtd = page_info.buffer; 3695 3696 /* init TD */ 3697 qtd->qtd_self = htohc32(sc, page_info.physaddr); 3698 qtd->obj_next = last_obj; 3699 qtd->page_cache = pc + n; 3700 3701 last_obj = qtd; 3702 3703 usb_pc_cpu_flush(pc + n); 3704 } 3705 } 3706 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3707 3708 last_obj = NULL; 3709 3710 if (usbd_transfer_setup_sub_malloc( 3711 parm, &pc, sizeof(ehci_qh_t), 3712 EHCI_QH_ALIGN, nqh)) { 3713 parm->err = USB_ERR_NOMEM; 3714 return; 3715 } 3716 if (parm->buf) { 3717 for (n = 0; n != nqh; n++) { 3718 ehci_qh_t *qh; 3719 3720 usbd_get_page(pc + n, 0, &page_info); 3721 3722 qh = page_info.buffer; 3723 3724 /* init QH */ 3725 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH); 3726 qh->obj_next = last_obj; 3727 qh->page_cache = pc + n; 3728 3729 last_obj = qh; 3730 3731 usb_pc_cpu_flush(pc + n); 3732 } 3733 } 3734 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3735 3736 if (!xfer->flags_int.curr_dma_set) { 3737 xfer->flags_int.curr_dma_set = 1; 3738 goto alloc_dma_set; 3739 } 3740} 3741 3742static void 3743ehci_xfer_unsetup(struct usb_xfer *xfer) 3744{ 3745 return; 3746} 3747 3748static void 3749ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3750 struct usb_endpoint *ep) 3751{ 3752 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3753 3754 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3755 ep, udev->address, 3756 edesc->bEndpointAddress, udev->flags.usb_mode, 3757 sc->sc_addr); 3758 3759 if (udev->device_index != sc->sc_addr) { 3760 3761 if ((udev->speed != USB_SPEED_HIGH) && 3762 ((udev->hs_hub_addr == 0) || 3763 (udev->hs_port_no == 0) || 3764 (udev->parent_hs_hub == NULL) || 3765 (udev->parent_hs_hub->hub == NULL))) { 3766 /* We need a transaction translator */ 3767 goto done; 3768 } 3769 switch (edesc->bmAttributes & UE_XFERTYPE) { 3770 case UE_CONTROL: 3771 ep->methods = &ehci_device_ctrl_methods; 3772 break; 3773 case UE_INTERRUPT: 3774 ep->methods = &ehci_device_intr_methods; 3775 break; 3776 case UE_ISOCHRONOUS: 3777 if (udev->speed == USB_SPEED_HIGH) { 3778 ep->methods = &ehci_device_isoc_hs_methods; 3779 } else if (udev->speed == USB_SPEED_FULL) { 3780 ep->methods = &ehci_device_isoc_fs_methods; 3781 } 3782 break; 3783 case UE_BULK: 3784 ep->methods = &ehci_device_bulk_methods; 3785 break; 3786 default: 3787 /* do nothing */ 3788 break; 3789 } 3790 } 3791done: 3792 return; 3793} 3794 3795static void 3796ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3797{ 3798 /* 3799 * Wait until the hardware has finished any possible use of 3800 * the transfer descriptor(s) and QH 3801 */ 3802 *pus = (1125); /* microseconds */ 3803} 3804 3805static void 3806ehci_device_resume(struct usb_device *udev) 3807{ 3808 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3809 struct usb_xfer *xfer; 3810 const struct usb_pipe_methods *methods; 3811 3812 DPRINTF("\n"); 3813 3814 USB_BUS_LOCK(udev->bus); 3815 3816 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3817 3818 if (xfer->xroot->udev == udev) { 3819 3820 methods = xfer->endpoint->methods; 3821 3822 if ((methods == &ehci_device_bulk_methods) || 3823 (methods == &ehci_device_ctrl_methods)) { 3824 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3825 sc->sc_async_p_last); 3826 } 3827 if (methods == &ehci_device_intr_methods) { 3828 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3829 sc->sc_intr_p_last[xfer->qh_pos]); 3830 } 3831 } 3832 } 3833 3834 USB_BUS_UNLOCK(udev->bus); 3835 3836 return; 3837} 3838 3839static void 3840ehci_device_suspend(struct usb_device *udev) 3841{ 3842 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3843 struct usb_xfer *xfer; 3844 const struct usb_pipe_methods *methods; 3845 3846 DPRINTF("\n"); 3847 3848 USB_BUS_LOCK(udev->bus); 3849 3850 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3851 3852 if (xfer->xroot->udev == udev) { 3853 3854 methods = xfer->endpoint->methods; 3855 3856 if ((methods == &ehci_device_bulk_methods) || 3857 (methods == &ehci_device_ctrl_methods)) { 3858 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3859 sc->sc_async_p_last); 3860 } 3861 if (methods == &ehci_device_intr_methods) { 3862 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3863 sc->sc_intr_p_last[xfer->qh_pos]); 3864 } 3865 } 3866 } 3867 3868 USB_BUS_UNLOCK(udev->bus); 3869} 3870 3871static void 3872ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3873{ 3874 struct ehci_softc *sc = EHCI_BUS2SC(bus); 3875 3876 switch (state) { 3877 case USB_HW_POWER_SUSPEND: 3878 case USB_HW_POWER_SHUTDOWN: 3879 ehci_suspend(sc); 3880 break; 3881 case USB_HW_POWER_RESUME: 3882 ehci_resume(sc); 3883 break; 3884 default: 3885 break; 3886 } 3887} 3888 3889static void 3890ehci_set_hw_power(struct usb_bus *bus) 3891{ 3892 ehci_softc_t *sc = EHCI_BUS2SC(bus); 3893 uint32_t temp; 3894 uint32_t flags; 3895 3896 DPRINTF("\n"); 3897 3898 USB_BUS_LOCK(bus); 3899 3900 flags = bus->hw_power_state; 3901 3902 temp = EOREAD4(sc, EHCI_USBCMD); 3903 3904 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 3905 3906 if (flags & (USB_HW_POWER_CONTROL | 3907 USB_HW_POWER_BULK)) { 3908 DPRINTF("Async is active\n"); 3909 temp |= EHCI_CMD_ASE; 3910 } 3911 if (flags & (USB_HW_POWER_INTERRUPT | 3912 USB_HW_POWER_ISOC)) { 3913 DPRINTF("Periodic is active\n"); 3914 temp |= EHCI_CMD_PSE; 3915 } 3916 EOWRITE4(sc, EHCI_USBCMD, temp); 3917 3918 USB_BUS_UNLOCK(bus); 3919 3920 return; 3921} 3922 3923static void 3924ehci_start_dma_delay_second(struct usb_xfer *xfer) 3925{ 3926 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus); 3927 3928 DPRINTF("\n"); 3929 3930 /* trigger doorbell */ 3931 ehci_doorbell_async(sc); 3932 3933 /* give the doorbell 4ms */ 3934 usbd_transfer_timeout_ms(xfer, 3935 (void (*)(void *))&usb_dma_delay_done_cb, 4); 3936} 3937 3938/* 3939 * Ring the doorbell twice before freeing any DMA descriptors. Some host 3940 * controllers apparently cache the QH descriptors and need a message 3941 * that the cache needs to be discarded. 3942 */ 3943static void 3944ehci_start_dma_delay(struct usb_xfer *xfer) 3945{ 3946 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus); 3947 3948 DPRINTF("\n"); 3949 3950 /* trigger doorbell */ 3951 ehci_doorbell_async(sc); 3952 3953 /* give the doorbell 4ms */ 3954 usbd_transfer_timeout_ms(xfer, 3955 (void (*)(void *))&ehci_start_dma_delay_second, 4); 3956} 3957 3958static const struct usb_bus_methods ehci_bus_methods = 3959{ 3960 .endpoint_init = ehci_ep_init, 3961 .xfer_setup = ehci_xfer_setup, 3962 .xfer_unsetup = ehci_xfer_unsetup, 3963 .get_dma_delay = ehci_get_dma_delay, 3964 .device_resume = ehci_device_resume, 3965 .device_suspend = ehci_device_suspend, 3966 .set_hw_power = ehci_set_hw_power, 3967 .set_hw_power_sleep = ehci_set_hw_power_sleep, 3968 .roothub_exec = ehci_roothub_exec, 3969 .xfer_poll = ehci_do_poll, 3970 .start_dma_delay = ehci_start_dma_delay, 3971}; 3972