1/* $OpenBSD: if_txpreg.h,v 1.35 2003/06/04 19:36:33 deraadt Exp $ */ 2/* $FreeBSD$ */ 3 4/*- 5 * SPDX-License-Identifier: BSD-2-Clause 6 * 7 * Copyright (c) 2001 Aaron Campbell <aaron@monkey.org>. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 28 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32/* 33 * Typhoon registers. 34 */ 35#define TXP_SRR 0x00 /* soft reset register */ 36#define TXP_ISR 0x04 /* interrupt status register */ 37#define TXP_IER 0x08 /* interrupt enable register */ 38#define TXP_IMR 0x0c /* interrupt mask register */ 39#define TXP_SIR 0x10 /* self interrupt register */ 40#define TXP_H2A_7 0x14 /* host->arm comm 7 */ 41#define TXP_H2A_6 0x18 /* host->arm comm 6 */ 42#define TXP_H2A_5 0x1c /* host->arm comm 5 */ 43#define TXP_H2A_4 0x20 /* host->arm comm 4 */ 44#define TXP_H2A_3 0x24 /* host->arm comm 3 */ 45#define TXP_H2A_2 0x28 /* host->arm comm 2 */ 46#define TXP_H2A_1 0x2c /* host->arm comm 1 */ 47#define TXP_H2A_0 0x30 /* host->arm comm 0 */ 48#define TXP_A2H_3 0x34 /* arm->host comm 3 */ 49#define TXP_A2H_2 0x38 /* arm->host comm 2 */ 50#define TXP_A2H_1 0x3c /* arm->host comm 1 */ 51#define TXP_A2H_0 0x40 /* arm->host comm 0 */ 52 53/* 54 * interrupt bits (IMR, ISR, IER) 55 */ 56#define TXP_INT_RESERVED 0xffff0000 57#define TXP_INT_A2H_7 0x00008000 /* arm->host comm 7 */ 58#define TXP_INT_A2H_6 0x00004000 /* arm->host comm 6 */ 59#define TXP_INT_A2H_5 0x00002000 /* arm->host comm 5 */ 60#define TXP_INT_A2H_4 0x00001000 /* arm->host comm 4 */ 61#define TXP_INT_SELF 0x00000800 /* self interrupt */ 62#define TXP_INT_PCI_TABORT 0x00000400 /* pci target abort */ 63#define TXP_INT_PCI_MABORT 0x00000200 /* pci master abort */ 64#define TXP_INT_DMA3 0x00000100 /* dma3 done */ 65#define TXP_INT_DMA2 0x00000080 /* dma2 done */ 66#define TXP_INT_DMA1 0x00000040 /* dma1 done */ 67#define TXP_INT_DMA0 0x00000020 /* dma0 done */ 68#define TXP_INT_A2H_3 0x00000010 /* arm->host comm 3 */ 69#define TXP_INT_A2H_2 0x00000008 /* arm->host comm 2 */ 70#define TXP_INT_A2H_1 0x00000004 /* arm->host comm 1 */ 71#define TXP_INT_A2H_0 0x00000002 /* arm->host comm 0 */ 72#define TXP_INT_LATCH 0x00000001 /* interrupt latch */ 73 74/* 75 * Controller periodically generates TXP_INT_A2H_3 interrupt so 76 * we don't want to see them in interrupt handler. 77 */ 78#define TXP_INTRS 0xFFFFFFEF 79#define TXP_INTR_ALL 0xFFFFFFFF 80#define TXP_INTR_NONE 0x00000000 81 82/* 83 * soft reset register (SRR) 84 */ 85#define TXP_SRR_ALL 0x0000007f /* full reset */ 86 87/* 88 * Typhoon boot commands. 89 */ 90#define TXP_BOOTCMD_NULL 0x00 91#define TXP_BOOTCMD_WAKEUP 0xfa 92#define TXP_BOOTCMD_DOWNLOAD_COMPLETE 0xfb 93#define TXP_BOOTCMD_SEGMENT_AVAILABLE 0xfc 94#define TXP_BOOTCMD_RUNTIME_IMAGE 0xfd 95#define TXP_BOOTCMD_REGISTER_BOOT_RECORD 0xff 96 97/* 98 * Typhoon runtime commands. 99 */ 100#define TXP_CMD_GLOBAL_RESET 0x00 101#define TXP_CMD_TX_ENABLE 0x01 102#define TXP_CMD_TX_DISABLE 0x02 103#define TXP_CMD_RX_ENABLE 0x03 104#define TXP_CMD_RX_DISABLE 0x04 105#define TXP_CMD_RX_FILTER_WRITE 0x05 106#define TXP_CMD_RX_FILTER_READ 0x06 107#define TXP_CMD_READ_STATISTICS 0x07 108#define TXP_CMD_CYCLE_STATISTICS 0x08 109#define TXP_CMD_CLEAR_STATISTICS 0x09 110#define TXP_CMD_MEMORY_READ 0x0a 111#define TXP_CMD_MEMORY_WRITE_SINGLE 0x0b 112#define TXP_CMD_VARIABLE_SECTION_READ 0x0c 113#define TXP_CMD_VARIABLE_SECTION_WRITE 0x0d 114#define TXP_CMD_STATIC_SECTION_READ 0x0e 115#define TXP_CMD_STATIC_SECTION_WRITE 0x0f 116#define TXP_CMD_IMAGE_SECTION_PROGRAM 0x10 117#define TXP_CMD_NVRAM_PAGE_READ 0x11 118#define TXP_CMD_NVRAM_PAGE_WRITE 0x12 119#define TXP_CMD_XCVR_SELECT 0x13 120#define TXP_CMD_TEST_MUX 0x14 121#define TXP_CMD_PHYLOOPBACK_ENABLE 0x15 122#define TXP_CMD_PHYLOOPBACK_DISABLE 0x16 123#define TXP_CMD_MAC_CONTROL_READ 0x17 124#define TXP_CMD_MAC_CONTROL_WRITE 0x18 125#define TXP_CMD_MAX_PKT_SIZE_READ 0x19 126#define TXP_CMD_MAX_PKT_SIZE_WRITE 0x1a 127#define TXP_CMD_MEDIA_STATUS_READ 0x1b 128#define TXP_CMD_MEDIA_STATUS_WRITE 0x1c 129#define TXP_CMD_NETWORK_DIAGS_READ 0x1d 130#define TXP_CMD_NETWORK_DIAGS_WRITE 0x1e 131#define TXP_CMD_PHY_MGMT_READ 0x1f 132#define TXP_CMD_PHY_MGMT_WRITE 0x20 133#define TXP_CMD_VARIABLE_PARAMETER_READ 0x21 134#define TXP_CMD_VARIABLE_PARAMETER_WRITE 0x22 135#define TXP_CMD_GOTO_SLEEP 0x23 136#define TXP_CMD_FIREWALL_CONTROL 0x24 137#define TXP_CMD_MCAST_HASH_MASK_WRITE 0x25 138#define TXP_CMD_STATION_ADDRESS_WRITE 0x26 139#define TXP_CMD_STATION_ADDRESS_READ 0x27 140#define TXP_CMD_STATION_MASK_WRITE 0x28 141#define TXP_CMD_STATION_MASK_READ 0x29 142#define TXP_CMD_VLAN_ETHER_TYPE_READ 0x2a 143#define TXP_CMD_VLAN_ETHER_TYPE_WRITE 0x2b 144#define TXP_CMD_VLAN_MASK_READ 0x2c 145#define TXP_CMD_VLAN_MASK_WRITE 0x2d 146#define TXP_CMD_BCAST_THROTTLE_WRITE 0x2e 147#define TXP_CMD_BCAST_THROTTLE_READ 0x2f 148#define TXP_CMD_DHCP_PREVENT_WRITE 0x30 149#define TXP_CMD_DHCP_PREVENT_READ 0x31 150#define TXP_CMD_RECV_BUFFER_CONTROL 0x32 151#define TXP_CMD_SOFTWARE_RESET 0x33 152#define TXP_CMD_CREATE_SA 0x34 153#define TXP_CMD_DELETE_SA 0x35 154#define TXP_CMD_ENABLE_RX_IP_OPTION 0x36 155#define TXP_CMD_RANDOM_NUMBER_CONTROL 0x37 156#define TXP_CMD_RANDOM_NUMBER_READ 0x38 157#define TXP_CMD_MATRIX_TABLE_MODE_WRITE 0x39 158#define TXP_CMD_MATRIX_DETAIL_READ 0x3a 159#define TXP_CMD_FILTER_ARRAY_READ 0x3b 160#define TXP_CMD_FILTER_DETAIL_READ 0x3c 161#define TXP_CMD_FILTER_TABLE_MODE_WRITE 0x3d 162#define TXP_CMD_FILTER_TCL_WRITE 0x3e 163#define TXP_CMD_FILTER_TBL_READ 0x3f 164#define TXP_CMD_VERSIONS_READ 0x43 165#define TXP_CMD_FILTER_DEFINE 0x45 166#define TXP_CMD_ADD_WAKEUP_PKT 0x46 167#define TXP_CMD_ADD_SLEEP_PKT 0x47 168#define TXP_CMD_ENABLE_SLEEP_EVENTS 0x48 169#define TXP_CMD_ENABLE_WAKEUP_EVENTS 0x49 170#define TXP_CMD_GET_IP_ADDRESS 0x4a 171#define TXP_CMD_READ_PCI_REG 0x4c 172#define TXP_CMD_WRITE_PCI_REG 0x4d 173#define TXP_CMD_OFFLOAD_READ 0x4e 174#define TXP_CMD_OFFLOAD_WRITE 0x4f 175#define TXP_CMD_HELLO_RESPONSE 0x57 176#define TXP_CMD_ENABLE_RX_FILTER 0x58 177#define TXP_CMD_RX_FILTER_CAPABILITY 0x59 178#define TXP_CMD_HALT 0x5d 179#define TXP_CMD_READ_IPSEC_INFO 0x54 180#define TXP_CMD_GET_IPSEC_ENABLE 0x67 181#define TXP_CMD_INVALID 0xffff 182 183#define TXP_FRAGMENT 0x0000 184#define TXP_TXFRAME 0x0001 185#define TXP_COMMAND 0x0002 186#define TXP_OPTION 0x0003 187#define TXP_RECEIVE 0x0004 188#define TXP_RESPONSE 0x0005 189 190#define TXP_TYPE_IPSEC 0x0000 191#define TXP_TYPE_TCPSEGMENT 0x0001 192 193#define TXP_PFLAG_NOCRC 0x0000 194#define TXP_PFLAG_IPCKSUM 0x0001 195#define TXP_PFLAG_TCPCKSUM 0x0002 196#define TXP_PFLAG_TCPSEGMENT 0x0004 197#define TXP_PFLAG_INSERTVLAN 0x0008 198#define TXP_PFLAG_IPSEC 0x0010 199#define TXP_PFLAG_PRIORITY 0x0020 200#define TXP_PFLAG_UDPCKSUM 0x0040 201#define TXP_PFLAG_PADFRAME 0x0080 202 203#define TXP_MISC_FIRSTDESC 0x0000 204#define TXP_MISC_LASTDESC 0x0001 205 206#define TXP_ERR_INTERNAL 0x0000 207#define TXP_ERR_FIFOUNDERRUN 0x0001 208#define TXP_ERR_BADSSD 0x0002 209#define TXP_ERR_RUNT 0x0003 210#define TXP_ERR_CRC 0x0004 211#define TXP_ERR_OVERSIZE 0x0005 212#define TXP_ERR_ALIGNMENT 0x0006 213#define TXP_ERR_DRIBBLEBIT 0x0007 214 215#define TXP_PROTO_UNKNOWN 0x0000 216#define TXP_PROTO_IP 0x0001 217#define TXP_PROTO_IPX 0x0002 218#define TXP_PROTO_RESERVED 0x0003 219 220#define TXP_STAT_PROTO 0x0001 221#define TXP_STAT_VLAN 0x0002 222#define TXP_STAT_IPFRAGMENT 0x0004 223#define TXP_STAT_IPSEC 0x0008 224#define TXP_STAT_IPCKSUMBAD 0x0010 225#define TXP_STAT_TCPCKSUMBAD 0x0020 226#define TXP_STAT_UDPCKSUMBAD 0x0040 227#define TXP_STAT_IPCKSUMGOOD 0x0080 228#define TXP_STAT_TCPCKSUMGOOD 0x0100 229#define TXP_STAT_UDPCKSUMGOOD 0x0200 230 231struct txp_tx_desc { 232 uint8_t tx_flags; /* type/descriptor flags */ 233 uint8_t tx_numdesc; /* number of descriptors */ 234 uint16_t tx_totlen; /* total packet length */ 235 uint32_t tx_addrlo; /* virt addr low word */ 236 uint32_t tx_addrhi; /* virt addr high word */ 237 uint32_t tx_pflags; /* processing flags */ 238}; 239#define TX_FLAGS_TYPE_M 0x07 /* type mask */ 240#define TX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 241#define TX_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 242#define TX_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 243#define TX_FLAGS_TYPE_OPT 0x03 /* type: options */ 244#define TX_FLAGS_TYPE_RX 0x04 /* type: command */ 245#define TX_FLAGS_TYPE_RESP 0x05 /* type: response */ 246#define TX_FLAGS_RESP 0x40 /* response requested */ 247#define TX_FLAGS_VALID 0x80 /* valid descriptor */ 248 249#define TX_PFLAGS_DNAC 0x00000001 /* do not add crc */ 250#define TX_PFLAGS_IPCKSUM 0x00000002 /* ip checksum */ 251#define TX_PFLAGS_TCPCKSUM 0x00000004 /* tcp checksum */ 252#define TX_PFLAGS_TCPSEG 0x00000008 /* tcp segmentation */ 253#define TX_PFLAGS_VLAN 0x00000010 /* insert vlan */ 254#define TX_PFLAGS_IPSEC 0x00000020 /* perform ipsec */ 255#define TX_PFLAGS_PRIO 0x00000040 /* priority field valid */ 256#define TX_PFLAGS_UDPCKSUM 0x00000080 /* udp checksum */ 257#define TX_PFLAGS_PADFRAME 0x00000100 /* pad frame */ 258#define TX_PFLAGS_VLANTAG_M 0x0ffff000 /* vlan tag mask */ 259#define TX_PFLAGS_VLANPRI_M 0x00700000 /* vlan priority mask */ 260#define TX_PFLAGS_VLANTAG_S 12 /* amount to shift tag */ 261 262struct txp_rx_desc { 263 uint8_t rx_flags; /* type/descriptor flags */ 264 uint8_t rx_numdesc; /* number of descriptors */ 265 uint16_t rx_len; /* frame length */ 266 uint32_t rx_vaddrlo; /* virtual address, lo word */ 267 uint32_t rx_vaddrhi; /* virtual address, hi word */ 268 uint32_t rx_stat; /* status */ 269 uint16_t rx_filter; /* filter status */ 270 uint16_t rx_hash; /* hash status */ 271 uint32_t rx_vlan; /* vlan tag/priority */ 272}; 273 274/* txp_rx_desc.rx_flags */ 275#define RX_FLAGS_TYPE_M 0x07 /* type mask */ 276#define RX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 277#define RX_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 278#define RX_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 279#define RX_FLAGS_TYPE_OPT 0x03 /* type: options */ 280#define RX_FLAGS_TYPE_RX 0x04 /* type: command */ 281#define RX_FLAGS_TYPE_RESP 0x05 /* type: response */ 282#define RX_FLAGS_RCV_TYPE_M 0x18 /* rcvtype mask */ 283#define RX_FLAGS_RCV_TYPE_RX 0x00 /* rcvtype: receive */ 284#define RX_FLAGS_RCV_TYPE_RSP 0x08 /* rcvtype: response */ 285#define RX_FLAGS_ERROR 0x40 /* error in packet */ 286 287/* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR bit set) */ 288#define RX_ERROR_ADAPTER 0x00000000 /* adapter internal error */ 289#define RX_ERROR_FIFO 0x00000001 /* fifo underrun */ 290#define RX_ERROR_BADSSD 0x00000002 /* bad ssd */ 291#define RX_ERROR_RUNT 0x00000003 /* runt packet */ 292#define RX_ERROR_CRC 0x00000004 /* bad crc */ 293#define RX_ERROR_OVERSIZE 0x00000005 /* oversized packet */ 294#define RX_ERROR_ALIGN 0x00000006 /* alignment error */ 295#define RX_ERROR_DRIBBLE 0x00000007 /* dribble bit */ 296#define RX_ERROR_MASK 0x07 297 298/* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR not bit set) */ 299#define RX_STAT_PROTO_M 0x00000003 /* protocol mask */ 300#define RX_STAT_PROTO_UK 0x00000000 /* unknown protocol */ 301#define RX_STAT_PROTO_IPX 0x00000001 /* IPX */ 302#define RX_STAT_PROTO_IP 0x00000002 /* IP */ 303#define RX_STAT_PROTO_RSV 0x00000003 /* reserved */ 304#define RX_STAT_VLAN 0x00000004 /* vlan tag (in rxd) */ 305#define RX_STAT_IPFRAG 0x00000008 /* fragment, ipsec not done */ 306#define RX_STAT_IPSEC 0x00000010 /* ipsec decoded packet */ 307#define RX_STAT_IPCKSUMBAD 0x00000020 /* ip checksum failed */ 308#define RX_STAT_UDPCKSUMBAD 0x00000040 /* udp checksum failed */ 309#define RX_STAT_TCPCKSUMBAD 0x00000080 /* tcp checksum failed */ 310#define RX_STAT_IPCKSUMGOOD 0x00000100 /* ip checksum succeeded */ 311#define RX_STAT_UDPCKSUMGOOD 0x00000200 /* udp checksum succeeded */ 312#define RX_STAT_TCPCKSUMGOOD 0x00000400 /* tcp checksum succeeded */ 313 314 315struct txp_rxbuf_desc { 316 uint32_t rb_paddrlo; 317 uint32_t rb_paddrhi; 318 uint32_t rb_vaddrlo; 319 uint32_t rb_vaddrhi; 320}; 321 322/* Extension descriptor */ 323struct txp_ext_desc { 324 uint32_t ext_1; 325 uint32_t ext_2; 326 uint32_t ext_3; 327 uint32_t ext_4; 328}; 329 330struct txp_cmd_desc { 331 uint8_t cmd_flags; 332 uint8_t cmd_numdesc; 333 uint16_t cmd_id; 334 uint16_t cmd_seq; 335 uint16_t cmd_par1; 336 uint32_t cmd_par2; 337 uint32_t cmd_par3; 338}; 339#define CMD_FLAGS_TYPE_M 0x07 /* type mask */ 340#define CMD_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 341#define CMD_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 342#define CMD_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 343#define CMD_FLAGS_TYPE_OPT 0x03 /* type: options */ 344#define CMD_FLAGS_TYPE_RX 0x04 /* type: command */ 345#define CMD_FLAGS_TYPE_RESP 0x05 /* type: response */ 346#define CMD_FLAGS_RESP 0x40 /* response requested */ 347#define CMD_FLAGS_VALID 0x80 /* valid descriptor */ 348 349struct txp_rsp_desc { 350 uint8_t rsp_flags; 351 uint8_t rsp_numdesc; 352 uint16_t rsp_id; 353 uint16_t rsp_seq; 354 uint16_t rsp_par1; 355 uint32_t rsp_par2; 356 uint32_t rsp_par3; 357}; 358#define RSP_FLAGS_TYPE_M 0x07 /* type mask */ 359#define RSP_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 360#define RSP_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 361#define RSP_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 362#define RSP_FLAGS_TYPE_OPT 0x03 /* type: options */ 363#define RSP_FLAGS_TYPE_RX 0x04 /* type: command */ 364#define RSP_FLAGS_TYPE_RESP 0x05 /* type: response */ 365#define RSP_FLAGS_ERROR 0x40 /* response error */ 366 367struct txp_frag_desc { 368 uint8_t frag_flags; /* type/descriptor flags */ 369 uint8_t frag_rsvd1; 370 uint16_t frag_len; /* bytes in this fragment */ 371 uint32_t frag_addrlo; /* phys addr low word */ 372 uint32_t frag_addrhi; /* phys addr high word */ 373 uint32_t frag_rsvd2; 374}; 375#define FRAG_FLAGS_TYPE_M 0x07 /* type mask */ 376#define FRAG_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 377#define FRAG_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 378#define FRAG_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 379#define FRAG_FLAGS_TYPE_OPT 0x03 /* type: options */ 380#define FRAG_FLAGS_TYPE_RX 0x04 /* type: command */ 381#define FRAG_FLAGS_TYPE_RESP 0x05 /* type: response */ 382#define FRAG_FLAGS_VALID 0x80 /* valid descriptor */ 383 384struct txp_opt_desc { 385 uint8_t opt_desctype:3, 386 opt_rsvd:1, 387 opt_type:4; 388 389 uint8_t opt_num; 390 uint16_t opt_dep1; 391 uint32_t opt_dep2; 392 uint32_t opt_dep3; 393 uint32_t opt_dep4; 394}; 395 396struct txp_ipsec_desc { 397 uint8_t ipsec_desctpe:3, 398 ipsec_rsvd:1, 399 ipsec_type:4; 400 401 uint8_t ipsec_num; 402 uint16_t ipsec_flags; 403 uint16_t ipsec_ah1; 404 uint16_t ipsec_esp1; 405 uint16_t ipsec_ah2; 406 uint16_t ipsec_esp2; 407 uint32_t ipsec_rsvd1; 408}; 409 410struct txp_tcpseg_desc { 411 uint8_t tcpseg_type; 412 uint8_t tcpseg_num; 413 uint16_t tcpseg_mss; 414 uint32_t tcpseg_respaddr; 415 uint32_t tcpseg_txbytes; 416 uint32_t tcpseg_lss; 417}; 418#define TCPSEG_DESC_TYPE_M 0x07 /* type mask */ 419#define TCPSEG_DESC_TYPE_FRAG 0x00 /* type: fragment */ 420#define TCPSEG_DESC_TYPE_DATA 0x01 /* type: data frame */ 421#define TCPSEG_DESC_TYPE_CMD 0x02 /* type: command frame */ 422#define TCPSEG_DESC_TYPE_OPT 0x03 /* type: options */ 423#define TCPSEG_DESC_TYPE_RX 0x04 /* type: command */ 424#define TCPSEG_DESC_TYPE_RESP 0x05 /* type: response */ 425#define TCPSEG_OPT_IPSEC 0x00 426#define TCPSEG_OPT_TSO 0x10 427#define TCPSEG_MSS_MASK 0x0FFF 428#define TCPSEG_MSS_FIRST 0x1000 429#define TCPSEG_MSS_LAST 0x2000 430 431/* 432 * Transceiver types 433 */ 434#define TXP_XCVR_10_HDX 0 435#define TXP_XCVR_10_FDX 1 436#define TXP_XCVR_100_HDX 2 437#define TXP_XCVR_100_FDX 3 438#define TXP_XCVR_AUTO 4 439 440#define TXP_MEDIA_CRC 0x0004 /* crc strip disable */ 441#define TXP_MEDIA_CD 0x0010 /* collision detection */ 442#define TXP_MEDIA_CS 0x0020 /* carrier sense */ 443#define TXP_MEDIA_POL 0x0400 /* polarity reversed */ 444#define TXP_MEDIA_NOLINK 0x0800 /* 0 = link, 1 = no link */ 445 446/* 447 * receive filter bits (par1 to TXP_CMD_RX_FILTER_{READ|WRITE} 448 */ 449#define TXP_RXFILT_DIRECT 0x0001 /* directed packets */ 450#define TXP_RXFILT_ALLMULTI 0x0002 /* all multicast packets */ 451#define TXP_RXFILT_BROADCAST 0x0004 /* broadcast packets */ 452#define TXP_RXFILT_PROMISC 0x0008 /* promiscuous mode */ 453#define TXP_RXFILT_HASHMULTI 0x0010 /* use multicast filter */ 454 455/* 456 * boot record (pointers to rings) 457 */ 458struct txp_boot_record { 459 uint32_t br_hostvar_lo; /* host ring pointer */ 460 uint32_t br_hostvar_hi; 461 uint32_t br_txlopri_lo; /* tx low pri ring */ 462 uint32_t br_txlopri_hi; 463 uint32_t br_txlopri_siz; 464 uint32_t br_txhipri_lo; /* tx high pri ring */ 465 uint32_t br_txhipri_hi; 466 uint32_t br_txhipri_siz; 467 uint32_t br_rxlopri_lo; /* rx low pri ring */ 468 uint32_t br_rxlopri_hi; 469 uint32_t br_rxlopri_siz; 470 uint32_t br_rxbuf_lo; /* rx buffer ring */ 471 uint32_t br_rxbuf_hi; 472 uint32_t br_rxbuf_siz; 473 uint32_t br_cmd_lo; /* command ring */ 474 uint32_t br_cmd_hi; 475 uint32_t br_cmd_siz; 476 uint32_t br_resp_lo; /* response ring */ 477 uint32_t br_resp_hi; 478 uint32_t br_resp_siz; 479 uint32_t br_zero_lo; /* zero word */ 480 uint32_t br_zero_hi; 481 uint32_t br_rxhipri_lo; /* rx high pri ring */ 482 uint32_t br_rxhipri_hi; 483 uint32_t br_rxhipri_siz; 484}; 485 486/* 487 * hostvar structure (shared with typhoon) 488 */ 489struct txp_hostvar { 490 uint32_t hv_rx_hi_read_idx; /* host->arm */ 491 uint32_t hv_rx_lo_read_idx; /* host->arm */ 492 uint32_t hv_rx_buf_write_idx; /* host->arm */ 493 uint32_t hv_resp_read_idx; /* host->arm */ 494 uint32_t hv_tx_lo_desc_read_idx; /* arm->host */ 495 uint32_t hv_tx_hi_desc_read_idx; /* arm->host */ 496 uint32_t hv_rx_lo_write_idx; /* arm->host */ 497 uint32_t hv_rx_buf_read_idx; /* arm->host */ 498 uint32_t hv_cmd_read_idx; /* arm->host */ 499 uint32_t hv_resp_write_idx; /* arm->host */ 500 uint32_t hv_rx_hi_write_idx; /* arm->host */ 501}; 502 503/* 504 * TYPHOON status register state (in TXP_A2H_0) 505 */ 506#define STAT_ROM_CODE 0x00000001 507#define STAT_ROM_EEPROM_LOAD 0x00000002 508#define STAT_WAITING_FOR_BOOT 0x00000007 509#define STAT_RUNNING 0x00000009 510#define STAT_WAITING_FOR_HOST_REQUEST 0x0000000d 511#define STAT_WAITING_FOR_SEGMENT 0x00000010 512#define STAT_SLEEPING 0x00000011 513#define STAT_HALTED 0x00000014 514 515#define TX_ENTRIES 256 516#define RX_ENTRIES 128 517#define RXBUF_ENTRIES 256 518#define CMD_ENTRIES 32 519#define RSP_ENTRIES 32 520 521#define OFFLOAD_TCPCKSUM 0x00000002 /* tcp checksum */ 522#define OFFLOAD_UDPCKSUM 0x00000004 /* udp checksum */ 523#define OFFLOAD_IPCKSUM 0x00000008 /* ip checksum */ 524#define OFFLOAD_IPSEC 0x00000010 /* ipsec enable */ 525#define OFFLOAD_BCAST 0x00000020 /* broadcast throttle */ 526#define OFFLOAD_DHCP 0x00000040 /* dhcp prevention */ 527#define OFFLOAD_VLAN 0x00000080 /* vlan enable */ 528#define OFFLOAD_FILTER 0x00000100 /* filter enable */ 529#define OFFLOAD_TCPSEG 0x00000200 /* tcp segmentation */ 530#define OFFLOAD_MASK 0xfffffffe /* mask off low bit */ 531 532/* 533 * Macros for converting array indices to offsets within the descriptor 534 * arrays. The chip operates on offsets, but it's much easier for us 535 * to operate on indices. Assumes descriptor entries are 16 bytes. 536 */ 537#define TXP_IDX2OFFSET(idx) ((idx) << 4) 538#define TXP_OFFSET2IDX(off) ((off) >> 4) 539 540struct txp_cmd_ring { 541 struct txp_cmd_desc *base; 542 uint32_t lastwrite; 543 uint32_t size; 544}; 545 546struct txp_rsp_ring { 547 struct txp_rsp_desc *base; 548 uint32_t lastwrite; 549 uint32_t size; 550}; 551 552struct txp_tx_ring { 553 struct txp_tx_desc *r_desc; /* base address of descs */ 554 bus_dma_tag_t r_tag; 555 bus_dmamap_t r_map; 556 uint32_t r_reg; /* register to activate */ 557 uint32_t r_prod; /* producer */ 558 uint32_t r_cons; /* consumer */ 559 uint32_t r_cnt; /* # descs in use */ 560 uint32_t *r_off; /* hostvar index pointer */ 561}; 562 563struct txp_swdesc { 564 struct mbuf *sd_mbuf; 565 bus_dmamap_t sd_map; 566}; 567 568struct txp_rx_swdesc { 569 TAILQ_ENTRY(txp_rx_swdesc) sd_next; 570 struct mbuf *sd_mbuf; 571 bus_dmamap_t sd_map; 572}; 573 574struct txp_rx_ring { 575 struct txp_rx_desc *r_desc; /* base address of descs */ 576 bus_dma_tag_t r_tag; 577 bus_dmamap_t r_map; 578 uint32_t *r_roff; /* hv read offset ptr */ 579 uint32_t *r_woff; /* hv write offset ptr */ 580}; 581 582struct txp_ldata { 583 struct txp_boot_record *txp_boot; 584 bus_addr_t txp_boot_paddr; 585 struct txp_hostvar *txp_hostvar; 586 bus_addr_t txp_hostvar_paddr; 587 struct txp_tx_desc *txp_txhiring; 588 bus_addr_t txp_txhiring_paddr; 589 struct txp_tx_desc *txp_txloring; 590 bus_addr_t txp_txloring_paddr; 591 struct txp_rxbuf_desc *txp_rxbufs; 592 bus_addr_t txp_rxbufs_paddr; 593 struct txp_rx_desc *txp_rxhiring; 594 bus_addr_t txp_rxhiring_paddr; 595 struct txp_rx_desc *txp_rxloring; 596 bus_addr_t txp_rxloring_paddr; 597 struct txp_cmd_desc *txp_cmdring; 598 bus_addr_t txp_cmdring_paddr; 599 struct txp_rsp_desc *txp_rspring; 600 bus_addr_t txp_rspring_paddr; 601 uint32_t *txp_zero; 602 bus_addr_t txp_zero_paddr; 603}; 604 605struct txp_chain_data { 606 bus_dma_tag_t txp_parent_tag; 607 bus_dma_tag_t txp_boot_tag; 608 bus_dmamap_t txp_boot_map; 609 bus_dma_tag_t txp_hostvar_tag; 610 bus_dmamap_t txp_hostvar_map; 611 bus_dma_tag_t txp_txhiring_tag; 612 bus_dmamap_t txp_txhiring_map; 613 bus_dma_tag_t txp_txloring_tag; 614 bus_dmamap_t txp_txloring_map; 615 bus_dma_tag_t txp_tx_tag; 616 bus_dma_tag_t txp_rx_tag; 617 bus_dma_tag_t txp_rxbufs_tag; 618 bus_dmamap_t txp_rxbufs_map; 619 bus_dma_tag_t txp_rxhiring_tag; 620 bus_dmamap_t txp_rxhiring_map; 621 bus_dma_tag_t txp_rxloring_tag; 622 bus_dmamap_t txp_rxloring_map; 623 bus_dma_tag_t txp_cmdring_tag; 624 bus_dmamap_t txp_cmdring_map; 625 bus_dma_tag_t txp_rspring_tag; 626 bus_dmamap_t txp_rspring_map; 627 bus_dma_tag_t txp_zero_tag; 628 bus_dmamap_t txp_zero_map; 629}; 630 631struct txp_hw_stats { 632 uint32_t tx_frames; 633 uint64_t tx_bytes; 634 uint32_t tx_deferred; 635 uint32_t tx_late_colls; 636 uint32_t tx_colls; 637 uint32_t tx_carrier_lost; 638 uint32_t tx_multi_colls; 639 uint32_t tx_excess_colls; 640 uint32_t tx_fifo_underruns; 641 uint32_t tx_mcast_oflows; 642 uint32_t tx_filtered; 643 uint32_t rx_frames; 644 uint64_t rx_bytes; 645 uint32_t rx_fifo_oflows; 646 uint32_t rx_badssd; 647 uint32_t rx_crcerrs; 648 uint32_t rx_lenerrs; 649 uint32_t rx_bcast_frames; 650 uint32_t rx_mcast_frames; 651 uint32_t rx_oflows; 652 uint32_t rx_filtered; 653}; 654 655struct txp_softc { 656 struct ifnet *sc_ifp; 657 device_t sc_dev; 658 struct txp_hostvar *sc_hostvar; 659 struct txp_boot_record *sc_boot; 660 struct resource *sc_res; 661 int sc_res_id; 662 int sc_res_type; 663 struct resource *sc_irq; 664 void *sc_intrhand; 665 struct txp_chain_data sc_cdata; 666 struct txp_ldata sc_ldata; 667 int sc_rxbufprod; 668 int sc_process_limit; 669 struct txp_cmd_ring sc_cmdring; 670 struct txp_rsp_ring sc_rspring; 671 struct callout sc_tick; 672 struct ifmedia sc_ifmedia; 673 struct txp_hw_stats sc_ostats; 674 struct txp_hw_stats sc_stats; 675 struct txp_tx_ring sc_txhir, sc_txlor; 676 struct txp_swdesc sc_txd[TX_ENTRIES]; 677 struct txp_rxbuf_desc *sc_rxbufs; 678 struct txp_rx_ring sc_rxhir, sc_rxlor; 679 uint16_t sc_xcvr; 680 uint16_t sc_seq; 681 int sc_watchdog_timer; 682 int sc_if_flags; 683 int sc_flags; 684#define TXP_FLAG_DETACH 0x4000 685#define TXP_FLAG_LINK 0x8000 686 TAILQ_HEAD(, txp_rx_swdesc) sc_free_list; 687 TAILQ_HEAD(, txp_rx_swdesc) sc_busy_list; 688 struct task sc_int_task; 689 struct taskqueue *sc_tq; 690 struct mtx sc_mtx; 691}; 692 693struct txp_fw_file_header { 694 uint8_t magicid[8]; /* TYPHOON\0 */ 695 uint32_t version; 696 uint32_t nsections; 697 uint32_t addr; 698 uint32_t hmac[5]; 699}; 700 701struct txp_fw_section_header { 702 uint32_t nbytes; 703 uint16_t cksum; 704 uint16_t reserved; 705 uint32_t addr; 706}; 707 708#define TXP_MAX_SEGLEN 0xffff 709#define TXP_MAX_PKTLEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) 710 711#define WRITE_REG(sc, reg, val) bus_write_4((sc)->sc_res, reg, val) 712#define READ_REG(sc, reg) bus_read_4((sc)->sc_res, reg) 713#define TXP_BARRIER(sc, o, l, f) bus_barrier((sc)->sc_res, (o), (l), (f)) 714 715#define TXP_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 716#define TXP_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 717#define TXP_LOCK_ASSERT(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 718 719#define TXP_MAXTXSEGS 16 720#define TXP_RXBUF_ALIGN (sizeof(uint32_t)) 721 722#define TXP_PROC_MIN 16 723#define TXP_PROC_MAX RX_ENTRIES 724#define TXP_PROC_DEFAULT (RX_ENTRIES / 2) 725 726#define TXP_ADDR_HI(x) ((uint64_t)(x) >> 32) 727#define TXP_ADDR_LO(x) ((uint64_t)(x) & 0xffffffff) 728 729/* 730 * 3Com PCI vendor ID. 731 */ 732#define TXP_VENDORID_3COM 0x10B7 733 734/* 735 * 3cR990 device IDs 736 */ 737#define TXP_DEVICEID_3CR990_TX_95 0x9902 738#define TXP_DEVICEID_3CR990_TX_97 0x9903 739#define TXP_DEVICEID_3CR990B_TXM 0x9904 740#define TXP_DEVICEID_3CR990_SRV_95 0x9908 741#define TXP_DEVICEID_3CR990_SRV_97 0x9909 742#define TXP_DEVICEID_3CR990B_SRV 0x990A 743 744struct txp_type { 745 uint16_t txp_vid; 746 uint16_t txp_did; 747 char *txp_name; 748}; 749 750#define TXP_TIMEOUT 10000 751#define TXP_CMD_NOWAIT 0 752#define TXP_CMD_WAIT 1 753#define TXP_TX_TIMEOUT 5 754 755/* 756 * Each frame requires one frame descriptor and one or more 757 * fragment descriptors. If TSO is used frame descriptor block 758 * requires one or two option frame descriptors depending on 759 * number of framents. Therefore we will consume three 760 * additional descriptors at most to use TSO for a frame and 761 * one reserved descriptor in order not to full Tx descriptor 762 * ring. 763 */ 764#define TXP_TXD_RESERVED 4 765 766#define TXP_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 767