1/*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD$ 35 */ 36 37struct tl_type { 38 u_int16_t tl_vid; 39 u_int16_t tl_did; 40 const char *tl_name; 41}; 42 43/* 44 * ThunderLAN TX/RX list format. The TX and RX lists are pretty much 45 * identical: the list begins with a 32-bit forward pointer which points 46 * at the next list in the chain, followed by 16 bits for the total 47 * frame size, and a 16 bit status field. This is followed by a series 48 * of 10 32-bit data count/data address pairs that point to the fragments 49 * that make up the complete frame. 50 */ 51 52#define TL_MAXFRAGS 10 53#define TL_RX_LIST_CNT 64 54#define TL_TX_LIST_CNT 128 55#define TL_MIN_FRAMELEN 64 56 57struct tl_frag { 58 u_int32_t tlist_dcnt; 59 u_int32_t tlist_dadr; 60}; 61 62struct tl_list { 63 u_int32_t tlist_fptr; /* phys address of next list */ 64 u_int16_t tlist_cstat; /* status word */ 65 u_int16_t tlist_frsize; /* size of data in frame */ 66 struct tl_frag tl_frag[TL_MAXFRAGS]; 67}; 68 69/* 70 * This is a special case of an RX list. By setting the One_Frag 71 * bit in the NETCONFIG register, the driver can force the ThunderLAN 72 * chip to use only one fragment when DMAing RX frames. 73 */ 74 75struct tl_list_onefrag { 76 u_int32_t tlist_fptr; 77 u_int16_t tlist_cstat; 78 u_int16_t tlist_frsize; 79 struct tl_frag tl_frag; 80}; 81 82struct tl_list_data { 83 struct tl_list_onefrag tl_rx_list[TL_RX_LIST_CNT]; 84 struct tl_list tl_tx_list[TL_TX_LIST_CNT]; 85 unsigned char tl_pad[TL_MIN_FRAMELEN]; 86}; 87 88struct tl_chain { 89 struct tl_list *tl_ptr; 90 struct mbuf *tl_mbuf; 91 struct tl_chain *tl_next; 92}; 93 94struct tl_chain_onefrag { 95 struct tl_list_onefrag *tl_ptr; 96 struct mbuf *tl_mbuf; 97 struct tl_chain_onefrag *tl_next; 98}; 99 100struct tl_chain_data { 101 struct tl_chain_onefrag tl_rx_chain[TL_RX_LIST_CNT]; 102 struct tl_chain tl_tx_chain[TL_TX_LIST_CNT]; 103 104 struct tl_chain_onefrag *tl_rx_head; 105 struct tl_chain_onefrag *tl_rx_tail; 106 107 struct tl_chain *tl_tx_head; 108 struct tl_chain *tl_tx_tail; 109 struct tl_chain *tl_tx_free; 110}; 111 112struct tl_softc { 113 struct ifnet *tl_ifp; 114 device_t tl_dev; 115 struct ifmedia ifmedia; /* media info */ 116 void *tl_intrhand; 117 struct resource *tl_irq; 118 struct resource *tl_res; 119 device_t tl_miibus; 120 u_int8_t tl_eeaddr; 121 struct tl_list_data *tl_ldata; /* TX/RX lists and mbufs */ 122 struct tl_chain_data tl_cdata; 123 u_int8_t tl_txeoc; 124 u_int8_t tl_bitrate; 125 int tl_if_flags; 126 struct callout tl_stat_callout; 127 struct mtx tl_mtx; 128 int tl_timer; 129}; 130 131#define TL_LOCK(_sc) mtx_lock(&(_sc)->tl_mtx) 132#define TL_UNLOCK(_sc) mtx_unlock(&(_sc)->tl_mtx) 133#define TL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tl_mtx, MA_OWNED) 134 135/* 136 * Transmit interrupt threshold. 137 */ 138#define TX_THR 0x00000004 139 140/* 141 * General constants that are fun to know. 142 * 143 * The ThunderLAN controller is made by Texas Instruments. The 144 * manual indicates that if the EEPROM checksum fails, the PCI 145 * vendor and device ID registers will be loaded with TI-specific 146 * values. 147 */ 148#define TI_VENDORID 0x104C 149#define TI_DEVICEID_THUNDERLAN 0x0500 150 151/* 152 * These are the PCI vendor and device IDs for Compaq ethernet 153 * adapters based on the ThunderLAN controller. 154 */ 155#define COMPAQ_VENDORID 0x0E11 156#define COMPAQ_DEVICEID_NETEL_10_100 0xAE32 157#define COMPAQ_DEVICEID_NETEL_UNKNOWN 0xAE33 158#define COMPAQ_DEVICEID_NETEL_10 0xAE34 159#define COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED 0xAE35 160#define COMPAQ_DEVICEID_NETEL_10_100_DUAL 0xAE40 161#define COMPAQ_DEVICEID_NETEL_10_100_PROLIANT 0xAE43 162#define COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED 0xB011 163#define COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX 0xB012 164#define COMPAQ_DEVICEID_NETEL_10_100_TX_UTP 0xB030 165#define COMPAQ_DEVICEID_NETFLEX_3P 0xF130 166#define COMPAQ_DEVICEID_NETFLEX_3P_BNC 0xF150 167 168/* 169 * These are the PCI vendor and device IDs for Olicom 170 * adapters based on the ThunderLAN controller. 171 */ 172#define OLICOM_VENDORID 0x108D 173#define OLICOM_DEVICEID_OC2183 0x0013 174#define OLICOM_DEVICEID_OC2325 0x0012 175#define OLICOM_DEVICEID_OC2326 0x0014 176 177/* 178 * PCI low memory base and low I/O base 179 */ 180#define TL_PCI_LOIO 0x10 181#define TL_PCI_LOMEM 0x14 182 183/* 184 * PCI latency timer (it's actually 0x0D, but we want a value 185 * that's longword aligned). 186 */ 187#define TL_PCI_LATENCY_TIMER 0x0C 188 189#define TL_DIO_ADDR_INC 0x8000 /* Increment addr on each read */ 190#define TL_DIO_RAM_SEL 0x4000 /* RAM address select */ 191#define TL_DIO_ADDR_MASK 0x3FFF /* address bits mask */ 192 193/* 194 * Interrupt types 195 */ 196#define TL_INTR_INVALID 0x0 197#define TL_INTR_TXEOF 0x1 198#define TL_INTR_STATOFLOW 0x2 199#define TL_INTR_RXEOF 0x3 200#define TL_INTR_DUMMY 0x4 201#define TL_INTR_TXEOC 0x5 202#define TL_INTR_ADCHK 0x6 203#define TL_INTR_RXEOC 0x7 204 205#define TL_INT_MASK 0x001C 206#define TL_VEC_MASK 0x1FE0 207 208/* 209 * Host command register bits 210 */ 211#define TL_CMD_GO 0x80000000 212#define TL_CMD_STOP 0x40000000 213#define TL_CMD_ACK 0x20000000 214#define TL_CMD_CHSEL7 0x10000000 215#define TL_CMD_CHSEL6 0x08000000 216#define TL_CMD_CHSEL5 0x04000000 217#define TL_CMD_CHSEL4 0x02000000 218#define TL_CMD_CHSEL3 0x01000000 219#define TL_CMD_CHSEL2 0x00800000 220#define TL_CMD_CHSEL1 0x00400000 221#define TL_CMD_CHSEL0 0x00200000 222#define TL_CMD_EOC 0x00100000 223#define TL_CMD_RT 0x00080000 224#define TL_CMD_NES 0x00040000 225#define TL_CMD_ZERO0 0x00020000 226#define TL_CMD_ZERO1 0x00010000 227#define TL_CMD_ADRST 0x00008000 228#define TL_CMD_LDTMR 0x00004000 229#define TL_CMD_LDTHR 0x00002000 230#define TL_CMD_REQINT 0x00001000 231#define TL_CMD_INTSOFF 0x00000800 232#define TL_CMD_INTSON 0x00000400 233#define TL_CMD_RSVD0 0x00000200 234#define TL_CMD_RSVD1 0x00000100 235#define TL_CMD_ACK7 0x00000080 236#define TL_CMD_ACK6 0x00000040 237#define TL_CMD_ACK5 0x00000020 238#define TL_CMD_ACK4 0x00000010 239#define TL_CMD_ACK3 0x00000008 240#define TL_CMD_ACK2 0x00000004 241#define TL_CMD_ACK1 0x00000002 242#define TL_CMD_ACK0 0x00000001 243 244#define TL_CMD_CHSEL_MASK 0x01FE0000 245#define TL_CMD_ACK_MASK 0xFF 246 247/* 248 * EEPROM address where station address resides. 249 */ 250#define TL_EEPROM_EADDR 0x83 251#define TL_EEPROM_EADDR2 0x99 252#define TL_EEPROM_EADDR3 0xAF 253#define TL_EEPROM_EADDR_OC 0xF8 /* Olicom cards use a different 254 address than Compaqs. */ 255/* 256 * ThunderLAN host command register offsets. 257 * (Can be accessed either by IO ports or memory map.) 258 */ 259#define TL_HOSTCMD 0x00 260#define TL_CH_PARM 0x04 261#define TL_DIO_ADDR 0x08 262#define TL_HOST_INT 0x0A 263#define TL_DIO_DATA 0x0C 264 265/* 266 * ThunderLAN internal registers 267 */ 268#define TL_NETCMD 0x00 269#define TL_NETSIO 0x01 270#define TL_NETSTS 0x02 271#define TL_NETMASK 0x03 272 273#define TL_NETCONFIG 0x04 274#define TL_MANTEST 0x06 275 276#define TL_VENID_LSB 0x08 277#define TL_VENID_MSB 0x09 278#define TL_DEVID_LSB 0x0A 279#define TL_DEVID_MSB 0x0B 280 281#define TL_REVISION 0x0C 282#define TL_SUBCLASS 0x0D 283#define TL_MINLAT 0x0E 284#define TL_MAXLAT 0x0F 285 286#define TL_AREG0_B5 0x10 287#define TL_AREG0_B4 0x11 288#define TL_AREG0_B3 0x12 289#define TL_AREG0_B2 0x13 290 291#define TL_AREG0_B1 0x14 292#define TL_AREG0_B0 0x15 293#define TL_AREG1_B5 0x16 294#define TL_AREG1_B4 0x17 295 296#define TL_AREG1_B3 0x18 297#define TL_AREG1_B2 0x19 298#define TL_AREG1_B1 0x1A 299#define TL_AREG1_B0 0x1B 300 301#define TL_AREG2_B5 0x1C 302#define TL_AREG2_B4 0x1D 303#define TL_AREG2_B3 0x1E 304#define TL_AREG2_B2 0x1F 305 306#define TL_AREG2_B1 0x20 307#define TL_AREG2_B0 0x21 308#define TL_AREG3_B5 0x22 309#define TL_AREG3_B4 0x23 310 311#define TL_AREG3_B3 0x24 312#define TL_AREG3_B2 0x25 313#define TL_AREG3_B1 0x26 314#define TL_AREG3_B0 0x27 315 316#define TL_HASH1 0x28 317#define TL_HASH2 0x2C 318#define TL_TXGOODFRAMES 0x30 319#define TL_TXUNDERRUN 0x33 320#define TL_RXGOODFRAMES 0x34 321#define TL_RXOVERRUN 0x37 322#define TL_DEFEREDTX 0x38 323#define TL_CRCERROR 0x3A 324#define TL_CODEERROR 0x3B 325#define TL_MULTICOLTX 0x3C 326#define TL_SINGLECOLTX 0x3E 327#define TL_EXCESSIVECOL 0x40 328#define TL_LATECOL 0x41 329#define TL_CARRIERLOSS 0x42 330#define TL_ACOMMIT 0x43 331#define TL_LDREG 0x44 332#define TL_BSIZEREG 0x45 333#define TL_MAXRX 0x46 334 335/* 336 * ThunderLAN SIO register bits 337 */ 338#define TL_SIO_MINTEN 0x80 339#define TL_SIO_ECLOK 0x40 340#define TL_SIO_ETXEN 0x20 341#define TL_SIO_EDATA 0x10 342#define TL_SIO_NMRST 0x08 343#define TL_SIO_MCLK 0x04 344#define TL_SIO_MTXEN 0x02 345#define TL_SIO_MDATA 0x01 346 347/* 348 * Thunderlan NETCONFIG bits 349 */ 350#define TL_CFG_RCLKTEST 0x8000 351#define TL_CFG_TCLKTEST 0x4000 352#define TL_CFG_BITRATE 0x2000 353#define TL_CFG_RXCRC 0x1000 354#define TL_CFG_PEF 0x0800 355#define TL_CFG_ONEFRAG 0x0400 356#define TL_CFG_ONECHAN 0x0200 357#define TL_CFG_MTEST 0x0100 358#define TL_CFG_PHYEN 0x0080 359#define TL_CFG_MACSEL6 0x0040 360#define TL_CFG_MACSEL5 0x0020 361#define TL_CFG_MACSEL4 0x0010 362#define TL_CFG_MACSEL3 0x0008 363#define TL_CFG_MACSEL2 0x0004 364#define TL_CFG_MACSEL1 0x0002 365#define TL_CFG_MACSEL0 0x0001 366 367/* 368 * ThunderLAN NETSTS bits 369 */ 370#define TL_STS_MIRQ 0x80 371#define TL_STS_HBEAT 0x40 372#define TL_STS_TXSTOP 0x20 373#define TL_STS_RXSTOP 0x10 374 375/* 376 * ThunderLAN NETCMD bits 377 */ 378#define TL_CMD_NRESET 0x80 379#define TL_CMD_NWRAP 0x40 380#define TL_CMD_CSF 0x20 381#define TL_CMD_CAF 0x10 382#define TL_CMD_NOBRX 0x08 383#define TL_CMD_DUPLEX 0x04 384#define TL_CMD_TRFRAM 0x02 385#define TL_CMD_TXPACE 0x01 386 387/* 388 * ThunderLAN NETMASK bits 389 */ 390#define TL_MASK_MASK7 0x80 391#define TL_MASK_MASK6 0x40 392#define TL_MASK_MASK5 0x20 393#define TL_MASK_MASK4 0x10 394 395#define TL_LAST_FRAG 0x80000000 396#define TL_CSTAT_UNUSED 0x8000 397#define TL_CSTAT_FRAMECMP 0x4000 398#define TL_CSTAT_READY 0x3000 399#define TL_CSTAT_UNUSED13 0x2000 400#define TL_CSTAT_UNUSED12 0x1000 401#define TL_CSTAT_EOC 0x0800 402#define TL_CSTAT_RXERROR 0x0400 403#define TL_CSTAT_PASSCRC 0x0200 404#define TL_CSTAT_DPRIO 0x0100 405 406#define TL_FRAME_MASK 0x00FFFFFF 407#define tl_tx_goodframes(x) (x.tl_txstat & TL_FRAME_MASK) 408#define tl_tx_underrun(x) ((x.tl_txstat & ~TL_FRAME_MASK) >> 24) 409#define tl_rx_goodframes(x) (x.tl_rxstat & TL_FRAME_MASK) 410#define tl_rx_overrun(x) ((x.tl_rxstat & ~TL_FRAME_MASK) >> 24) 411 412struct tl_stats { 413 u_int32_t tl_txstat; 414 u_int32_t tl_rxstat; 415 u_int16_t tl_deferred; 416 u_int8_t tl_crc_errors; 417 u_int8_t tl_code_errors; 418 u_int16_t tl_tx_multi_collision; 419 u_int16_t tl_tx_single_collision; 420 u_int8_t tl_excessive_collision; 421 u_int8_t tl_late_collision; 422 u_int8_t tl_carrier_loss; 423 u_int8_t acommit; 424}; 425 426/* 427 * ACOMMIT register bits. These are used only when a bitrate 428 * PHY is selected ('bitrate' bit in netconfig register is set). 429 */ 430#define TL_AC_MTXER 0x01 /* reserved */ 431#define TL_AC_MTXD1 0x02 /* 0 == 10baseT 1 == AUI */ 432#define TL_AC_MTXD2 0x04 /* loopback disable */ 433#define TL_AC_MTXD3 0x08 /* full duplex disable */ 434 435#define TL_AC_TXTHRESH 0xF0 436#define TL_AC_TXTHRESH_16LONG 0x00 437#define TL_AC_TXTHRESH_32LONG 0x10 438#define TL_AC_TXTHRESH_64LONG 0x20 439#define TL_AC_TXTHRESH_128LONG 0x30 440#define TL_AC_TXTHRESH_256LONG 0x40 441#define TL_AC_TXTHRESH_WHOLEPKT 0x50 442 443/* 444 * PCI burst size register (TL_BSIZEREG). 445 */ 446#define TL_RXBURST 0x0F 447#define TL_TXBURST 0xF0 448 449#define TL_RXBURST_4LONG 0x00 450#define TL_RXBURST_8LONG 0x01 451#define TL_RXBURST_16LONG 0x02 452#define TL_RXBURST_32LONG 0x03 453#define TL_RXBURST_64LONG 0x04 454#define TL_RXBURST_128LONG 0x05 455 456#define TL_TXBURST_4LONG 0x00 457#define TL_TXBURST_8LONG 0x10 458#define TL_TXBURST_16LONG 0x20 459#define TL_TXBURST_32LONG 0x30 460#define TL_TXBURST_64LONG 0x40 461#define TL_TXBURST_128LONG 0x50 462 463/* 464 * register space access macros 465 */ 466#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->tl_res, reg, val) 467#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->tl_res, reg, val) 468#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->tl_res, reg, val) 469 470#define CSR_READ_4(sc, reg) bus_read_4(sc->tl_res, reg) 471#define CSR_READ_2(sc, reg) bus_read_2(sc->tl_res, reg) 472#define CSR_READ_1(sc, reg) bus_read_1(sc->tl_res, reg) 473 474#define CSR_BARRIER(sc, reg, length, flags) \ 475 bus_barrier(sc->tl_res, reg, length, flags) 476 477#define CMD_PUT(sc, x) CSR_WRITE_4(sc, TL_HOSTCMD, x) 478#define CMD_SET(sc, x) \ 479 CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) | (x)) 480#define CMD_CLR(sc, x) \ 481 CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) & ~(x)) 482 483/* 484 * ThunderLAN adapters typically have a serial EEPROM containing 485 * configuration information. The main reason we're interested in 486 * it is because it also contains the adapters's station address. 487 * 488 * Access to the EEPROM is a bit goofy since it is a serial device: 489 * you have to do reads and writes one bit at a time. The state of 490 * the DATA bit can only change while the CLOCK line is held low. 491 * Transactions work basically like this: 492 * 493 * 1) Send the EEPROM_START sequence to prepare the EEPROM for 494 * accepting commands. This pulls the clock high, sets 495 * the data bit to 0, enables transmission to the EEPROM, 496 * pulls the data bit up to 1, then pulls the clock low. 497 * The idea is to do a 0 to 1 transition of the data bit 498 * while the clock pin is held high. 499 * 500 * 2) To write a bit to the EEPROM, set the TXENABLE bit, then 501 * set the EDATA bit to send a 1 or clear it to send a 0. 502 * Finally, set and then clear ECLOK. Strobing the clock 503 * transmits the bit. After 8 bits have been written, the 504 * EEPROM should respond with an ACK, which should be read. 505 * 506 * 3) To read a bit from the EEPROM, clear the TXENABLE bit, 507 * then set ECLOK. The bit can then be read by reading EDATA. 508 * ECLOCK should then be cleared again. This can be repeated 509 * 8 times to read a whole byte, after which the 510 * 511 * 4) We need to send the address byte to the EEPROM. For this 512 * we have to send the write control byte to the EEPROM to 513 * tell it to accept data. The byte is 0xA0. The EEPROM should 514 * ack this. The address byte can be send after that. 515 * 516 * 5) Now we have to tell the EEPROM to send us data. For that we 517 * have to transmit the read control byte, which is 0xA1. This 518 * byte should also be acked. We can then read the data bits 519 * from the EEPROM. 520 * 521 * 6) When we're all finished, send the EEPROM_STOP sequence. 522 * 523 * Note that we use the ThunderLAN's NetSio register to access the 524 * EEPROM, however there is an alternate method. There is a PCI NVRAM 525 * register at PCI offset 0xB4 which can also be used with minor changes. 526 * The difference is that access to PCI registers via pci_conf_read() 527 * and pci_conf_write() is done using programmed I/O, which we want to 528 * avoid. 529 */ 530 531/* 532 * Note that EEPROM_START leaves transmission enabled. 533 */ 534#define EEPROM_START \ 535 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock pin high */\ 536 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Set DATA bit to 1 */ \ 537 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit to write bit */\ 538 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA bit to 0 again */\ 539 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */ 540 541/* 542 * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so 543 * that no further data can be written to the EEPROM I/O pin. 544 */ 545#define EEPROM_STOP \ 546 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit */ \ 547 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA to 0 */ \ 548 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock high */ \ 549 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit */ \ 550 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Toggle DATA to 1 */ \ 551 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit. */ \ 552 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */ 553 554 555/* 556 * Microchip Technology 24Cxx EEPROM control bytes 557 */ 558#define EEPROM_CTL_READ 0xA1 /* 0101 0001 */ 559#define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */ 560