1/* $NetBSD: if_stgereg.h,v 1.3 2003/02/10 21:10:07 christos Exp $ */ 2 3/*- 4 * SPDX-License-Identifier: BSD-2-Clause-NetBSD 5 * 6 * Copyright (c) 2001 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Jason R. Thorpe. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34/* $FreeBSD$ */ 35 36/* 37 * Sundance Technology PCI vendor ID 38 */ 39#define VENDOR_SUNDANCETI 0x13f0 40 41/* 42 * Tamarack Microelectronics PCI vendor ID 43 */ 44#define VENDOR_TAMARACK 0x143d 45 46/* 47 * D-Link Systems PCI vendor ID 48 */ 49#define VENDOR_DLINK 0x1186 50 51/* 52 * Antares Microsystems PCI vendor ID 53 */ 54#define VENDOR_ANTARES 0x1754 55 56/* 57 * Sundance Technology device ID 58 */ 59#define DEVICEID_SUNDANCETI_ST1023 0x1023 60#define DEVICEID_SUNDANCETI_ST2021 0x2021 61#define DEVICEID_TAMARACK_TC9021 0x1021 62#define DEVICEID_TAMARACK_TC9021_ALT 0x9021 63 64/* 65 * D-Link Systems device ID 66 */ 67#define DEVICEID_DLINK_DL4000 0x4000 68 69/* 70 * Antares Microsystems device ID 71 */ 72#define DEVICEID_ANTARES_TC9021 0x1021 73 74/* 75 * Register description for the Sundance Tech. TC9021 10/100/1000 76 * Ethernet controller. 77 * 78 * Note that while DMA addresses are all in 64-bit fields, only 79 * the lower 40 bits of a DMA address are valid. 80 */ 81#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 82#define STGE_DMA_MAXADDR BUS_SPACE_MAXADDR 83#else 84#define STGE_DMA_MAXADDR 0xFFFFFFFFFF 85#endif 86 87/* 88 * Register access macros 89 */ 90#define CSR_WRITE_4(_sc, reg, val) \ 91 bus_write_4((_sc)->sc_res[0], (reg), (val)) 92#define CSR_WRITE_2(_sc, reg, val) \ 93 bus_write_2((_sc)->sc_res[0], (reg), (val)) 94#define CSR_WRITE_1(_sc, reg, val) \ 95 bus_write_1((_sc)->sc_res[0], (reg), (val)) 96 97#define CSR_READ_4(_sc, reg) \ 98 bus_read_4((_sc)->sc_res[0], (reg)) 99#define CSR_READ_2(_sc, reg) \ 100 bus_read_2((_sc)->sc_res[0], (reg)) 101#define CSR_READ_1(_sc, reg) \ 102 bus_read_1((_sc)->sc_res[0], (reg)) 103 104#define CSR_BARRIER(_sc, reg, length, flags) \ 105 bus_barrier((_sc)->sc_res[0], reg, length, flags) 106 107/* 108 * TC9021 buffer fragment descriptor. 109 */ 110struct stge_frag { 111 uint64_t frag_word0; /* address, length */ 112}; 113 114#define FRAG_ADDR(x) (((uint64_t)(x)) << 0) 115#define FRAG_ADDR_MASK FRAG_ADDR(0xfffffffffULL) 116#define FRAG_LEN(x) (((uint64_t)(x)) << 48) 117#define FRAG_LEN_MASK FRAG_LEN(0xffffULL) 118 119/* 120 * TC9021 Transmit Frame Descriptor. Note the number of fragments 121 * here is arbitrary, but we can't have any more than 15. 122 */ 123#define STGE_NTXFRAGS 15 124struct stge_tfd { 125 uint64_t tfd_next; /* next TFD in list */ 126 uint64_t tfd_control; /* control bits */ 127 /* the buffer fragments */ 128 struct stge_frag tfd_frags[STGE_NTXFRAGS]; 129}; 130 131#define TFD_FrameId(x) ((x) << 0) 132#define TFD_FrameId_MAX 0xffff 133#define TFD_WordAlign(x) ((x) << 16) 134#define TFD_WordAlign_dword 0 /* align to dword in TxFIFO */ 135#define TFD_WordAlign_word 2 /* align to word in TxFIFO */ 136#define TFD_WordAlign_disable 1 /* disable alignment */ 137#define TFD_TCPChecksumEnable (1ULL << 18) 138#define TFD_UDPChecksumEnable (1ULL << 19) 139#define TFD_IPChecksumEnable (1ULL << 20) 140#define TFD_FcsAppendDisable (1ULL << 21) 141#define TFD_TxIndicate (1ULL << 22) 142#define TFD_TxDMAIndicate (1ULL << 23) 143#define TFD_FragCount(x) ((x) << 24) 144#define TFD_VLANTagInsert (1ULL << 28) 145#define TFD_TFDDone (1ULL << 31) 146#define TFD_VID(x) (((uint64_t)(x)) << 32) 147#define TFD_CFI (1ULL << 44) 148#define TFD_UserPriority(x) (((uint64_t)(x)) << 45) 149 150/* 151 * TC9021 Receive Frame Descriptor. Each RFD has a single fragment 152 * in it, and the chip tells us the beginning and end of the frame. 153 */ 154struct stge_rfd { 155 uint64_t rfd_next; /* next RFD in list */ 156 uint64_t rfd_status; /* status bits */ 157 struct stge_frag rfd_frag; /* the buffer */ 158}; 159 160/* Low word of rfd_status */ 161#define RFD_RxStatus(x) ((x) & 0xffffffff) 162#define RFD_RxDMAFrameLen(x) ((x) & 0xffff) 163#define RFD_RxFIFOOverrun 0x00010000 164#define RFD_RxRuntFrame 0x00020000 165#define RFD_RxAlignmentError 0x00040000 166#define RFD_RxFCSError 0x00080000 167#define RFD_RxOversizedFrame 0x00100000 168#define RFD_RxLengthError 0x00200000 169#define RFD_VLANDetected 0x00400000 170#define RFD_TCPDetected 0x00800000 171#define RFD_TCPError 0x01000000 172#define RFD_UDPDetected 0x02000000 173#define RFD_UDPError 0x04000000 174#define RFD_IPDetected 0x08000000 175#define RFD_IPError 0x10000000 176#define RFD_FrameStart 0x20000000 177#define RFD_FrameEnd 0x40000000 178#define RFD_RFDDone 0x80000000 179/* High word of rfd_status */ 180#define RFD_TCI(x) ((((uint64_t)(x)) >> 32) & 0xffff) 181 182/* 183 * EEPROM offsets. 184 */ 185#define STGE_EEPROM_ConfigParam 0x00 186#define STGE_EEPROM_AsicCtrl 0x01 187#define STGE_EEPROM_SubSystemVendorId 0x02 188#define STGE_EEPROM_SubSystemId 0x03 189#define STGE_EEPROM_LEDMode 0x06 190#define STGE_EEPROM_StationAddress0 0x10 191#define STGE_EEPROM_StationAddress1 0x11 192#define STGE_EEPROM_StationAddress2 0x12 193 194/* 195 * The TC9021 register space. 196 */ 197 198#define STGE_DMACtrl 0x00 199#define DMAC_RxDMAComplete (1U << 3) 200#define DMAC_RxDMAPollNow (1U << 4) 201#define DMAC_TxDMAComplete (1U << 11) 202#define DMAC_TxDMAPollNow (1U << 12) 203#define DMAC_TxDMAInProg (1U << 15) 204#define DMAC_RxEarlyDisable (1U << 16) 205#define DMAC_MWIDisable (1U << 18) 206#define DMAC_TxWriteBackDisable (1U << 19) 207#define DMAC_TxBurstLimit(x) ((x) << 20) 208#define DMAC_TargetAbort (1U << 30) 209#define DMAC_MasterAbort (1U << 31) 210 211#define STGE_RxDMAStatus 0x08 212 213#define STGE_TFDListPtrLo 0x10 214 215#define STGE_TFDListPtrHi 0x14 216 217#define STGE_TxDMABurstThresh 0x18 /* 8-bit */ 218 219#define STGE_TxDMAUrgentThresh 0x19 /* 8-bit */ 220 221#define STGE_TxDMAPollPeriod 0x1a /* 8-bit, 320ns increments */ 222 223#define STGE_RFDListPtrLo 0x1c 224 225#define STGE_RFDListPtrHi 0x20 226 227#define STGE_RxDMABurstThresh 0x24 /* 8-bit */ 228 229#define STGE_RxDMAUrgentThresh 0x25 /* 8-bit */ 230 231#define STGE_RxDMAPollPeriod 0x26 /* 8-bit, 320ns increments */ 232 233#define STGE_RxDMAIntCtrl 0x28 234#define RDIC_RxFrameCount(x) ((x) & 0xff) 235#define RDIC_PriorityThresh(x) ((x) << 10) 236#define RDIC_RxDMAWaitTime(x) ((x) << 16) 237/* 238 * Number of receive frames transferred via DMA before a Rx interrupt is issued. 239 */ 240#define STGE_RXINT_NFRAME_DEFAULT 8 241#define STGE_RXINT_NFRAME_MIN 1 242#define STGE_RXINT_NFRAME_MAX 255 243/* 244 * Maximum amount of time (in 64ns increments) to wait before issuing a Rx 245 * interrupt if number of frames recevied is less than STGE_RXINT_NFRAME 246 * (STGE_RXINT_NFRAME_MIN <= STGE_RXINT_NFRAME <= STGE_RXINT_NFRAME_MAX) 247 */ 248#define STGE_RXINT_DMAWAIT_DEFAULT 30 /* 30us */ 249#define STGE_RXINT_DMAWAIT_MIN 0 250#define STGE_RXINT_DMAWAIT_MAX 4194 251#define STGE_RXINT_USECS2TICK(x) (((x) * 1000)/64) 252 253#define STGE_DebugCtrl 0x2c /* 16-bit */ 254#define DC_GPIO0Ctrl (1U << 0) 255#define DC_GPIO1Ctrl (1U << 1) 256#define DC_GPIO0 (1U << 2) 257#define DC_GPIO1 (1U << 3) 258 259#define STGE_AsicCtrl 0x30 260#define AC_ExpRomDisable (1U << 0) 261#define AC_ExpRomSize (1U << 1) 262#define AC_PhySpeed10 (1U << 4) 263#define AC_PhySpeed100 (1U << 5) 264#define AC_PhySpeed1000 (1U << 6) 265#define AC_PhyMedia (1U << 7) 266#define AC_ForcedConfig(x) ((x) << 8) 267#define AC_ForcedConfig_MASK AC_ForcedConfig(7) 268#define AC_D3ResetDisable (1U << 11) 269#define AC_SpeedupMode (1U << 13) 270#define AC_LEDMode (1U << 14) 271#define AC_RstOutPolarity (1U << 15) 272#define AC_GlobalReset (1U << 16) 273#define AC_RxReset (1U << 17) 274#define AC_TxReset (1U << 18) 275#define AC_DMA (1U << 19) 276#define AC_FIFO (1U << 20) 277#define AC_Network (1U << 21) 278#define AC_Host (1U << 22) 279#define AC_AutoInit (1U << 23) 280#define AC_RstOut (1U << 24) 281#define AC_InterruptRequest (1U << 25) 282#define AC_ResetBusy (1U << 26) 283#define AC_LEDSpeed (1U << 27) 284#define AC_LEDModeBit1 (1U << 29) 285 286#define STGE_FIFOCtrl 0x38 /* 16-bit */ 287#define FC_RAMTestMode (1U << 0) 288#define FC_Transmitting (1U << 14) 289#define FC_Receiving (1U << 15) 290 291#define STGE_RxEarlyThresh 0x3a /* 16-bit */ 292 293#define STGE_FlowOffThresh 0x3c /* 16-bit */ 294 295#define STGE_FlowOnTresh 0x3e /* 16-bit */ 296 297#define STGE_TxStartThresh 0x44 /* 16-bit */ 298 299#define STGE_EepromData 0x48 /* 16-bit */ 300 301#define STGE_EepromCtrl 0x4a /* 16-bit */ 302#define EC_EepromAddress(x) ((x) & 0xff) 303#define EC_EepromOpcode(x) ((x) << 8) 304#define EC_OP_WE 0 305#define EC_OP_WR 1 306#define EC_OP_RR 2 307#define EC_OP_ER 3 308#define EC_EepromBusy (1U << 15) 309 310#define STGE_ExpRomAddr 0x4c 311 312#define STGE_ExpRomData 0x50 /* 8-bit */ 313 314#define STGE_WakeEvent 0x51 /* 8-bit */ 315#define WE_WakePktEnable (1U << 0) 316#define WE_MagicPktEnable (1U << 1) 317#define WE_LinkEventEnable (1U << 2) 318#define WE_WakePolarity (1U << 3) 319#define WE_WakePktEvent (1U << 4) 320#define WE_MagicPktEvent (1U << 5) 321#define WE_LinkEvent (1U << 6) 322#define WE_WakeOnLanEnable (1U << 7) 323 324#define STGE_Countdown 0x54 325#define CD_Count(x) ((x) & 0xffff) 326#define CD_CountdownSpeed (1U << 24) 327#define CD_CountdownMode (1U << 25) 328#define CD_CountdownIntEnabled (1U << 26) 329 330#define STGE_IntStatusAck 0x5a /* 16-bit */ 331 332#define STGE_IntEnable 0x5c /* 16-bit */ 333 334#define STGE_IntStatus 0x5e /* 16-bit */ 335 336#define IS_InterruptStatus (1U << 0) 337#define IS_HostError (1U << 1) 338#define IS_TxComplete (1U << 2) 339#define IS_MACControlFrame (1U << 3) 340#define IS_RxComplete (1U << 4) 341#define IS_RxEarly (1U << 5) 342#define IS_InRequested (1U << 6) 343#define IS_UpdateStats (1U << 7) 344#define IS_LinkEvent (1U << 8) 345#define IS_TxDMAComplete (1U << 9) 346#define IS_RxDMAComplete (1U << 10) 347#define IS_RFDListEnd (1U << 11) 348#define IS_RxDMAPriority (1U << 12) 349 350#define STGE_TxStatus 0x60 351#define TS_TxError (1U << 0) 352#define TS_LateCollision (1U << 2) 353#define TS_MaxCollisions (1U << 3) 354#define TS_TxUnderrun (1U << 4) 355#define TS_TxIndicateReqd (1U << 6) 356#define TS_TxComplete (1U << 7) 357#define TS_TxFrameId_get(x) ((x) >> 16) 358 359#define STGE_MACCtrl 0x6c 360#define MC_IFSSelect(x) ((x) & 3) 361#define MC_IFS96bit 0 362#define MC_IFS1024bit 1 363#define MC_IFS1792bit 2 364#define MC_IFS4352bit 3 365 366#define MC_DuplexSelect (1U << 5) 367#define MC_RcvLargeFrames (1U << 6) 368#define MC_TxFlowControlEnable (1U << 7) 369#define MC_RxFlowControlEnable (1U << 8) 370#define MC_RcvFCS (1U << 9) 371#define MC_FIFOLoopback (1U << 10) 372#define MC_MACLoopback (1U << 11) 373#define MC_AutoVLANtagging (1U << 12) 374#define MC_AutoVLANuntagging (1U << 13) 375#define MC_CollisionDetect (1U << 16) 376#define MC_CarrierSense (1U << 17) 377#define MC_StatisticsEnable (1U << 21) 378#define MC_StatisticsDisable (1U << 22) 379#define MC_StatisticsEnabled (1U << 23) 380#define MC_TxEnable (1U << 24) 381#define MC_TxDisable (1U << 25) 382#define MC_TxEnabled (1U << 26) 383#define MC_RxEnable (1U << 27) 384#define MC_RxDisable (1U << 28) 385#define MC_RxEnabled (1U << 29) 386#define MC_Paused (1U << 30) 387#define MC_MASK 0x7fe33fa3 388 389#define STGE_VLANTag 0x70 390 391#define STGE_PhySet 0x75 /* 8-bit */ 392#define PS_MemLenb9b (1U << 0) 393#define PS_MemLen (1U << 1) 394#define PS_NonCompdet (1U << 2) 395 396#define STGE_PhyCtrl 0x76 /* 8-bit */ 397#define PC_MgmtClk (1U << 0) 398#define PC_MgmtData (1U << 1) 399#define PC_MgmtDir (1U << 2) /* MAC->PHY */ 400#define PC_PhyDuplexPolarity (1U << 3) 401#define PC_PhyDuplexStatus (1U << 4) 402#define PC_PhyLnkPolarity (1U << 5) 403#define PC_LinkSpeed(x) (((x) >> 6) & 3) 404#define PC_LinkSpeed_Down 0 405#define PC_LinkSpeed_10 1 406#define PC_LinkSpeed_100 2 407#define PC_LinkSpeed_1000 3 408 409#define STGE_StationAddress0 0x78 /* 16-bit */ 410 411#define STGE_StationAddress1 0x7a /* 16-bit */ 412 413#define STGE_StationAddress2 0x7c /* 16-bit */ 414 415#define STGE_VLANHashTable 0x7e /* 16-bit */ 416 417#define STGE_VLANId 0x80 418 419#define STGE_MaxFrameSize 0x86 420 421#define STGE_ReceiveMode 0x88 /* 16-bit */ 422#define RM_ReceiveUnicast (1U << 0) 423#define RM_ReceiveMulticast (1U << 1) 424#define RM_ReceiveBroadcast (1U << 2) 425#define RM_ReceiveAllFrames (1U << 3) 426#define RM_ReceiveMulticastHash (1U << 4) 427#define RM_ReceiveIPMulticast (1U << 5) 428#define RM_ReceiveVLANMatch (1U << 8) 429#define RM_ReceiveVLANHash (1U << 9) 430 431#define STGE_HashTable0 0x8c 432 433#define STGE_HashTable1 0x90 434 435#define STGE_RMONStatisticsMask 0x98 /* set to disable */ 436 437#define STGE_StatisticsMask 0x9c /* set to disable */ 438 439#define STGE_RxJumboFrames 0xbc /* 16-bit */ 440 441#define STGE_TCPCheckSumErrors 0xc0 /* 16-bit */ 442 443#define STGE_IPCheckSumErrors 0xc2 /* 16-bit */ 444 445#define STGE_UDPCheckSumErrors 0xc4 /* 16-bit */ 446 447#define STGE_TxJumboFrames 0xf4 /* 16-bit */ 448 449/* 450 * TC9021 statistics. Available memory and I/O mapped. 451 */ 452 453#define STGE_OctetRcvOk 0xa8 454 455#define STGE_McstOctetRcvdOk 0xac 456 457#define STGE_BcstOctetRcvdOk 0xb0 458 459#define STGE_FramesRcvdOk 0xb4 460 461#define STGE_McstFramesRcvdOk 0xb8 462 463#define STGE_BcstFramesRcvdOk 0xbe /* 16-bit */ 464 465#define STGE_MacControlFramesRcvd 0xc6 /* 16-bit */ 466 467#define STGE_FrameTooLongErrors 0xc8 /* 16-bit */ 468 469#define STGE_InRangeLengthErrors 0xca /* 16-bit */ 470 471#define STGE_FramesCheckSeqErrors 0xcc /* 16-bit */ 472 473#define STGE_FramesLostRxErrors 0xce /* 16-bit */ 474 475#define STGE_OctetXmtdOk 0xd0 476 477#define STGE_McstOctetXmtdOk 0xd4 478 479#define STGE_BcstOctetXmtdOk 0xd8 480 481#define STGE_FramesXmtdOk 0xdc 482 483#define STGE_McstFramesXmtdOk 0xe0 484 485#define STGE_FramesWDeferredXmt 0xe4 486 487#define STGE_LateCollisions 0xe8 488 489#define STGE_MultiColFrames 0xec 490 491#define STGE_SingleColFrames 0xf0 492 493#define STGE_BcstFramesXmtdOk 0xf6 /* 16-bit */ 494 495#define STGE_CarrierSenseErrors 0xf8 /* 16-bit */ 496 497#define STGE_MacControlFramesXmtd 0xfa /* 16-bit */ 498 499#define STGE_FramesAbortXSColls 0xfc /* 16-bit */ 500 501#define STGE_FramesWEXDeferal 0xfe /* 16-bit */ 502 503/* 504 * RMON-compatible statistics. Only accessible if memory-mapped. 505 */ 506 507#define STGE_EtherStatsCollisions 0x100 508 509#define STGE_EtherStatsOctetsTransmit 0x104 510 511#define STGE_EtherStatsPktsTransmit 0x108 512 513#define STGE_EtherStatsPkts64OctetsTransmit 0x10c 514 515#define STGE_EtherStatsPkts64to127OctetsTransmit 0x110 516 517#define STGE_EtherStatsPkts128to255OctetsTransmit 0x114 518 519#define STGE_EtherStatsPkts256to511OctetsTransmit 0x118 520 521#define STGE_EtherStatsPkts512to1023OctetsTransmit 0x11c 522 523#define STGE_EtherStatsPkts1024to1518OctetsTransmit 0x120 524 525#define STGE_EtherStatsCRCAlignErrors 0x124 526 527#define STGE_EtherStatsUndersizePkts 0x128 528 529#define STGE_EtherStatsFragments 0x12c 530 531#define STGE_EtherStatsJabbers 0x130 532 533#define STGE_EtherStatsOctets 0x134 534 535#define STGE_EtherStatsPkts 0x138 536 537#define STGE_EtherStatsPkts64Octets 0x13c 538 539#define STGE_EtherStatsPkts65to127Octets 0x140 540 541#define STGE_EtherStatsPkts128to255Octets 0x144 542 543#define STGE_EtherStatsPkts256to511Octets 0x148 544 545#define STGE_EtherStatsPkts512to1023Octets 0x14c 546 547#define STGE_EtherStatsPkts1024to1518Octets 0x150 548 549/* 550 * Transmit descriptor list size. 551 */ 552#define STGE_TX_RING_CNT 256 553#define STGE_TX_LOWAT (STGE_TX_RING_CNT/32) 554#define STGE_TX_HIWAT (STGE_TX_RING_CNT - STGE_TX_LOWAT) 555 556/* 557 * Receive descriptor list size. 558 */ 559#define STGE_RX_RING_CNT 256 560 561#define STGE_MAXTXSEGS STGE_NTXFRAGS 562 563#define STGE_JUMBO_FRAMELEN 9022 564#define STGE_JUMBO_MTU \ 565 (STGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 566 567struct stge_txdesc { 568 struct mbuf *tx_m; /* head of our mbuf chain */ 569 bus_dmamap_t tx_dmamap; /* our DMA map */ 570 STAILQ_ENTRY(stge_txdesc) tx_q; 571}; 572 573STAILQ_HEAD(stge_txdq, stge_txdesc); 574 575struct stge_rxdesc { 576 struct mbuf *rx_m; 577 bus_dmamap_t rx_dmamap; 578}; 579 580#define STGE_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff) 581#define STGE_ADDR_HI(x) ((u_int64_t) (x) >> 32) 582 583#define STGE_RING_ALIGN 8 584 585struct stge_chain_data{ 586 bus_dma_tag_t stge_parent_tag; 587 bus_dma_tag_t stge_tx_tag; 588 struct stge_txdesc stge_txdesc[STGE_TX_RING_CNT]; 589 struct stge_txdq stge_txfreeq; 590 struct stge_txdq stge_txbusyq; 591 bus_dma_tag_t stge_rx_tag; 592 struct stge_rxdesc stge_rxdesc[STGE_RX_RING_CNT]; 593 bus_dma_tag_t stge_tx_ring_tag; 594 bus_dmamap_t stge_tx_ring_map; 595 bus_dma_tag_t stge_rx_ring_tag; 596 bus_dmamap_t stge_rx_ring_map; 597 bus_dmamap_t stge_rx_sparemap; 598 599 int stge_tx_prod; 600 int stge_tx_cons; 601 int stge_tx_cnt; 602 int stge_rx_cons; 603#ifdef DEVICE_POLLING 604 int stge_rxcycles; 605#endif 606 int stge_rxlen; 607 struct mbuf *stge_rxhead; 608 struct mbuf *stge_rxtail; 609}; 610 611struct stge_ring_data { 612 struct stge_tfd *stge_tx_ring; 613 bus_addr_t stge_tx_ring_paddr; 614 struct stge_rfd *stge_rx_ring; 615 bus_addr_t stge_rx_ring_paddr; 616}; 617 618#define STGE_TX_RING_ADDR(sc, i) \ 619 ((sc)->sc_rdata.stge_tx_ring_paddr + sizeof(struct stge_tfd) * (i)) 620#define STGE_RX_RING_ADDR(sc, i) \ 621 ((sc)->sc_rdata.stge_rx_ring_paddr + sizeof(struct stge_rfd) * (i)) 622 623#define STGE_TX_RING_SZ \ 624 (sizeof(struct stge_tfd) * STGE_TX_RING_CNT) 625#define STGE_RX_RING_SZ \ 626 (sizeof(struct stge_rfd) * STGE_RX_RING_CNT) 627 628/* 629 * Software state per device. 630 */ 631struct stge_softc { 632 struct ifnet *sc_ifp; /* interface info */ 633 device_t sc_dev; 634 device_t sc_miibus; 635 struct resource *sc_res[2]; 636 struct resource_spec *sc_spec; 637 void *sc_ih; /* interrupt cookie */ 638 int sc_rev; /* silicon revision */ 639 640 struct callout sc_tick_ch; /* tick callout */ 641 642 struct stge_chain_data sc_cdata; 643 struct stge_ring_data sc_rdata; 644 int sc_if_flags; 645 int sc_if_framesize; 646 int sc_txthresh; /* Tx threshold */ 647 uint32_t sc_usefiber:1; /* if we're fiber */ 648 uint32_t sc_stge1023:1; /* are we a 1023 */ 649 uint32_t sc_DMACtrl; /* prototype DMACtrl reg. */ 650 uint32_t sc_MACCtrl; /* prototype MacCtrl reg. */ 651 uint16_t sc_IntEnable; /* prototype IntEnable reg. */ 652 uint16_t sc_led; /* LED conf. from EEPROM */ 653 uint8_t sc_PhyCtrl; /* prototype PhyCtrl reg. */ 654 int sc_suspended; 655 int sc_detach; 656 657 int sc_rxint_nframe; 658 int sc_rxint_dmawait; 659 int sc_nerr; 660 int sc_watchdog_timer; 661 int sc_link; 662 663 struct task sc_link_task; 664 struct mtx sc_mii_mtx; /* MII mutex */ 665 struct mtx sc_mtx; 666}; 667 668#define STGE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 669#define STGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 670#define STGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 671#define STGE_MII_LOCK(_sc) mtx_lock(&(_sc)->sc_mii_mtx) 672#define STGE_MII_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mii_mtx) 673 674#define STGE_MAXERR 5 675 676#define STGE_RXCHAIN_RESET(_sc) \ 677do { \ 678 (_sc)->sc_cdata.stge_rxhead = NULL; \ 679 (_sc)->sc_cdata.stge_rxtail = NULL; \ 680 (_sc)->sc_cdata.stge_rxlen = 0; \ 681} while (/*CONSTCOND*/0) 682 683#define STGE_TIMEOUT 1000 684 685#define STGE_RESET_NONE 0x00 686#define STGE_RESET_TX 0x01 687#define STGE_RESET_RX 0x02 688#define STGE_RESET_FULL 0x04 689