1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1999-2000 Taku YAMAMOTO <taku@cent.saitama-u.ac.jp> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * maestro_reg.h,v 1.13 2001/11/11 18:29:46 taku Exp 29 * $FreeBSD$ 30 */ 31 32#ifndef MAESTRO_REG_H_INCLUDED 33#define MAESTRO_REG_H_INCLUDED 34 35/* ----------------------------- 36 * PCI config registers 37 */ 38 39/* Legacy emulation */ 40#define CONF_LEGACY 0x40 41 42#define LEGACY_DISABLED 0x8000 43 44/* Chip configurations */ 45#define CONF_MAESTRO 0x50 46#define MAESTRO_PMC 0x08000000 47#define MAESTRO_SPDIF 0x01000000 48#define MAESTRO_HWVOL 0x00800000 49#define MAESTRO_CHIBUS 0x00100000 50#define MAESTRO_POSTEDWRITE 0x00000080 51#define MAESTRO_DMA_PCITIMING 0x00000040 52#define MAESTRO_SWAP_LR 0x00000020 53 54/* ACPI configurations */ 55#define CONF_ACPI_STOPCLOCK 0x54 56#define ACPI_PART_2ndC_CLOCK 15 57#define ACPI_PART_CODEC_CLOCK 14 58#define ACPI_PART_978 13 /* Docking station or something */ 59#define ACPI_PART_SPDIF 12 60#define ACPI_PART_GLUE 11 /* What? */ 61#define ACPI_PART_DAA 10 62#define ACPI_PART_PCI_IF 9 63#define ACPI_PART_HW_VOL 8 64#define ACPI_PART_GPIO 7 65#define ACPI_PART_ASSP 6 66#define ACPI_PART_SB 5 67#define ACPI_PART_FM 4 68#define ACPI_PART_RINGBUS 3 69#define ACPI_PART_MIDI 2 70#define ACPI_PART_GAME_PORT 1 71#define ACPI_PART_WP 0 72 73/* Power management */ 74#define CONF_PM_PTR 0x34 /* BYTE R */ 75#define PM_CID 0 /* BYTE R */ 76#define PPMI_CID 1 77#define PM_CTRL 4 /* BYTE RW */ 78#define PPMI_D0 0 /* Full power */ 79#define PPMI_D1 1 /* Medium power */ 80#define PPMI_D2 2 /* Low power */ 81#define PPMI_D3 3 /* Turned off */ 82 83 84/* ----------------------------- 85 * I/O ports 86 */ 87 88/* Direct Sound Processor (aka WP) */ 89#define PORT_DSP_DATA 0x00 /* WORD RW */ 90#define PORT_DSP_INDEX 0x02 /* WORD RW */ 91#define PORT_INT_STAT 0x04 /* WORD RW */ 92#define PORT_SAMPLE_CNT 0x06 /* WORD RO */ 93 94/* WaveCache */ 95#define PORT_WAVCACHE_INDEX 0x10 /* WORD RW */ 96#define PORT_WAVCACHE_DATA 0x12 /* WORD RW */ 97#define WAVCACHE_PCMBAR 0x1fc 98#define WAVCACHE_WTBAR 0x1f0 99#define WAVCACHE_BASEADDR_SHIFT 12 100 101#define WAVCACHE_CHCTL_ADDRTAG_MASK 0xfff8 102#define WAVCACHE_CHCTL_U8 0x0004 103#define WAVCACHE_CHCTL_STEREO 0x0002 104#define WAVCACHE_CHCTL_DECREMENTAL 0x0001 105 106#define PORT_WAVCACHE_CTRL 0x14 /* WORD RW */ 107#define WAVCACHE_EXTRA_CH_ENABLED 0x0200 108#define WAVCACHE_ENABLED 0x0100 109#define WAVCACHE_CH_60_ENABLED 0x0080 110#define WAVCACHE_WTSIZE_MASK 0x0060 111#define WAVCACHE_WTSIZE_1MB 0x0000 112#define WAVCACHE_WTSIZE_2MB 0x0020 113#define WAVCACHE_WTSIZE_4MB 0x0040 114#define WAVCACHE_WTSIZE_8MB 0x0060 115#define WAVCACHE_SGC_MASK 0x000c 116#define WAVCACHE_SGC_DISABLED 0x0000 117#define WAVCACHE_SGC_40_47 0x0004 118#define WAVCACHE_SGC_32_47 0x0008 119#define WAVCACHE_TESTMODE 0x0001 120 121/* Host Interruption */ 122#define PORT_HOSTINT_CTRL 0x18 /* WORD RW */ 123#define HOSTINT_CTRL_SOFT_RESET 0x8000 124#define HOSTINT_CTRL_DSOUND_RESET 0x4000 125#define HOSTINT_CTRL_HW_VOL_TO_PME 0x0400 126#define HOSTINT_CTRL_CLKRUN_ENABLED 0x0100 127#define HOSTINT_CTRL_HWVOL_ENABLED 0x0040 128#define HOSTINT_CTRL_ASSP_INT_ENABLED 0x0010 129#define HOSTINT_CTRL_ISDN_INT_ENABLED 0x0008 130#define HOSTINT_CTRL_DSOUND_INT_ENABLED 0x0004 131#define HOSTINT_CTRL_MPU401_INT_ENABLED 0x0002 132#define HOSTINT_CTRL_SB_INT_ENABLED 0x0001 133 134#define PORT_HOSTINT_STAT 0x1a /* BYTE RW */ 135#define HOSTINT_STAT_HWVOL 0x40 136#define HOSTINT_STAT_ASSP 0x10 137#define HOSTINT_STAT_ISDN 0x08 138#define HOSTINT_STAT_DSOUND 0x04 139#define HOSTINT_STAT_MPU401 0x02 140#define HOSTINT_STAT_SB 0x01 141 142/* Hardware volume */ 143#define PORT_HWVOL_CTRL 0x1b /* BYTE RW */ 144#define HWVOL_CTRL_SPLIT_SHADOW 0x01 145 146#define PORT_HWVOL_VOICE_SHADOW 0x1c /* BYTE RW */ 147#define PORT_HWVOL_VOICE 0x1d /* BYTE RW */ 148#define PORT_HWVOL_MASTER_SHADOW 0x1e /* BYTE RW */ 149#define PORT_HWVOL_MASTER 0x1f /* BYTE RW */ 150#define HWVOL_NOP 0x88 151#define HWVOL_MUTE 0x11 152#define HWVOL_UP 0xaa 153#define HWVOL_DOWN 0x66 154 155/* CODEC */ 156#define PORT_CODEC_CMD 0x30 /* BYTE W */ 157#define CODEC_CMD_READ 0x80 158#define CODEC_CMD_WRITE 0x00 159#define CODEC_CMD_ADDR_MASK 0x7f 160 161#define PORT_CODEC_STAT 0x30 /* BYTE R */ 162#define CODEC_STAT_MASK 0x01 163#define CODEC_STAT_RW_DONE 0x00 164#define CODEC_STAT_PROGLESS 0x01 165 166#define PORT_CODEC_REG 0x32 /* WORD RW */ 167 168/* Ring bus control */ 169#define PORT_RINGBUS_CTRL 0x34 /* DWORD RW */ 170#define RINGBUS_CTRL_I2S_ENABLED 0x80000000 171#define RINGBUS_CTRL_RINGBUS_ENABLED 0x20000000 172#define RINGBUS_CTRL_ACLINK_ENABLED 0x10000000 173#define RINGBUS_CTRL_AC97_SWRESET 0x08000000 174 175#define RINGBUS_SRC_MIC 20 176#define RINGBUS_SRC_I2S 16 177#define RINGBUS_SRC_ADC 12 178#define RINGBUS_SRC_MODEM 8 179#define RINGBUS_SRC_DSOUND 4 180#define RINGBUS_SRC_ASSP 0 181 182#define RINGBUS_DEST_MONORAL 000 183#define RINGBUS_DEST_STEREO 010 184#define RINGBUS_DEST_NONE 0 185#define RINGBUS_DEST_DAC 1 186#define RINGBUS_DEST_MODEM_IN 2 187#define RINGBUS_DEST_RESERVED3 3 188#define RINGBUS_DEST_DSOUND_IN 4 189#define RINGBUS_DEST_ASSP_IN 5 190 191/* Ring bus control B */ 192#define PORT_RINGBUS_CTRL_B 0x38 /* BYTE RW */ 193#define RINGBUS_CTRL_SSPE 0x40 194#define RINGBUS_CTRL_2ndCODEC 0x20 195#define RINGBUS_CTRL_SPDIF 0x10 196#define RINGBUS_CTRL_ITB_DISABLE 0x08 197#define RINGBUS_CTRL_CODEC_ID_MASK 0x03 198#define RINGBUS_CTRL_CODEC_ID_AC98 2 199 200/* General Purpose I/O */ 201#define PORT_GPIO_DATA 0x60 /* WORD RW */ 202#define PORT_GPIO_MASK 0x64 /* WORD RW */ 203#define PORT_GPIO_DIR 0x68 /* WORD RW */ 204 205/* Application Specific Signal Processor */ 206#define PORT_ASSP_MEM_INDEX 0x80 /* DWORD RW */ 207#define PORT_ASSP_MEM_DATA 0x84 /* WORD RW */ 208#define PORT_ASSP_CTRL_A 0xa2 /* BYTE RW */ 209#define PORT_ASSP_CTRL_B 0xa4 /* BYTE RW */ 210#define PORT_ASSP_CTRL_C 0xa6 /* BYTE RW */ 211#define PORT_ASSP_HOST_WR_INDEX 0xa8 /* BYTE W */ 212#define PORT_ASSP_HOST_WR_DATA 0xaa /* BYTE RW */ 213#define PORT_ASSP_INT_STAT 0xac /* BYTE RW */ 214 215 216/* ----------------------------- 217 * Wave Processor Indexed Data Registers. 218 */ 219 220#define WPREG_DATA_PORT 0 221#define WPREG_CRAM_PTR 1 222#define WPREG_CRAM_DATA 2 223#define WPREG_WAVE_DATA 3 224#define WPREG_WAVE_PTR_LOW 4 225#define WPREG_WAVE_PTR_HIGH 5 226 227#define WPREG_TIMER_FREQ 6 228#define WP_TIMER_FREQ_PRESCALE_MASK 0x00e0 /* actual - 9 */ 229#define WP_TIMER_FREQ_PRESCALE_SHIFT 5 230#define WP_TIMER_FREQ_DIVIDE_MASK 0x001f 231#define WP_TIMER_FREQ_DIVIDE_SHIFT 0 232 233#define WPREG_WAVE_ROMRAM 7 234#define WP_WAVE_VIRTUAL_ENABLED 0x0400 235#define WP_WAVE_8BITRAM_ENABLED 0x0200 236#define WP_WAVE_DRAM_ENABLED 0x0100 237#define WP_WAVE_RAMSPLIT_MASK 0x00ff 238#define WP_WAVE_RAMSPLIT_SHIFT 0 239 240#define WPREG_BASE 12 241#define WP_PARAOUT_BASE_MASK 0xf000 242#define WP_PARAOUT_BASE_SHIFT 12 243#define WP_PARAIN_BASE_MASK 0x0f00 244#define WP_PARAIN_BASE_SHIFT 8 245#define WP_SERIAL0_BASE_MASK 0x00f0 246#define WP_SERIAL0_BASE_SHIFT 4 247#define WP_SERIAL1_BASE_MASK 0x000f 248#define WP_SERIAL1_BASE_SHIFT 0 249 250#define WPREG_TIMER_ENABLE 17 251#define WPREG_TIMER_START 23 252 253 254/* ----------------------------- 255 * Audio Processing Unit. 256 */ 257#define APUREG_APUTYPE 0 258#define APU_DMA_ENABLED 0x4000 259#define APU_INT_ON_LOOP 0x2000 260#define APU_ENDCURVE 0x1000 261#define APU_APUTYPE_MASK 0x00f0 262#define APU_FILTERTYPE_MASK 0x000c 263#define APU_FILTERQ_MASK 0x0003 264 265/* APU types */ 266#define APU_APUTYPE_SHIFT 4 267 268#define APUTYPE_INACTIVE 0 269#define APUTYPE_16BITLINEAR 1 270#define APUTYPE_16BITSTEREO 2 271#define APUTYPE_8BITLINEAR 3 272#define APUTYPE_8BITSTEREO 4 273#define APUTYPE_8BITDIFF 5 274#define APUTYPE_DIGITALDELAY 6 275#define APUTYPE_DUALTAP_READER 7 276#define APUTYPE_CORRELATOR 8 277#define APUTYPE_INPUTMIXER 9 278#define APUTYPE_WAVETABLE 10 279#define APUTYPE_RATECONV 11 280#define APUTYPE_16BITPINGPONG 12 281/* APU type 13 through 15 are reserved. */ 282 283/* Filter types */ 284#define APU_FILTERTYPE_SHIFT 2 285 286#define FILTERTYPE_2POLE_LOPASS 0 287#define FILTERTYPE_2POLE_BANDPASS 1 288#define FILTERTYPE_2POLE_HIPASS 2 289#define FILTERTYPE_1POLE_LOPASS 3 290#define FILTERTYPE_1POLE_HIPASS 4 291#define FILTERTYPE_PASSTHROUGH 5 292 293/* Filter Q */ 294#define APU_FILTERQ_SHIFT 0 295 296#define FILTERQ_LESSQ 0 297#define FILTERQ_MOREQ 3 298 299/* APU register 2 */ 300#define APUREG_FREQ_LOBYTE 2 301#define APU_FREQ_LOBYTE_MASK 0xff00 302#define APU_plus6dB 0x0010 303 304/* APU register 3 */ 305#define APUREG_FREQ_HIWORD 3 306#define APU_FREQ_HIWORD_MASK 0x0fff 307 308/* Frequency */ 309#define APU_FREQ_LOBYTE_SHIFT 8 310#define APU_FREQ_HIWORD_SHIFT 0 311#define FREQ_Hz2DIV(freq) (((u_int64_t)(freq) << 16) / 48000) 312 313/* APU register 4 */ 314#define APUREG_WAVESPACE 4 315#define APU_64KPAGE_MASK 0xff00 316 317/* 64KW (==128KB) Page */ 318#define APU_64KPAGE_SHIFT 8 319 320/* Wave Processor Wavespace Address */ 321#define WPWA_MAX ((1 << 22) - 1) 322#define WPWA_STEREO (1 << 23) 323#define WPWA_USE_SYSMEM (1 << 22) 324 325#define WPWA_WTBAR_SHIFT(wtsz) WPWA_WTBAR_SHIFT_##wtsz 326#define WPWA_WTBAR_SHIFT_1 15 327#define WPWA_WTBAR_SHIFT_2 16 328#define WPWA_WTBAR_SHIFT_4 17 329#define WPWA_WTBAR_SHIFT_8 18 330 331#define WPWA_PCMBAR_SHIFT 20 332 333/* APU register 5 - 7 */ 334#define APUREG_CURPTR 5 335#define APUREG_ENDPTR 6 336#define APUREG_LOOPLEN 7 337 338/* APU register 8 */ 339#define APUREG_EFFECT_GAIN 8 340 341/* Effect gain? */ 342#define APUREG_EFFECT_GAIN_MASK 0x00ff 343 344/* APU register 9 */ 345#define APUREG_AMPLITUDE 9 346#define APU_AMPLITUDE_NOW_MASK 0xff00 347#define APU_AMPLITUDE_DEST_MASK 0x00ff 348 349/* Amplitude now? */ 350#define APU_AMPLITUDE_NOW_SHIFT 8 351 352/* APU register 10 */ 353#define APUREG_POSITION 10 354#define APU_RADIUS_MASK 0x00c0 355#define APU_PAN_MASK 0x003f 356 357/* Radius control. */ 358#define APU_RADIUS_SHIFT 6 359#define RADIUS_CENTERCIRCLE 0 360#define RADIUS_MIDDLE 1 361#define RADIUS_OUTSIDE 2 362 363/* Polar pan. */ 364#define APU_PAN_SHIFT 0 365#define PAN_RIGHT 0x00 366#define PAN_FRONT 0x08 367#define PAN_LEFT 0x10 368 369/* Source routing. */ 370#define APUREG_ROUTING 11 371#define APU_INVERT_POLARITY_B 0x8000 372#define APU_DATASRC_B_MASK 0x7f00 373#define APU_INVERT_POLARITY_A 0x0080 374#define APU_DATASRC_A_MASK 0x007f 375 376#define APU_DATASRC_A_SHIFT 0 377#define APU_DATASRC_B_SHIFT 8 378 379 380/* ----------------------------- 381 * Limits. 382 */ 383#define WPWA_MAXADDR ((1 << 23) - 1) 384#define MAESTRO_MAXADDR ((1 << 28) - 1) 385 386#endif /* MAESTRO_REG_H_INCLUDED */ 387