1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD$"); 31 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/bus.h> 35#include <sys/callout.h> 36#include <sys/conf.h> 37#include <sys/kernel.h> 38#include <sys/kobj.h> 39#include <sys/libkern.h> 40#include <sys/lock.h> 41#include <sys/malloc.h> 42#include <sys/module.h> 43#include <sys/mutex.h> 44#include <sys/resource.h> 45#include <sys/rman.h> 46#include <sys/sysctl.h> 47#include <sys/taskqueue.h> 48 49#include <machine/bus.h> 50#include <machine/resource.h> 51#include <machine/stdarg.h> 52 53#include <dev/mmc/bridge.h> 54#include <dev/mmc/mmcreg.h> 55#include <dev/mmc/mmcbrvar.h> 56 57#include <dev/sdhci/sdhci.h> 58 59#include <cam/cam.h> 60#include <cam/cam_ccb.h> 61#include <cam/cam_debug.h> 62#include <cam/cam_sim.h> 63#include <cam/cam_xpt_sim.h> 64 65#include "mmcbr_if.h" 66#include "sdhci_if.h" 67 68#include "opt_mmccam.h" 69 70SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 71 72static int sdhci_debug = 0; 73SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, 74 "Debug level"); 75u_int sdhci_quirk_clear = 0; 76SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear, 77 0, "Mask of quirks to clear"); 78u_int sdhci_quirk_set = 0; 79SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0, 80 "Mask of quirks to set"); 81 82#define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 83#define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 84#define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 85#define RD_MULTI_4(slot, off, ptr, count) \ 86 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 87 88#define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 89#define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 90#define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 91#define WR_MULTI_4(slot, off, ptr, count) \ 92 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 93 94static void sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err); 95static void sdhci_card_poll(void *arg); 96static void sdhci_card_task(void *arg, int pending); 97static void sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask); 98static void sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask); 99static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset); 100static void sdhci_handle_card_present_locked(struct sdhci_slot *slot, 101 bool is_present); 102static void sdhci_finish_command(struct sdhci_slot *slot); 103static void sdhci_init(struct sdhci_slot *slot); 104static void sdhci_read_block_pio(struct sdhci_slot *slot); 105static void sdhci_req_done(struct sdhci_slot *slot); 106static void sdhci_req_wakeup(struct mmc_request *req); 107static void sdhci_reset(struct sdhci_slot *slot, uint8_t mask); 108static void sdhci_retune(void *arg); 109static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 110static void sdhci_set_power(struct sdhci_slot *slot, u_char power); 111static void sdhci_set_transfer_mode(struct sdhci_slot *slot, 112 const struct mmc_data *data); 113static void sdhci_start(struct sdhci_slot *slot); 114static void sdhci_timeout(void *arg); 115static void sdhci_start_command(struct sdhci_slot *slot, 116 struct mmc_command *cmd); 117static void sdhci_start_data(struct sdhci_slot *slot, 118 const struct mmc_data *data); 119static void sdhci_write_block_pio(struct sdhci_slot *slot); 120static void sdhci_transfer_pio(struct sdhci_slot *slot); 121 122#ifdef MMCCAM 123/* CAM-related */ 124static void sdhci_cam_action(struct cam_sim *sim, union ccb *ccb); 125static int sdhci_cam_get_possible_host_clock(const struct sdhci_slot *slot, 126 int proposed_clock); 127static void sdhci_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb); 128static void sdhci_cam_poll(struct cam_sim *sim); 129static int sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb); 130static int sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb); 131static int sdhci_cam_update_ios(struct sdhci_slot *slot); 132#endif 133 134/* helper routines */ 135static int sdhci_dma_alloc(struct sdhci_slot *slot); 136static void sdhci_dma_free(struct sdhci_slot *slot); 137static void sdhci_dumpregs(struct sdhci_slot *slot); 138static void sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, 139 int error); 140static int slot_printf(const struct sdhci_slot *slot, const char * fmt, ...) 141 __printflike(2, 3); 142static uint32_t sdhci_tuning_intmask(const struct sdhci_slot *slot); 143 144#define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 145#define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 146#define SDHCI_LOCK_INIT(_slot) \ 147 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 148#define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 149#define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 150#define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 151 152#define SDHCI_DEFAULT_MAX_FREQ 50 153 154#define SDHCI_200_MAX_DIVIDER 256 155#define SDHCI_300_MAX_DIVIDER 2046 156 157#define SDHCI_CARD_PRESENT_TICKS (hz / 5) 158#define SDHCI_INSERT_DELAY_TICKS (hz / 2) 159 160/* 161 * Broadcom BCM577xx Controller Constants 162 */ 163/* Maximum divider supported by the default clock source. */ 164#define BCM577XX_DEFAULT_MAX_DIVIDER 256 165/* Alternative clock's base frequency. */ 166#define BCM577XX_ALT_CLOCK_BASE 63000000 167 168#define BCM577XX_HOST_CONTROL 0x198 169#define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF 170#define BCM577XX_CTRL_CLKSEL_SHIFT 12 171#define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 172#define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 173 174static void 175sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 176{ 177 178 if (error != 0) { 179 printf("getaddr: error %d\n", error); 180 return; 181 } 182 *(bus_addr_t *)arg = segs[0].ds_addr; 183} 184 185static int 186slot_printf(const struct sdhci_slot *slot, const char * fmt, ...) 187{ 188 va_list ap; 189 int retval; 190 191 retval = printf("%s-slot%d: ", 192 device_get_nameunit(slot->bus), slot->num); 193 194 va_start(ap, fmt); 195 retval += vprintf(fmt, ap); 196 va_end(ap); 197 return (retval); 198} 199 200static void 201sdhci_dumpregs(struct sdhci_slot *slot) 202{ 203 204 slot_printf(slot, 205 "============== REGISTER DUMP ==============\n"); 206 207 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 208 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 209 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 210 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 211 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 212 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 213 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 214 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 215 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 216 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 217 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 218 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 219 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 220 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 221 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 222 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 223 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2:0x%08x\n", 224 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2)); 225 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n", 226 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2)); 227 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n", 228 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR)); 229 slot_printf(slot, "ADMA addr:0x%08x | Slot int: 0x%08x\n", 230 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS)); 231 232 slot_printf(slot, 233 "===========================================\n"); 234} 235 236static void 237sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 238{ 239 int timeout; 240 uint32_t clock; 241 242 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 243 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot)) 244 return; 245 } 246 247 /* Some controllers need this kick or reset won't work. */ 248 if ((mask & SDHCI_RESET_ALL) == 0 && 249 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 250 /* This is to force an update */ 251 clock = slot->clock; 252 slot->clock = 0; 253 sdhci_set_clock(slot, clock); 254 } 255 256 if (mask & SDHCI_RESET_ALL) { 257 slot->clock = 0; 258 slot->power = 0; 259 } 260 261 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 262 263 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 264 /* 265 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 266 * specification. The reset bit has internal propagation delay, 267 * so a fast read after write returns 0 even if reset process is 268 * in progress. The workaround is to poll for 1 before polling 269 * for 0. In the worst case, if we miss seeing it asserted the 270 * time we spent waiting is enough to ensure the reset finishes. 271 */ 272 timeout = 10000; 273 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 274 if (timeout <= 0) 275 break; 276 timeout--; 277 DELAY(1); 278 } 279 } 280 281 /* Wait max 100 ms */ 282 timeout = 10000; 283 /* Controller clears the bits when it's done */ 284 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 285 if (timeout <= 0) { 286 slot_printf(slot, "Reset 0x%x never completed.\n", 287 mask); 288 sdhci_dumpregs(slot); 289 return; 290 } 291 timeout--; 292 DELAY(10); 293 } 294} 295 296static uint32_t 297sdhci_tuning_intmask(const struct sdhci_slot *slot) 298{ 299 uint32_t intmask; 300 301 intmask = 0; 302 if (slot->opt & SDHCI_TUNING_ENABLED) { 303 intmask |= SDHCI_INT_TUNEERR; 304 if (slot->retune_mode == SDHCI_RETUNE_MODE_2 || 305 slot->retune_mode == SDHCI_RETUNE_MODE_3) 306 intmask |= SDHCI_INT_RETUNE; 307 } 308 return (intmask); 309} 310 311static void 312sdhci_init(struct sdhci_slot *slot) 313{ 314 315 sdhci_reset(slot, SDHCI_RESET_ALL); 316 317 /* Enable interrupts. */ 318 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 319 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 320 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 321 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 322 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 323 SDHCI_INT_ACMD12ERR; 324 325 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 326 !(slot->opt & SDHCI_NON_REMOVABLE)) { 327 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; 328 } 329 330 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 331 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 332} 333 334static void 335sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 336{ 337 uint32_t clk_base; 338 uint32_t clk_sel; 339 uint32_t res; 340 uint16_t clk; 341 uint16_t div; 342 int timeout; 343 344 if (clock == slot->clock) 345 return; 346 slot->clock = clock; 347 348 /* Turn off the clock. */ 349 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 350 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 351 /* If no clock requested - leave it so. */ 352 if (clock == 0) 353 return; 354 355 /* Determine the clock base frequency */ 356 clk_base = slot->max_clk; 357 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { 358 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & 359 BCM577XX_CTRL_CLKSEL_MASK; 360 361 /* 362 * Select clock source appropriate for the requested frequency. 363 */ 364 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) { 365 clk_base = BCM577XX_ALT_CLOCK_BASE; 366 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << 367 BCM577XX_CTRL_CLKSEL_SHIFT); 368 } else { 369 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << 370 BCM577XX_CTRL_CLKSEL_SHIFT); 371 } 372 373 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); 374 } 375 376 /* Recalculate timeout clock frequency based on the new sd clock. */ 377 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 378 slot->timeout_clk = slot->clock / 1000; 379 380 if (slot->version < SDHCI_SPEC_300) { 381 /* Looking for highest freq <= clock. */ 382 res = clk_base; 383 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 384 if (res <= clock) 385 break; 386 res >>= 1; 387 } 388 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 389 div >>= 1; 390 } else { 391 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */ 392 if (clock >= clk_base) 393 div = 0; 394 else { 395 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 396 if ((clk_base / div) <= clock) 397 break; 398 } 399 } 400 div >>= 1; 401 } 402 403 if (bootverbose || sdhci_debug) 404 slot_printf(slot, "Divider %d for freq %d (base %d)\n", 405 div, clock, clk_base); 406 407 /* Now we have got divider, set it. */ 408 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 409 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 410 << SDHCI_DIVIDER_HI_SHIFT; 411 412 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 413 /* Enable clock. */ 414 clk |= SDHCI_CLOCK_INT_EN; 415 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 416 /* Wait up to 10 ms until it stabilize. */ 417 timeout = 10; 418 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 419 & SDHCI_CLOCK_INT_STABLE)) { 420 if (timeout == 0) { 421 slot_printf(slot, 422 "Internal clock never stabilised.\n"); 423 sdhci_dumpregs(slot); 424 return; 425 } 426 timeout--; 427 DELAY(1000); 428 } 429 /* Pass clock signal to the bus. */ 430 clk |= SDHCI_CLOCK_CARD_EN; 431 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 432} 433 434static void 435sdhci_set_power(struct sdhci_slot *slot, u_char power) 436{ 437 int i; 438 uint8_t pwr; 439 440 if (slot->power == power) 441 return; 442 443 slot->power = power; 444 445 /* Turn off the power. */ 446 pwr = 0; 447 WR1(slot, SDHCI_POWER_CONTROL, pwr); 448 /* If power down requested - leave it so. */ 449 if (power == 0) 450 return; 451 /* Set voltage. */ 452 switch (1 << power) { 453 case MMC_OCR_LOW_VOLTAGE: 454 pwr |= SDHCI_POWER_180; 455 break; 456 case MMC_OCR_290_300: 457 case MMC_OCR_300_310: 458 pwr |= SDHCI_POWER_300; 459 break; 460 case MMC_OCR_320_330: 461 case MMC_OCR_330_340: 462 pwr |= SDHCI_POWER_330; 463 break; 464 } 465 WR1(slot, SDHCI_POWER_CONTROL, pwr); 466 /* 467 * Turn on VDD1 power. Note that at least some Intel controllers can 468 * fail to enable bus power on the first try after transiting from D3 469 * to D0, so we give them up to 2 ms. 470 */ 471 pwr |= SDHCI_POWER_ON; 472 for (i = 0; i < 20; i++) { 473 WR1(slot, SDHCI_POWER_CONTROL, pwr); 474 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON) 475 break; 476 DELAY(100); 477 } 478 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)) 479 slot_printf(slot, "Bus power failed to enable\n"); 480 481 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) { 482 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10); 483 DELAY(10); 484 WR1(slot, SDHCI_POWER_CONTROL, pwr); 485 DELAY(300); 486 } 487} 488 489static void 490sdhci_read_block_pio(struct sdhci_slot *slot) 491{ 492 uint32_t data; 493 char *buffer; 494 size_t left; 495 496 buffer = slot->curcmd->data->data; 497 buffer += slot->offset; 498 /* Transfer one block at a time. */ 499 left = min(512, slot->curcmd->data->len - slot->offset); 500 slot->offset += left; 501 502 /* If we are too fast, broken controllers return zeroes. */ 503 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 504 DELAY(10); 505 /* Handle unaligned and aligned buffer cases. */ 506 if ((intptr_t)buffer & 3) { 507 while (left > 3) { 508 data = RD4(slot, SDHCI_BUFFER); 509 buffer[0] = data; 510 buffer[1] = (data >> 8); 511 buffer[2] = (data >> 16); 512 buffer[3] = (data >> 24); 513 buffer += 4; 514 left -= 4; 515 } 516 } else { 517 RD_MULTI_4(slot, SDHCI_BUFFER, 518 (uint32_t *)buffer, left >> 2); 519 left &= 3; 520 } 521 /* Handle uneven size case. */ 522 if (left > 0) { 523 data = RD4(slot, SDHCI_BUFFER); 524 while (left > 0) { 525 *(buffer++) = data; 526 data >>= 8; 527 left--; 528 } 529 } 530} 531 532static void 533sdhci_write_block_pio(struct sdhci_slot *slot) 534{ 535 uint32_t data = 0; 536 char *buffer; 537 size_t left; 538 539 buffer = slot->curcmd->data->data; 540 buffer += slot->offset; 541 /* Transfer one block at a time. */ 542 left = min(512, slot->curcmd->data->len - slot->offset); 543 slot->offset += left; 544 545 /* Handle unaligned and aligned buffer cases. */ 546 if ((intptr_t)buffer & 3) { 547 while (left > 3) { 548 data = buffer[0] + 549 (buffer[1] << 8) + 550 (buffer[2] << 16) + 551 (buffer[3] << 24); 552 left -= 4; 553 buffer += 4; 554 WR4(slot, SDHCI_BUFFER, data); 555 } 556 } else { 557 WR_MULTI_4(slot, SDHCI_BUFFER, 558 (uint32_t *)buffer, left >> 2); 559 left &= 3; 560 } 561 /* Handle uneven size case. */ 562 if (left > 0) { 563 while (left > 0) { 564 data <<= 8; 565 data += *(buffer++); 566 left--; 567 } 568 WR4(slot, SDHCI_BUFFER, data); 569 } 570} 571 572static void 573sdhci_transfer_pio(struct sdhci_slot *slot) 574{ 575 576 /* Read as many blocks as possible. */ 577 if (slot->curcmd->data->flags & MMC_DATA_READ) { 578 while (RD4(slot, SDHCI_PRESENT_STATE) & 579 SDHCI_DATA_AVAILABLE) { 580 sdhci_read_block_pio(slot); 581 if (slot->offset >= slot->curcmd->data->len) 582 break; 583 } 584 } else { 585 while (RD4(slot, SDHCI_PRESENT_STATE) & 586 SDHCI_SPACE_AVAILABLE) { 587 sdhci_write_block_pio(slot); 588 if (slot->offset >= slot->curcmd->data->len) 589 break; 590 } 591 } 592} 593 594static void 595sdhci_card_task(void *arg, int pending __unused) 596{ 597 struct sdhci_slot *slot = arg; 598 device_t d; 599 600 SDHCI_LOCK(slot); 601 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) { 602#ifdef MMCCAM 603 if (slot->card_present == 0) { 604#else 605 if (slot->dev == NULL) { 606#endif 607 /* If card is present - attach mmc bus. */ 608 if (bootverbose || sdhci_debug) 609 slot_printf(slot, "Card inserted\n"); 610#ifdef MMCCAM 611 slot->card_present = 1; 612 union ccb *ccb; 613 uint32_t pathid; 614 pathid = cam_sim_path(slot->sim); 615 ccb = xpt_alloc_ccb_nowait(); 616 if (ccb == NULL) { 617 slot_printf(slot, "Unable to alloc CCB for rescan\n"); 618 SDHCI_UNLOCK(slot); 619 return; 620 } 621 622 /* 623 * We create a rescan request for BUS:0:0, since the card 624 * will be at lun 0. 625 */ 626 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid, 627 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) { 628 slot_printf(slot, "Unable to create path for rescan\n"); 629 SDHCI_UNLOCK(slot); 630 xpt_free_ccb(ccb); 631 return; 632 } 633 SDHCI_UNLOCK(slot); 634 xpt_rescan(ccb); 635#else 636 d = slot->dev = device_add_child(slot->bus, "mmc", -1); 637 SDHCI_UNLOCK(slot); 638 if (d) { 639 device_set_ivars(d, slot); 640 (void)device_probe_and_attach(d); 641 } 642#endif 643 } else 644 SDHCI_UNLOCK(slot); 645 } else { 646#ifdef MMCCAM 647 if (slot->card_present == 1) { 648#else 649 if (slot->dev != NULL) { 650#endif 651 /* If no card present - detach mmc bus. */ 652 if (bootverbose || sdhci_debug) 653 slot_printf(slot, "Card removed\n"); 654 d = slot->dev; 655 slot->dev = NULL; 656#ifdef MMCCAM 657 slot->card_present = 0; 658 union ccb *ccb; 659 uint32_t pathid; 660 pathid = cam_sim_path(slot->sim); 661 ccb = xpt_alloc_ccb_nowait(); 662 if (ccb == NULL) { 663 slot_printf(slot, "Unable to alloc CCB for rescan\n"); 664 SDHCI_UNLOCK(slot); 665 return; 666 } 667 668 /* 669 * We create a rescan request for BUS:0:0, since the card 670 * will be at lun 0. 671 */ 672 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid, 673 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) { 674 slot_printf(slot, "Unable to create path for rescan\n"); 675 SDHCI_UNLOCK(slot); 676 xpt_free_ccb(ccb); 677 return; 678 } 679 SDHCI_UNLOCK(slot); 680 xpt_rescan(ccb); 681#else 682 slot->intmask &= ~sdhci_tuning_intmask(slot); 683 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 684 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 685 slot->opt &= ~SDHCI_TUNING_ENABLED; 686 SDHCI_UNLOCK(slot); 687 callout_drain(&slot->retune_callout); 688 device_delete_child(slot->bus, d); 689#endif 690 } else 691 SDHCI_UNLOCK(slot); 692 } 693} 694 695static void 696sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present) 697{ 698 bool was_present; 699 700 /* 701 * If there was no card and now there is one, schedule the task to 702 * create the child device after a short delay. The delay is to 703 * debounce the card insert (sometimes the card detect pin stabilizes 704 * before the other pins have made good contact). 705 * 706 * If there was a card present and now it's gone, immediately schedule 707 * the task to delete the child device. No debouncing -- gone is gone, 708 * because once power is removed, a full card re-init is needed, and 709 * that happens by deleting and recreating the child device. 710 */ 711#ifdef MMCCAM 712 was_present = slot->card_present; 713#else 714 was_present = slot->dev != NULL; 715#endif 716 if (!was_present && is_present) { 717 taskqueue_enqueue_timeout(taskqueue_swi_giant, 718 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS); 719 } else if (was_present && !is_present) { 720 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 721 } 722} 723 724void 725sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present) 726{ 727 728 SDHCI_LOCK(slot); 729 sdhci_handle_card_present_locked(slot, is_present); 730 SDHCI_UNLOCK(slot); 731} 732 733static void 734sdhci_card_poll(void *arg) 735{ 736 struct sdhci_slot *slot = arg; 737 738 sdhci_handle_card_present(slot, 739 SDHCI_GET_CARD_PRESENT(slot->bus, slot)); 740 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS, 741 sdhci_card_poll, slot); 742} 743 744static int 745sdhci_dma_alloc(struct sdhci_slot *slot) 746{ 747 int err; 748 749 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY)) { 750 if (MAXPHYS <= 1024 * 4) 751 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_4K; 752 else if (MAXPHYS <= 1024 * 8) 753 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_8K; 754 else if (MAXPHYS <= 1024 * 16) 755 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_16K; 756 else if (MAXPHYS <= 1024 * 32) 757 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_32K; 758 else if (MAXPHYS <= 1024 * 64) 759 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_64K; 760 else if (MAXPHYS <= 1024 * 128) 761 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_128K; 762 else if (MAXPHYS <= 1024 * 256) 763 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_256K; 764 else 765 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_512K; 766 } 767 slot->sdma_bbufsz = SDHCI_SDMA_BNDRY_TO_BBUFSZ(slot->sdma_boundary); 768 769 /* 770 * Allocate the DMA tag for an SDMA bounce buffer. 771 * Note that the SDHCI specification doesn't state any alignment 772 * constraint for the SDMA system address. However, controllers 773 * typically ignore the SDMA boundary bits in SDHCI_DMA_ADDRESS when 774 * forming the actual address of data, requiring the SDMA buffer to 775 * be aligned to the SDMA boundary. 776 */ 777 err = bus_dma_tag_create(bus_get_dma_tag(slot->bus), slot->sdma_bbufsz, 778 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 779 slot->sdma_bbufsz, 1, slot->sdma_bbufsz, BUS_DMA_ALLOCNOW, 780 NULL, NULL, &slot->dmatag); 781 if (err != 0) { 782 slot_printf(slot, "Can't create DMA tag for SDMA\n"); 783 return (err); 784 } 785 /* Allocate DMA memory for the SDMA bounce buffer. */ 786 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 787 BUS_DMA_NOWAIT, &slot->dmamap); 788 if (err != 0) { 789 slot_printf(slot, "Can't alloc DMA memory for SDMA\n"); 790 bus_dma_tag_destroy(slot->dmatag); 791 return (err); 792 } 793 /* Map the memory of the SDMA bounce buffer. */ 794 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 795 (void *)slot->dmamem, slot->sdma_bbufsz, sdhci_getaddr, 796 &slot->paddr, 0); 797 if (err != 0 || slot->paddr == 0) { 798 slot_printf(slot, "Can't load DMA memory for SDMA\n"); 799 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 800 bus_dma_tag_destroy(slot->dmatag); 801 if (err) 802 return (err); 803 else 804 return (EFAULT); 805 } 806 807 return (0); 808} 809 810static void 811sdhci_dma_free(struct sdhci_slot *slot) 812{ 813 814 bus_dmamap_unload(slot->dmatag, slot->dmamap); 815 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 816 bus_dma_tag_destroy(slot->dmatag); 817} 818 819int 820sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 821{ 822 kobjop_desc_t kobj_desc; 823 kobj_method_t *kobj_method; 824 uint32_t caps, caps2, freq, host_caps; 825 int err; 826 827 SDHCI_LOCK_INIT(slot); 828 829 slot->num = num; 830 slot->bus = dev; 831 832 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 833 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 834 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) { 835 caps = slot->caps; 836 caps2 = slot->caps2; 837 } else { 838 caps = RD4(slot, SDHCI_CAPABILITIES); 839 if (slot->version >= SDHCI_SPEC_300) 840 caps2 = RD4(slot, SDHCI_CAPABILITIES2); 841 else 842 caps2 = 0; 843 } 844 if (slot->version >= SDHCI_SPEC_300) { 845 if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE && 846 (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) { 847 slot_printf(slot, 848 "Driver doesn't support shared bus slots\n"); 849 SDHCI_LOCK_DESTROY(slot); 850 return (ENXIO); 851 } else if ((caps & SDHCI_SLOTTYPE_MASK) == 852 SDHCI_SLOTTYPE_EMBEDDED) { 853 slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE; 854 } 855 } 856 /* Calculate base clock frequency. */ 857 if (slot->version >= SDHCI_SPEC_300) 858 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 859 SDHCI_CLOCK_BASE_SHIFT; 860 else 861 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 862 SDHCI_CLOCK_BASE_SHIFT; 863 if (freq != 0) 864 slot->max_clk = freq * 1000000; 865 /* 866 * If the frequency wasn't in the capabilities and the hardware driver 867 * hasn't already set max_clk we're probably not going to work right 868 * with an assumption, so complain about it. 869 */ 870 if (slot->max_clk == 0) { 871 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 872 slot_printf(slot, "Hardware doesn't specify base clock " 873 "frequency, using %dMHz as default.\n", 874 SDHCI_DEFAULT_MAX_FREQ); 875 } 876 /* Calculate/set timeout clock frequency. */ 877 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 878 slot->timeout_clk = slot->max_clk / 1000; 879 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) { 880 slot->timeout_clk = 1000; 881 } else { 882 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >> 883 SDHCI_TIMEOUT_CLK_SHIFT; 884 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 885 slot->timeout_clk *= 1000; 886 } 887 /* 888 * If the frequency wasn't in the capabilities and the hardware driver 889 * hasn't already set timeout_clk we'll probably work okay using the 890 * max timeout, but still mention it. 891 */ 892 if (slot->timeout_clk == 0) { 893 slot_printf(slot, "Hardware doesn't specify timeout clock " 894 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 895 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 896 } 897 898 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 899 slot->host.f_max = slot->max_clk; 900 slot->host.host_ocr = 0; 901 if (caps & SDHCI_CAN_VDD_330) 902 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 903 if (caps & SDHCI_CAN_VDD_300) 904 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 905 /* 906 * 1.8V VDD is not supposed to be used for removable cards. Hardware 907 * prior to v3.0 had no way to indicate embedded slots, but did 908 * sometimes support 1.8v for non-removable devices. 909 */ 910 if ((caps & SDHCI_CAN_VDD_180) && (slot->version < SDHCI_SPEC_300 || 911 (slot->opt & SDHCI_SLOT_EMBEDDED))) 912 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 913 if (slot->host.host_ocr == 0) { 914 slot_printf(slot, "Hardware doesn't report any " 915 "support voltages.\n"); 916 } 917 918 host_caps = MMC_CAP_4_BIT_DATA; 919 if (caps & SDHCI_CAN_DO_8BITBUS) 920 host_caps |= MMC_CAP_8_BIT_DATA; 921 if (caps & SDHCI_CAN_DO_HISPD) 922 host_caps |= MMC_CAP_HSPEED; 923 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC) 924 host_caps |= MMC_CAP_BOOT_NOACC; 925 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY) 926 host_caps |= MMC_CAP_WAIT_WHILE_BUSY; 927 928 /* Determine supported UHS-I and eMMC modes. */ 929 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50)) 930 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 931 if (caps2 & SDHCI_CAN_SDR104) { 932 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 933 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200)) 934 host_caps |= MMC_CAP_MMC_HS200; 935 } else if (caps2 & SDHCI_CAN_SDR50) 936 host_caps |= MMC_CAP_UHS_SDR50; 937 if (caps2 & SDHCI_CAN_DDR50 && 938 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50)) 939 host_caps |= MMC_CAP_UHS_DDR50; 940 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52) 941 host_caps |= MMC_CAP_MMC_DDR52; 942 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 && 943 caps2 & SDHCI_CAN_MMC_HS400) 944 host_caps |= MMC_CAP_MMC_HS400; 945 if (slot->quirks & SDHCI_QUIRK_MMC_HS400_IF_CAN_SDR104 && 946 caps2 & SDHCI_CAN_SDR104) 947 host_caps |= MMC_CAP_MMC_HS400; 948 949 /* 950 * Disable UHS-I and eMMC modes if the set_uhs_timing method is the 951 * default NULL implementation. 952 */ 953 kobj_desc = &sdhci_set_uhs_timing_desc; 954 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 955 kobj_desc); 956 if (kobj_method == &kobj_desc->deflt) 957 host_caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 958 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | 959 MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | MMC_CAP_MMC_HS400); 960 961#define SDHCI_CAP_MODES_TUNING(caps2) \ 962 (((caps2) & SDHCI_TUNE_SDR50 ? MMC_CAP_UHS_SDR50 : 0) | \ 963 MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_HS200 | \ 964 MMC_CAP_MMC_HS400) 965 966 /* 967 * Disable UHS-I and eMMC modes that require (re-)tuning if either 968 * the tune or re-tune method is the default NULL implementation. 969 */ 970 kobj_desc = &mmcbr_tune_desc; 971 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 972 kobj_desc); 973 if (kobj_method == &kobj_desc->deflt) 974 goto no_tuning; 975 kobj_desc = &mmcbr_retune_desc; 976 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 977 kobj_desc); 978 if (kobj_method == &kobj_desc->deflt) { 979no_tuning: 980 host_caps &= ~(SDHCI_CAP_MODES_TUNING(caps2)); 981 } 982 983 /* Allocate tuning structures and determine tuning parameters. */ 984 if (host_caps & SDHCI_CAP_MODES_TUNING(caps2)) { 985 slot->opt |= SDHCI_TUNING_SUPPORTED; 986 slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF, 987 M_WAITOK); 988 slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF, 989 M_WAITOK); 990 slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF, 991 M_WAITOK); 992 if (caps2 & SDHCI_TUNE_SDR50) 993 slot->opt |= SDHCI_SDR50_NEEDS_TUNING; 994 slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >> 995 SDHCI_RETUNE_MODES_SHIFT; 996 if (slot->retune_mode == SDHCI_RETUNE_MODE_1) { 997 slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >> 998 SDHCI_RETUNE_CNT_SHIFT; 999 if (slot->retune_count > 0xb) { 1000 slot_printf(slot, "Unknown re-tuning count " 1001 "%x, using 1 sec\n", slot->retune_count); 1002 slot->retune_count = 1; 1003 } else if (slot->retune_count != 0) 1004 slot->retune_count = 1005 1 << (slot->retune_count - 1); 1006 } 1007 } 1008 1009#undef SDHCI_CAP_MODES_TUNING 1010 1011 /* Determine supported VCCQ signaling levels. */ 1012 host_caps |= MMC_CAP_SIGNALING_330; 1013 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 1014 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | 1015 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 | 1016 MMC_CAP_MMC_HS400_180)) 1017 host_caps |= MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180; 1018 1019 /* 1020 * Disable 1.2 V and 1.8 V signaling if the switch_vccq method is the 1021 * default NULL implementation. Disable 1.2 V support if it's the 1022 * generic SDHCI implementation. 1023 */ 1024 kobj_desc = &mmcbr_switch_vccq_desc; 1025 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 1026 kobj_desc); 1027 if (kobj_method == &kobj_desc->deflt) 1028 host_caps &= ~(MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180); 1029 else if (kobj_method->func == (kobjop_t)sdhci_generic_switch_vccq) 1030 host_caps &= ~MMC_CAP_SIGNALING_120; 1031 1032 /* Determine supported driver types (type B is always mandatory). */ 1033 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A) 1034 host_caps |= MMC_CAP_DRIVER_TYPE_A; 1035 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C) 1036 host_caps |= MMC_CAP_DRIVER_TYPE_C; 1037 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D) 1038 host_caps |= MMC_CAP_DRIVER_TYPE_D; 1039 slot->host.caps = host_caps; 1040 1041 /* Decide if we have usable DMA. */ 1042 if (caps & SDHCI_CAN_DO_DMA) 1043 slot->opt |= SDHCI_HAVE_DMA; 1044 1045 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 1046 slot->opt &= ~SDHCI_HAVE_DMA; 1047 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 1048 slot->opt |= SDHCI_HAVE_DMA; 1049 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE) 1050 slot->opt |= SDHCI_NON_REMOVABLE; 1051 1052 /* 1053 * Use platform-provided transfer backend 1054 * with PIO as a fallback mechanism 1055 */ 1056 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 1057 slot->opt &= ~SDHCI_HAVE_DMA; 1058 1059 if (slot->opt & SDHCI_HAVE_DMA) { 1060 err = sdhci_dma_alloc(slot); 1061 if (err != 0) { 1062 if (slot->opt & SDHCI_TUNING_SUPPORTED) { 1063 free(slot->tune_req, M_DEVBUF); 1064 free(slot->tune_cmd, M_DEVBUF); 1065 free(slot->tune_data, M_DEVBUF); 1066 } 1067 SDHCI_LOCK_DESTROY(slot); 1068 return (err); 1069 } 1070 } 1071 1072 if (bootverbose || sdhci_debug) { 1073 slot_printf(slot, 1074 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s %s\n", 1075 slot->max_clk / 1000000, 1076 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 1077 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" : 1078 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"), 1079 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 1080 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 1081 ((caps & SDHCI_CAN_VDD_180) && 1082 (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "", 1083 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "", 1084 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "", 1085 (host_caps & MMC_CAP_DRIVER_TYPE_A) ? "A" : "", 1086 (host_caps & MMC_CAP_DRIVER_TYPE_C) ? "C" : "", 1087 (host_caps & MMC_CAP_DRIVER_TYPE_D) ? "D" : "", 1088 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO", 1089 (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" : 1090 (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" : 1091 "removable"); 1092 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | 1093 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) 1094 slot_printf(slot, "eMMC:%s%s%s%s\n", 1095 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "", 1096 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "", 1097 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "", 1098 ((host_caps & 1099 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) == 1100 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ? 1101 " HS400ES" : ""); 1102 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 1103 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)) 1104 slot_printf(slot, "UHS-I:%s%s%s%s%s\n", 1105 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "", 1106 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "", 1107 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "", 1108 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "", 1109 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : ""); 1110 if (slot->opt & SDHCI_TUNING_SUPPORTED) 1111 slot_printf(slot, "Re-tuning count %d secs, mode %d\n", 1112 slot->retune_count, slot->retune_mode + 1); 1113 sdhci_dumpregs(slot); 1114 } 1115 1116 slot->timeout = 10; 1117 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus), 1118 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO, 1119 "timeout", CTLFLAG_RWTUN, &slot->timeout, 0, 1120 "Maximum timeout for SDHCI transfers (in secs)"); 1121 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 1122 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0, 1123 sdhci_card_task, slot); 1124 callout_init(&slot->card_poll_callout, 1); 1125 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0); 1126 callout_init_mtx(&slot->retune_callout, &slot->mtx, 0); 1127 1128 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 1129 !(slot->opt & SDHCI_NON_REMOVABLE)) { 1130 callout_reset(&slot->card_poll_callout, 1131 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot); 1132 } 1133 1134 sdhci_init(slot); 1135 1136 return (0); 1137} 1138 1139#ifndef MMCCAM 1140void 1141sdhci_start_slot(struct sdhci_slot *slot) 1142{ 1143 1144 sdhci_card_task(slot, 0); 1145} 1146#endif 1147 1148int 1149sdhci_cleanup_slot(struct sdhci_slot *slot) 1150{ 1151 device_t d; 1152 1153 callout_drain(&slot->timeout_callout); 1154 callout_drain(&slot->card_poll_callout); 1155 callout_drain(&slot->retune_callout); 1156 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 1157 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task); 1158 1159 SDHCI_LOCK(slot); 1160 d = slot->dev; 1161 slot->dev = NULL; 1162 SDHCI_UNLOCK(slot); 1163 if (d != NULL) 1164 device_delete_child(slot->bus, d); 1165 1166 SDHCI_LOCK(slot); 1167 sdhci_reset(slot, SDHCI_RESET_ALL); 1168 SDHCI_UNLOCK(slot); 1169 if (slot->opt & SDHCI_HAVE_DMA) 1170 sdhci_dma_free(slot); 1171 if (slot->opt & SDHCI_TUNING_SUPPORTED) { 1172 free(slot->tune_req, M_DEVBUF); 1173 free(slot->tune_cmd, M_DEVBUF); 1174 free(slot->tune_data, M_DEVBUF); 1175 } 1176 1177 SDHCI_LOCK_DESTROY(slot); 1178 1179 return (0); 1180} 1181 1182int 1183sdhci_generic_suspend(struct sdhci_slot *slot) 1184{ 1185 1186 /* 1187 * We expect the MMC layer to issue initial tuning after resume. 1188 * Otherwise, we'd need to indicate re-tuning including circuit reset 1189 * being required at least for re-tuning modes 1 and 2 ourselves. 1190 */ 1191 callout_drain(&slot->retune_callout); 1192 SDHCI_LOCK(slot); 1193 slot->opt &= ~SDHCI_TUNING_ENABLED; 1194 sdhci_reset(slot, SDHCI_RESET_ALL); 1195 SDHCI_UNLOCK(slot); 1196 1197 return (0); 1198} 1199 1200int 1201sdhci_generic_resume(struct sdhci_slot *slot) 1202{ 1203 1204 SDHCI_LOCK(slot); 1205 sdhci_init(slot); 1206 SDHCI_UNLOCK(slot); 1207 1208 return (0); 1209} 1210 1211uint32_t 1212sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot) 1213{ 1214 1215 if (slot->version >= SDHCI_SPEC_300) 1216 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 1217 else 1218 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 1219} 1220 1221bool 1222sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot) 1223{ 1224 1225 if (slot->opt & SDHCI_NON_REMOVABLE) 1226 return true; 1227 1228 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 1229} 1230 1231void 1232sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot) 1233{ 1234 const struct mmc_ios *ios; 1235 uint16_t hostctrl2; 1236 1237 if (slot->version < SDHCI_SPEC_300) 1238 return; 1239 1240 SDHCI_ASSERT_LOCKED(slot); 1241 ios = &slot->host.ios; 1242 sdhci_set_clock(slot, 0); 1243 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1244 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK; 1245 if (ios->clock > SD_SDR50_MAX) { 1246 if (ios->timing == bus_timing_mmc_hs400 || 1247 ios->timing == bus_timing_mmc_hs400es) 1248 hostctrl2 |= SDHCI_CTRL2_MMC_HS400; 1249 else 1250 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104; 1251 } 1252 else if (ios->clock > SD_SDR25_MAX) 1253 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50; 1254 else if (ios->clock > SD_SDR12_MAX) { 1255 if (ios->timing == bus_timing_uhs_ddr50 || 1256 ios->timing == bus_timing_mmc_ddr52) 1257 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50; 1258 else 1259 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25; 1260 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) 1261 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12; 1262 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1263 sdhci_set_clock(slot, ios->clock); 1264} 1265 1266int 1267sdhci_generic_update_ios(device_t brdev, device_t reqdev) 1268{ 1269 struct sdhci_slot *slot = device_get_ivars(reqdev); 1270 struct mmc_ios *ios = &slot->host.ios; 1271 1272 SDHCI_LOCK(slot); 1273 /* Do full reset on bus power down to clear from any state. */ 1274 if (ios->power_mode == power_off) { 1275 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 1276 sdhci_init(slot); 1277 } 1278 /* Configure the bus. */ 1279 sdhci_set_clock(slot, ios->clock); 1280 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 1281 if (ios->bus_width == bus_width_8) { 1282 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 1283 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 1284 } else if (ios->bus_width == bus_width_4) { 1285 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 1286 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 1287 } else if (ios->bus_width == bus_width_1) { 1288 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 1289 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 1290 } else { 1291 panic("Invalid bus width: %d", ios->bus_width); 1292 } 1293 if (ios->clock > SD_SDR12_MAX && 1294 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 1295 slot->hostctrl |= SDHCI_CTRL_HISPD; 1296 else 1297 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 1298 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 1299 SDHCI_SET_UHS_TIMING(brdev, slot); 1300 /* Some controllers like reset after bus changes. */ 1301 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 1302 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1303 1304 SDHCI_UNLOCK(slot); 1305 return (0); 1306} 1307 1308int 1309sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev) 1310{ 1311 struct sdhci_slot *slot = device_get_ivars(reqdev); 1312 enum mmc_vccq vccq; 1313 int err; 1314 uint16_t hostctrl2; 1315 1316 if (slot->version < SDHCI_SPEC_300) 1317 return (0); 1318 1319 err = 0; 1320 vccq = slot->host.ios.vccq; 1321 SDHCI_LOCK(slot); 1322 sdhci_set_clock(slot, 0); 1323 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1324 switch (vccq) { 1325 case vccq_330: 1326 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 1327 goto done; 1328 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE; 1329 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1330 DELAY(5000); 1331 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1332 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 1333 goto done; 1334 err = EAGAIN; 1335 break; 1336 case vccq_180: 1337 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) { 1338 err = EINVAL; 1339 goto done; 1340 } 1341 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1342 goto done; 1343 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE; 1344 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1345 DELAY(5000); 1346 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1347 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1348 goto done; 1349 err = EAGAIN; 1350 break; 1351 default: 1352 slot_printf(slot, 1353 "Attempt to set unsupported signaling voltage\n"); 1354 err = EINVAL; 1355 break; 1356 } 1357done: 1358 sdhci_set_clock(slot, slot->host.ios.clock); 1359 SDHCI_UNLOCK(slot); 1360 return (err); 1361} 1362 1363int 1364sdhci_generic_tune(device_t brdev __unused, device_t reqdev, bool hs400) 1365{ 1366 struct sdhci_slot *slot = device_get_ivars(reqdev); 1367 const struct mmc_ios *ios = &slot->host.ios; 1368 struct mmc_command *tune_cmd; 1369 struct mmc_data *tune_data; 1370 uint32_t opcode; 1371 int err; 1372 1373 if (!(slot->opt & SDHCI_TUNING_SUPPORTED)) 1374 return (0); 1375 1376 slot->retune_ticks = slot->retune_count * hz; 1377 opcode = MMC_SEND_TUNING_BLOCK; 1378 SDHCI_LOCK(slot); 1379 switch (ios->timing) { 1380 case bus_timing_mmc_hs400: 1381 slot_printf(slot, "HS400 must be tuned in HS200 mode\n"); 1382 SDHCI_UNLOCK(slot); 1383 return (EINVAL); 1384 case bus_timing_mmc_hs200: 1385 /* 1386 * In HS400 mode, controllers use the data strobe line to 1387 * latch data from the devices so periodic re-tuning isn't 1388 * expected to be required. 1389 */ 1390 if (hs400) 1391 slot->retune_ticks = 0; 1392 opcode = MMC_SEND_TUNING_BLOCK_HS200; 1393 break; 1394 case bus_timing_uhs_ddr50: 1395 case bus_timing_uhs_sdr104: 1396 break; 1397 case bus_timing_uhs_sdr50: 1398 if (slot->opt & SDHCI_SDR50_NEEDS_TUNING) 1399 break; 1400 /* FALLTHROUGH */ 1401 default: 1402 SDHCI_UNLOCK(slot); 1403 return (0); 1404 } 1405 1406 tune_cmd = slot->tune_cmd; 1407 memset(tune_cmd, 0, sizeof(*tune_cmd)); 1408 tune_cmd->opcode = opcode; 1409 tune_cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1410 tune_data = tune_cmd->data = slot->tune_data; 1411 memset(tune_data, 0, sizeof(*tune_data)); 1412 tune_data->len = (opcode == MMC_SEND_TUNING_BLOCK_HS200 && 1413 ios->bus_width == bus_width_8) ? MMC_TUNING_LEN_HS200 : 1414 MMC_TUNING_LEN; 1415 tune_data->flags = MMC_DATA_READ; 1416 tune_data->mrq = tune_cmd->mrq = slot->tune_req; 1417 1418 slot->opt &= ~SDHCI_TUNING_ENABLED; 1419 err = sdhci_exec_tuning(slot, true); 1420 if (err == 0) { 1421 slot->opt |= SDHCI_TUNING_ENABLED; 1422 slot->intmask |= sdhci_tuning_intmask(slot); 1423 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 1424 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1425 if (slot->retune_ticks) { 1426 callout_reset(&slot->retune_callout, slot->retune_ticks, 1427 sdhci_retune, slot); 1428 } 1429 } 1430 SDHCI_UNLOCK(slot); 1431 return (err); 1432} 1433 1434int 1435sdhci_generic_retune(device_t brdev __unused, device_t reqdev, bool reset) 1436{ 1437 struct sdhci_slot *slot = device_get_ivars(reqdev); 1438 int err; 1439 1440 if (!(slot->opt & SDHCI_TUNING_ENABLED)) 1441 return (0); 1442 1443 /* HS400 must be tuned in HS200 mode. */ 1444 if (slot->host.ios.timing == bus_timing_mmc_hs400) 1445 return (EINVAL); 1446 1447 SDHCI_LOCK(slot); 1448 err = sdhci_exec_tuning(slot, reset); 1449 /* 1450 * There are two ways sdhci_exec_tuning() can fail: 1451 * EBUSY should not actually happen when requests are only issued 1452 * with the host properly acquired, and 1453 * EIO re-tuning failed (but it did work initially). 1454 * 1455 * In both cases, we should retry at later point if periodic re-tuning 1456 * is enabled. Note that due to slot->retune_req not being cleared in 1457 * these failure cases, the MMC layer should trigger another attempt at 1458 * re-tuning with the next request anyway, though. 1459 */ 1460 if (slot->retune_ticks) { 1461 callout_reset(&slot->retune_callout, slot->retune_ticks, 1462 sdhci_retune, slot); 1463 } 1464 SDHCI_UNLOCK(slot); 1465 return (err); 1466} 1467 1468static int 1469sdhci_exec_tuning(struct sdhci_slot *slot, bool reset) 1470{ 1471 struct mmc_request *tune_req; 1472 struct mmc_command *tune_cmd; 1473 int i; 1474 uint32_t intmask; 1475 uint16_t hostctrl2; 1476 u_char opt; 1477 1478 SDHCI_ASSERT_LOCKED(slot); 1479 if (slot->req != NULL) 1480 return (EBUSY); 1481 1482 /* Tuning doesn't work with DMA enabled. */ 1483 opt = slot->opt; 1484 slot->opt = opt & ~SDHCI_HAVE_DMA; 1485 1486 /* 1487 * Ensure that as documented, SDHCI_INT_DATA_AVAIL is the only 1488 * kind of interrupt we receive in response to a tuning request. 1489 */ 1490 intmask = slot->intmask; 1491 slot->intmask = SDHCI_INT_DATA_AVAIL; 1492 WR4(slot, SDHCI_INT_ENABLE, SDHCI_INT_DATA_AVAIL); 1493 WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL); 1494 1495 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1496 if (reset) 1497 hostctrl2 &= ~SDHCI_CTRL2_SAMPLING_CLOCK; 1498 else 1499 hostctrl2 |= SDHCI_CTRL2_SAMPLING_CLOCK; 1500 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING); 1501 1502 tune_req = slot->tune_req; 1503 tune_cmd = slot->tune_cmd; 1504 for (i = 0; i < MMC_TUNING_MAX; i++) { 1505 memset(tune_req, 0, sizeof(*tune_req)); 1506 tune_req->cmd = tune_cmd; 1507 tune_req->done = sdhci_req_wakeup; 1508 tune_req->done_data = slot; 1509 slot->req = tune_req; 1510 slot->flags = 0; 1511 sdhci_start(slot); 1512 while (!(tune_req->flags & MMC_REQ_DONE)) 1513 msleep(tune_req, &slot->mtx, 0, "sdhciet", 0); 1514 if (!(tune_req->flags & MMC_TUNE_DONE)) 1515 break; 1516 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1517 if (!(hostctrl2 & SDHCI_CTRL2_EXEC_TUNING)) 1518 break; 1519 if (tune_cmd->opcode == MMC_SEND_TUNING_BLOCK) 1520 DELAY(1000); 1521 } 1522 1523 /* 1524 * Restore DMA usage and interrupts. 1525 * Note that the interrupt aggregation code might have cleared 1526 * SDHCI_INT_DMA_END and/or SDHCI_INT_RESPONSE in slot->intmask 1527 * and SDHCI_SIGNAL_ENABLE respectively so ensure SDHCI_INT_ENABLE 1528 * doesn't lose these. 1529 */ 1530 slot->opt = opt; 1531 slot->intmask = intmask; 1532 WR4(slot, SDHCI_INT_ENABLE, intmask | SDHCI_INT_DMA_END | 1533 SDHCI_INT_RESPONSE); 1534 WR4(slot, SDHCI_SIGNAL_ENABLE, intmask); 1535 1536 if ((hostctrl2 & (SDHCI_CTRL2_EXEC_TUNING | 1537 SDHCI_CTRL2_SAMPLING_CLOCK)) == SDHCI_CTRL2_SAMPLING_CLOCK) { 1538 slot->retune_req = 0; 1539 return (0); 1540 } 1541 1542 slot_printf(slot, "Tuning failed, using fixed sampling clock\n"); 1543 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING | 1544 SDHCI_CTRL2_SAMPLING_CLOCK)); 1545 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1546 return (EIO); 1547} 1548 1549static void 1550sdhci_retune(void *arg) 1551{ 1552 struct sdhci_slot *slot = arg; 1553 1554 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED; 1555} 1556 1557#ifdef MMCCAM 1558static void 1559sdhci_req_done(struct sdhci_slot *slot) 1560{ 1561 union ccb *ccb; 1562 1563 if (__predict_false(sdhci_debug > 1)) 1564 slot_printf(slot, "%s\n", __func__); 1565 if (slot->ccb != NULL && slot->curcmd != NULL) { 1566 callout_stop(&slot->timeout_callout); 1567 ccb = slot->ccb; 1568 slot->ccb = NULL; 1569 slot->curcmd = NULL; 1570 1571 /* Tell CAM the request is finished */ 1572 struct ccb_mmcio *mmcio; 1573 mmcio = &ccb->mmcio; 1574 1575 ccb->ccb_h.status = 1576 (mmcio->cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 1577 xpt_done(ccb); 1578 } 1579} 1580#else 1581static void 1582sdhci_req_done(struct sdhci_slot *slot) 1583{ 1584 struct mmc_request *req; 1585 1586 if (slot->req != NULL && slot->curcmd != NULL) { 1587 callout_stop(&slot->timeout_callout); 1588 req = slot->req; 1589 slot->req = NULL; 1590 slot->curcmd = NULL; 1591 req->done(req); 1592 } 1593} 1594#endif 1595 1596static void 1597sdhci_req_wakeup(struct mmc_request *req) 1598{ 1599 struct sdhci_slot *slot; 1600 1601 slot = req->done_data; 1602 req->flags |= MMC_REQ_DONE; 1603 wakeup(req); 1604} 1605 1606static void 1607sdhci_timeout(void *arg) 1608{ 1609 struct sdhci_slot *slot = arg; 1610 1611 if (slot->curcmd != NULL) { 1612 slot_printf(slot, "Controller timeout\n"); 1613 sdhci_dumpregs(slot); 1614 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1615 slot->curcmd->error = MMC_ERR_TIMEOUT; 1616 sdhci_req_done(slot); 1617 } else { 1618 slot_printf(slot, "Spurious timeout - no active command\n"); 1619 } 1620} 1621 1622static void 1623sdhci_set_transfer_mode(struct sdhci_slot *slot, const struct mmc_data *data) 1624{ 1625 uint16_t mode; 1626 1627 if (data == NULL) 1628 return; 1629 1630 mode = SDHCI_TRNS_BLK_CNT_EN; 1631 if (data->len > 512) { 1632 mode |= SDHCI_TRNS_MULTI; 1633 if (__predict_true( 1634#ifdef MMCCAM 1635 slot->ccb->mmcio.stop.opcode == MMC_STOP_TRANSMISSION && 1636#else 1637 slot->req->stop != NULL && 1638#endif 1639 !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP))) 1640 mode |= SDHCI_TRNS_ACMD12; 1641 } 1642 if (data->flags & MMC_DATA_READ) 1643 mode |= SDHCI_TRNS_READ; 1644 if (slot->flags & SDHCI_USE_DMA) 1645 mode |= SDHCI_TRNS_DMA; 1646 1647 WR2(slot, SDHCI_TRANSFER_MODE, mode); 1648} 1649 1650static void 1651sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 1652{ 1653 int flags, timeout; 1654 uint32_t mask; 1655 1656 slot->curcmd = cmd; 1657 slot->cmd_done = 0; 1658 1659 cmd->error = MMC_ERR_NONE; 1660 1661 /* This flags combination is not supported by controller. */ 1662 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1663 slot_printf(slot, "Unsupported response type!\n"); 1664 cmd->error = MMC_ERR_FAILED; 1665 sdhci_req_done(slot); 1666 return; 1667 } 1668 1669 /* 1670 * Do not issue command if there is no card, clock or power. 1671 * Controller will not detect timeout without clock active. 1672 */ 1673 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) || 1674 slot->power == 0 || 1675 slot->clock == 0) { 1676 slot_printf(slot, 1677 "Cannot issue a command (power=%d clock=%d)", 1678 slot->power, slot->clock); 1679 cmd->error = MMC_ERR_FAILED; 1680 sdhci_req_done(slot); 1681 return; 1682 } 1683 /* Always wait for free CMD bus. */ 1684 mask = SDHCI_CMD_INHIBIT; 1685 /* Wait for free DAT if we have data or busy signal. */ 1686 if (cmd->data != NULL || (cmd->flags & MMC_RSP_BUSY)) 1687 mask |= SDHCI_DAT_INHIBIT; 1688 /* 1689 * We shouldn't wait for DAT for stop commands or CMD19/CMD21. Note 1690 * that these latter are also special in that SDHCI_CMD_DATA should 1691 * be set below but no actual data is ever read from the controller. 1692 */ 1693#ifdef MMCCAM 1694 if (cmd == &slot->ccb->mmcio.stop || 1695#else 1696 if (cmd == slot->req->stop || 1697#endif 1698 __predict_false(cmd->opcode == MMC_SEND_TUNING_BLOCK || 1699 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)) 1700 mask &= ~SDHCI_DAT_INHIBIT; 1701 /* 1702 * Wait for bus no more then 250 ms. Typically there will be no wait 1703 * here at all, but when writing a crash dump we may be bypassing the 1704 * host platform's interrupt handler, and in some cases that handler 1705 * may be working around hardware quirks such as not respecting r1b 1706 * busy indications. In those cases, this wait-loop serves the purpose 1707 * of waiting for the prior command and data transfers to be done, and 1708 * SD cards are allowed to take up to 250ms for write and erase ops. 1709 * (It's usually more like 20-30ms in the real world.) 1710 */ 1711 timeout = 250; 1712 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) { 1713 if (timeout == 0) { 1714 slot_printf(slot, "Controller never released " 1715 "inhibit bit(s).\n"); 1716 sdhci_dumpregs(slot); 1717 cmd->error = MMC_ERR_FAILED; 1718 sdhci_req_done(slot); 1719 return; 1720 } 1721 timeout--; 1722 DELAY(1000); 1723 } 1724 1725 /* Prepare command flags. */ 1726 if (!(cmd->flags & MMC_RSP_PRESENT)) 1727 flags = SDHCI_CMD_RESP_NONE; 1728 else if (cmd->flags & MMC_RSP_136) 1729 flags = SDHCI_CMD_RESP_LONG; 1730 else if (cmd->flags & MMC_RSP_BUSY) 1731 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1732 else 1733 flags = SDHCI_CMD_RESP_SHORT; 1734 if (cmd->flags & MMC_RSP_CRC) 1735 flags |= SDHCI_CMD_CRC; 1736 if (cmd->flags & MMC_RSP_OPCODE) 1737 flags |= SDHCI_CMD_INDEX; 1738 if (cmd->data != NULL) 1739 flags |= SDHCI_CMD_DATA; 1740 if (cmd->opcode == MMC_STOP_TRANSMISSION) 1741 flags |= SDHCI_CMD_TYPE_ABORT; 1742 /* Prepare data. */ 1743 sdhci_start_data(slot, cmd->data); 1744 /* 1745 * Interrupt aggregation: To reduce total number of interrupts 1746 * group response interrupt with data interrupt when possible. 1747 * If there going to be data interrupt, mask response one. 1748 */ 1749 if (slot->data_done == 0) { 1750 WR4(slot, SDHCI_SIGNAL_ENABLE, 1751 slot->intmask &= ~SDHCI_INT_RESPONSE); 1752 } 1753 /* Set command argument. */ 1754 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 1755 /* Set data transfer mode. */ 1756 sdhci_set_transfer_mode(slot, cmd->data); 1757 if (__predict_false(sdhci_debug > 1)) 1758 slot_printf(slot, "Starting command!\n"); 1759 /* Start command. */ 1760 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 1761 /* Start timeout callout. */ 1762 callout_reset(&slot->timeout_callout, slot->timeout * hz, 1763 sdhci_timeout, slot); 1764} 1765 1766static void 1767sdhci_finish_command(struct sdhci_slot *slot) 1768{ 1769 int i; 1770 uint32_t val; 1771 uint8_t extra; 1772 1773 if (__predict_false(sdhci_debug > 1)) 1774 slot_printf(slot, "%s: called, err %d flags %d\n", 1775 __func__, slot->curcmd->error, slot->curcmd->flags); 1776 slot->cmd_done = 1; 1777 /* 1778 * Interrupt aggregation: Restore command interrupt. 1779 * Main restore point for the case when command interrupt 1780 * happened first. 1781 */ 1782 if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK && 1783 slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) 1784 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= 1785 SDHCI_INT_RESPONSE); 1786 /* In case of error - reset host and return. */ 1787 if (slot->curcmd->error) { 1788 if (slot->curcmd->error == MMC_ERR_BADCRC) 1789 slot->retune_req |= SDHCI_RETUNE_REQ_RESET; 1790 sdhci_reset(slot, SDHCI_RESET_CMD); 1791 sdhci_reset(slot, SDHCI_RESET_DATA); 1792 sdhci_start(slot); 1793 return; 1794 } 1795 /* If command has response - fetch it. */ 1796 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 1797 if (slot->curcmd->flags & MMC_RSP_136) { 1798 /* CRC is stripped so we need one byte shift. */ 1799 extra = 0; 1800 for (i = 0; i < 4; i++) { 1801 val = RD4(slot, SDHCI_RESPONSE + i * 4); 1802 if (slot->quirks & 1803 SDHCI_QUIRK_DONT_SHIFT_RESPONSE) 1804 slot->curcmd->resp[3 - i] = val; 1805 else { 1806 slot->curcmd->resp[3 - i] = 1807 (val << 8) | extra; 1808 extra = val >> 24; 1809 } 1810 } 1811 } else 1812 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 1813 } 1814 if (__predict_false(sdhci_debug > 1)) 1815 printf("Resp: %02x %02x %02x %02x\n", 1816 slot->curcmd->resp[0], slot->curcmd->resp[1], 1817 slot->curcmd->resp[2], slot->curcmd->resp[3]); 1818 1819 /* If data ready - finish. */ 1820 if (slot->data_done) 1821 sdhci_start(slot); 1822} 1823 1824static void 1825sdhci_start_data(struct sdhci_slot *slot, const struct mmc_data *data) 1826{ 1827 uint32_t blkcnt, blksz, current_timeout, sdma_bbufsz, target_timeout; 1828 uint8_t div; 1829 1830 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1831 slot->data_done = 1; 1832 return; 1833 } 1834 1835 slot->data_done = 0; 1836 1837 /* Calculate and set data timeout.*/ 1838 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 1839 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 1840 div = 0xE; 1841 } else { 1842 target_timeout = 1000000; 1843 div = 0; 1844 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 1845 while (current_timeout < target_timeout && div < 0xE) { 1846 ++div; 1847 current_timeout <<= 1; 1848 } 1849 /* Compensate for an off-by-one error in the CaFe chip.*/ 1850 if (div < 0xE && 1851 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 1852 ++div; 1853 } 1854 } 1855 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 1856 1857 if (data == NULL) 1858 return; 1859 1860 /* Use DMA if possible. */ 1861 if ((slot->opt & SDHCI_HAVE_DMA)) 1862 slot->flags |= SDHCI_USE_DMA; 1863 /* If data is small, broken DMA may return zeroes instead of data. */ 1864 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 1865 (data->len <= 512)) 1866 slot->flags &= ~SDHCI_USE_DMA; 1867 /* Some controllers require even block sizes. */ 1868 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1869 ((data->len) & 0x3)) 1870 slot->flags &= ~SDHCI_USE_DMA; 1871 /* Load DMA buffer. */ 1872 if (slot->flags & SDHCI_USE_DMA) { 1873 sdma_bbufsz = slot->sdma_bbufsz; 1874 if (data->flags & MMC_DATA_READ) 1875 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1876 BUS_DMASYNC_PREREAD); 1877 else { 1878 memcpy(slot->dmamem, data->data, ulmin(data->len, 1879 sdma_bbufsz)); 1880 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1881 BUS_DMASYNC_PREWRITE); 1882 } 1883 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1884 /* 1885 * Interrupt aggregation: Mask border interrupt for the last 1886 * bounce buffer and unmask otherwise. 1887 */ 1888 if (data->len == sdma_bbufsz) 1889 slot->intmask &= ~SDHCI_INT_DMA_END; 1890 else 1891 slot->intmask |= SDHCI_INT_DMA_END; 1892 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1893 } 1894 /* Current data offset for both PIO and DMA. */ 1895 slot->offset = 0; 1896 /* Set block size and request border interrupts on the SDMA boundary. */ 1897 blksz = SDHCI_MAKE_BLKSZ(slot->sdma_boundary, ulmin(data->len, 512)); 1898 WR2(slot, SDHCI_BLOCK_SIZE, blksz); 1899 /* Set block count. */ 1900 blkcnt = howmany(data->len, 512); 1901 WR2(slot, SDHCI_BLOCK_COUNT, blkcnt); 1902 if (__predict_false(sdhci_debug > 1)) 1903 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 1904 blksz, blkcnt); 1905} 1906 1907void 1908sdhci_finish_data(struct sdhci_slot *slot) 1909{ 1910 struct mmc_data *data = slot->curcmd->data; 1911 size_t left; 1912 1913 /* Interrupt aggregation: Restore command interrupt. 1914 * Auxiliary restore point for the case when data interrupt 1915 * happened first. */ 1916 if (!slot->cmd_done) { 1917 WR4(slot, SDHCI_SIGNAL_ENABLE, 1918 slot->intmask |= SDHCI_INT_RESPONSE); 1919 } 1920 /* Unload rest of data from DMA buffer. */ 1921 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) && 1922 slot->curcmd->data != NULL) { 1923 if (data->flags & MMC_DATA_READ) { 1924 left = data->len - slot->offset; 1925 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1926 BUS_DMASYNC_POSTREAD); 1927 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1928 ulmin(left, slot->sdma_bbufsz)); 1929 } else 1930 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1931 BUS_DMASYNC_POSTWRITE); 1932 } 1933 slot->data_done = 1; 1934 /* If there was error - reset the host. */ 1935 if (slot->curcmd->error) { 1936 if (slot->curcmd->error == MMC_ERR_BADCRC) 1937 slot->retune_req |= SDHCI_RETUNE_REQ_RESET; 1938 sdhci_reset(slot, SDHCI_RESET_CMD); 1939 sdhci_reset(slot, SDHCI_RESET_DATA); 1940 sdhci_start(slot); 1941 return; 1942 } 1943 /* If we already have command response - finish. */ 1944 if (slot->cmd_done) 1945 sdhci_start(slot); 1946} 1947 1948#ifdef MMCCAM 1949static void 1950sdhci_start(struct sdhci_slot *slot) 1951{ 1952 union ccb *ccb; 1953 struct ccb_mmcio *mmcio; 1954 1955 ccb = slot->ccb; 1956 if (ccb == NULL) 1957 return; 1958 1959 mmcio = &ccb->mmcio; 1960 if (!(slot->flags & CMD_STARTED)) { 1961 slot->flags |= CMD_STARTED; 1962 sdhci_start_command(slot, &mmcio->cmd); 1963 return; 1964 } 1965 1966 /* 1967 * Old stack doesn't use this! 1968 * Enabling this code causes significant performance degradation 1969 * and IRQ storms on BBB, Wandboard behaves fine. 1970 * Not using this code does no harm... 1971 if (!(slot->flags & STOP_STARTED) && mmcio->stop.opcode != 0) { 1972 slot->flags |= STOP_STARTED; 1973 sdhci_start_command(slot, &mmcio->stop); 1974 return; 1975 } 1976 */ 1977 if (__predict_false(sdhci_debug > 1)) 1978 slot_printf(slot, "result: %d\n", mmcio->cmd.error); 1979 if (mmcio->cmd.error == 0 && 1980 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 1981 sdhci_reset(slot, SDHCI_RESET_CMD); 1982 sdhci_reset(slot, SDHCI_RESET_DATA); 1983 } 1984 1985 sdhci_req_done(slot); 1986} 1987#else 1988static void 1989sdhci_start(struct sdhci_slot *slot) 1990{ 1991 const struct mmc_request *req; 1992 1993 req = slot->req; 1994 if (req == NULL) 1995 return; 1996 1997 if (!(slot->flags & CMD_STARTED)) { 1998 slot->flags |= CMD_STARTED; 1999 sdhci_start_command(slot, req->cmd); 2000 return; 2001 } 2002 if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) && 2003 !(slot->flags & STOP_STARTED) && req->stop) { 2004 slot->flags |= STOP_STARTED; 2005 sdhci_start_command(slot, req->stop); 2006 return; 2007 } 2008 if (__predict_false(sdhci_debug > 1)) 2009 slot_printf(slot, "result: %d\n", req->cmd->error); 2010 if (!req->cmd->error && 2011 ((slot->curcmd == req->stop && 2012 (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) || 2013 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 2014 sdhci_reset(slot, SDHCI_RESET_CMD); 2015 sdhci_reset(slot, SDHCI_RESET_DATA); 2016 } 2017 2018 sdhci_req_done(slot); 2019} 2020#endif 2021 2022int 2023sdhci_generic_request(device_t brdev __unused, device_t reqdev, 2024 struct mmc_request *req) 2025{ 2026 struct sdhci_slot *slot = device_get_ivars(reqdev); 2027 2028 SDHCI_LOCK(slot); 2029 if (slot->req != NULL) { 2030 SDHCI_UNLOCK(slot); 2031 return (EBUSY); 2032 } 2033 if (__predict_false(sdhci_debug > 1)) { 2034 slot_printf(slot, 2035 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 2036 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 2037 (req->cmd->data)?(u_int)req->cmd->data->len:0, 2038 (req->cmd->data)?req->cmd->data->flags:0); 2039 } 2040 slot->req = req; 2041 slot->flags = 0; 2042 sdhci_start(slot); 2043 SDHCI_UNLOCK(slot); 2044 if (dumping) { 2045 while (slot->req != NULL) { 2046 sdhci_generic_intr(slot); 2047 DELAY(10); 2048 } 2049 } 2050 return (0); 2051} 2052 2053int 2054sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev) 2055{ 2056 struct sdhci_slot *slot = device_get_ivars(reqdev); 2057 uint32_t val; 2058 2059 SDHCI_LOCK(slot); 2060 val = RD4(slot, SDHCI_PRESENT_STATE); 2061 SDHCI_UNLOCK(slot); 2062 return (!(val & SDHCI_WRITE_PROTECT)); 2063} 2064 2065int 2066sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev) 2067{ 2068 struct sdhci_slot *slot = device_get_ivars(reqdev); 2069 int err = 0; 2070 2071 SDHCI_LOCK(slot); 2072 while (slot->bus_busy) 2073 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 2074 slot->bus_busy++; 2075 /* Activate led. */ 2076 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 2077 SDHCI_UNLOCK(slot); 2078 return (err); 2079} 2080 2081int 2082sdhci_generic_release_host(device_t brdev __unused, device_t reqdev) 2083{ 2084 struct sdhci_slot *slot = device_get_ivars(reqdev); 2085 2086 SDHCI_LOCK(slot); 2087 /* Deactivate led. */ 2088 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 2089 slot->bus_busy--; 2090 SDHCI_UNLOCK(slot); 2091 wakeup(slot); 2092 return (0); 2093} 2094 2095static void 2096sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 2097{ 2098 2099 if (!slot->curcmd) { 2100 slot_printf(slot, "Got command interrupt 0x%08x, but " 2101 "there is no active command.\n", intmask); 2102 sdhci_dumpregs(slot); 2103 return; 2104 } 2105 if (intmask & SDHCI_INT_TIMEOUT) 2106 slot->curcmd->error = MMC_ERR_TIMEOUT; 2107 else if (intmask & SDHCI_INT_CRC) 2108 slot->curcmd->error = MMC_ERR_BADCRC; 2109 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 2110 slot->curcmd->error = MMC_ERR_FIFO; 2111 2112 sdhci_finish_command(slot); 2113} 2114 2115static void 2116sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 2117{ 2118 struct mmc_data *data; 2119 size_t left; 2120 uint32_t sdma_bbufsz; 2121 2122 if (!slot->curcmd) { 2123 slot_printf(slot, "Got data interrupt 0x%08x, but " 2124 "there is no active command.\n", intmask); 2125 sdhci_dumpregs(slot); 2126 return; 2127 } 2128 if (slot->curcmd->data == NULL && 2129 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 2130 slot_printf(slot, "Got data interrupt 0x%08x, but " 2131 "there is no active data operation.\n", 2132 intmask); 2133 sdhci_dumpregs(slot); 2134 return; 2135 } 2136 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2137 slot->curcmd->error = MMC_ERR_TIMEOUT; 2138 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 2139 slot->curcmd->error = MMC_ERR_BADCRC; 2140 if (slot->curcmd->data == NULL && 2141 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 2142 SDHCI_INT_DMA_END))) { 2143 slot_printf(slot, "Got data interrupt 0x%08x, but " 2144 "there is busy-only command.\n", intmask); 2145 sdhci_dumpregs(slot); 2146 slot->curcmd->error = MMC_ERR_INVALID; 2147 } 2148 if (slot->curcmd->error) { 2149 /* No need to continue after any error. */ 2150 goto done; 2151 } 2152 2153 /* Handle tuning completion interrupt. */ 2154 if (__predict_false((intmask & SDHCI_INT_DATA_AVAIL) && 2155 (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK || 2156 slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) { 2157 slot->req->flags |= MMC_TUNE_DONE; 2158 sdhci_finish_command(slot); 2159 sdhci_finish_data(slot); 2160 return; 2161 } 2162 /* Handle PIO interrupt. */ 2163 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 2164 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 2165 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 2166 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, 2167 &intmask); 2168 slot->flags |= PLATFORM_DATA_STARTED; 2169 } else 2170 sdhci_transfer_pio(slot); 2171 } 2172 /* Handle DMA border. */ 2173 if (intmask & SDHCI_INT_DMA_END) { 2174 data = slot->curcmd->data; 2175 sdma_bbufsz = slot->sdma_bbufsz; 2176 2177 /* Unload DMA buffer ... */ 2178 left = data->len - slot->offset; 2179 if (data->flags & MMC_DATA_READ) { 2180 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2181 BUS_DMASYNC_POSTREAD); 2182 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 2183 ulmin(left, sdma_bbufsz)); 2184 } else { 2185 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2186 BUS_DMASYNC_POSTWRITE); 2187 } 2188 /* ... and reload it again. */ 2189 slot->offset += sdma_bbufsz; 2190 left = data->len - slot->offset; 2191 if (data->flags & MMC_DATA_READ) { 2192 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2193 BUS_DMASYNC_PREREAD); 2194 } else { 2195 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 2196 ulmin(left, sdma_bbufsz)); 2197 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2198 BUS_DMASYNC_PREWRITE); 2199 } 2200 /* 2201 * Interrupt aggregation: Mask border interrupt for the last 2202 * bounce buffer. 2203 */ 2204 if (left == sdma_bbufsz) { 2205 slot->intmask &= ~SDHCI_INT_DMA_END; 2206 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 2207 } 2208 /* Restart DMA. */ 2209 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 2210 } 2211 /* We have got all data. */ 2212 if (intmask & SDHCI_INT_DATA_END) { 2213 if (slot->flags & PLATFORM_DATA_STARTED) { 2214 slot->flags &= ~PLATFORM_DATA_STARTED; 2215 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 2216 } else 2217 sdhci_finish_data(slot); 2218 } 2219done: 2220 if (slot->curcmd != NULL && slot->curcmd->error != 0) { 2221 if (slot->flags & PLATFORM_DATA_STARTED) { 2222 slot->flags &= ~PLATFORM_DATA_STARTED; 2223 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 2224 } else 2225 sdhci_finish_data(slot); 2226 } 2227} 2228 2229static void 2230sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err) 2231{ 2232 2233 if (!slot->curcmd) { 2234 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 2235 "there is no active command.\n", acmd_err); 2236 sdhci_dumpregs(slot); 2237 return; 2238 } 2239 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", acmd_err); 2240 sdhci_reset(slot, SDHCI_RESET_CMD); 2241} 2242 2243void 2244sdhci_generic_intr(struct sdhci_slot *slot) 2245{ 2246 uint32_t intmask, present; 2247 uint16_t val16; 2248 2249 SDHCI_LOCK(slot); 2250 /* Read slot interrupt status. */ 2251 intmask = RD4(slot, SDHCI_INT_STATUS); 2252 if (intmask == 0 || intmask == 0xffffffff) { 2253 SDHCI_UNLOCK(slot); 2254 return; 2255 } 2256 if (__predict_false(sdhci_debug > 2)) 2257 slot_printf(slot, "Interrupt %#x\n", intmask); 2258 2259 /* Handle tuning error interrupt. */ 2260 if (__predict_false(intmask & SDHCI_INT_TUNEERR)) { 2261 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_TUNEERR); 2262 slot_printf(slot, "Tuning error indicated\n"); 2263 slot->retune_req |= SDHCI_RETUNE_REQ_RESET; 2264 if (slot->curcmd) { 2265 slot->curcmd->error = MMC_ERR_BADCRC; 2266 sdhci_finish_command(slot); 2267 } 2268 } 2269 /* Handle re-tuning interrupt. */ 2270 if (__predict_false(intmask & SDHCI_INT_RETUNE)) 2271 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED; 2272 /* Handle card presence interrupts. */ 2273 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2274 present = (intmask & SDHCI_INT_CARD_INSERT) != 0; 2275 slot->intmask &= 2276 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 2277 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE : 2278 SDHCI_INT_CARD_INSERT; 2279 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 2280 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 2281 WR4(slot, SDHCI_INT_STATUS, intmask & 2282 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 2283 sdhci_handle_card_present_locked(slot, present); 2284 } 2285 /* Handle command interrupts. */ 2286 if (intmask & SDHCI_INT_CMD_MASK) { 2287 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 2288 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 2289 } 2290 /* Handle data interrupts. */ 2291 if (intmask & SDHCI_INT_DATA_MASK) { 2292 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 2293 /* Don't call data_irq in case of errored command. */ 2294 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 2295 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 2296 } 2297 /* Handle AutoCMD12 error interrupt. */ 2298 if (intmask & SDHCI_INT_ACMD12ERR) { 2299 /* Clearing SDHCI_INT_ACMD12ERR may clear SDHCI_ACMD12_ERR. */ 2300 val16 = RD2(slot, SDHCI_ACMD12_ERR); 2301 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 2302 sdhci_acmd_irq(slot, val16); 2303 } 2304 /* Handle bus power interrupt. */ 2305 if (intmask & SDHCI_INT_BUS_POWER) { 2306 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 2307 slot_printf(slot, "Card is consuming too much power!\n"); 2308 } 2309 intmask &= ~(SDHCI_INT_ERROR | SDHCI_INT_TUNEERR | SDHCI_INT_RETUNE | 2310 SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CMD_MASK | 2311 SDHCI_INT_DATA_MASK | SDHCI_INT_ACMD12ERR | SDHCI_INT_BUS_POWER); 2312 /* The rest is unknown. */ 2313 if (intmask) { 2314 WR4(slot, SDHCI_INT_STATUS, intmask); 2315 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 2316 intmask); 2317 sdhci_dumpregs(slot); 2318 } 2319 2320 SDHCI_UNLOCK(slot); 2321} 2322 2323int 2324sdhci_generic_read_ivar(device_t bus, device_t child, int which, 2325 uintptr_t *result) 2326{ 2327 const struct sdhci_slot *slot = device_get_ivars(child); 2328 2329 switch (which) { 2330 default: 2331 return (EINVAL); 2332 case MMCBR_IVAR_BUS_MODE: 2333 *result = slot->host.ios.bus_mode; 2334 break; 2335 case MMCBR_IVAR_BUS_WIDTH: 2336 *result = slot->host.ios.bus_width; 2337 break; 2338 case MMCBR_IVAR_CHIP_SELECT: 2339 *result = slot->host.ios.chip_select; 2340 break; 2341 case MMCBR_IVAR_CLOCK: 2342 *result = slot->host.ios.clock; 2343 break; 2344 case MMCBR_IVAR_F_MIN: 2345 *result = slot->host.f_min; 2346 break; 2347 case MMCBR_IVAR_F_MAX: 2348 *result = slot->host.f_max; 2349 break; 2350 case MMCBR_IVAR_HOST_OCR: 2351 *result = slot->host.host_ocr; 2352 break; 2353 case MMCBR_IVAR_MODE: 2354 *result = slot->host.mode; 2355 break; 2356 case MMCBR_IVAR_OCR: 2357 *result = slot->host.ocr; 2358 break; 2359 case MMCBR_IVAR_POWER_MODE: 2360 *result = slot->host.ios.power_mode; 2361 break; 2362 case MMCBR_IVAR_VDD: 2363 *result = slot->host.ios.vdd; 2364 break; 2365 case MMCBR_IVAR_RETUNE_REQ: 2366 if (slot->opt & SDHCI_TUNING_ENABLED) { 2367 if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) { 2368 *result = retune_req_reset; 2369 break; 2370 } 2371 if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) { 2372 *result = retune_req_normal; 2373 break; 2374 } 2375 } 2376 *result = retune_req_none; 2377 break; 2378 case MMCBR_IVAR_VCCQ: 2379 *result = slot->host.ios.vccq; 2380 break; 2381 case MMCBR_IVAR_CAPS: 2382 *result = slot->host.caps; 2383 break; 2384 case MMCBR_IVAR_TIMING: 2385 *result = slot->host.ios.timing; 2386 break; 2387 case MMCBR_IVAR_MAX_DATA: 2388 /* 2389 * Re-tuning modes 1 and 2 restrict the maximum data length 2390 * per read/write command to 4 MiB. 2391 */ 2392 if (slot->opt & SDHCI_TUNING_ENABLED && 2393 (slot->retune_mode == SDHCI_RETUNE_MODE_1 || 2394 slot->retune_mode == SDHCI_RETUNE_MODE_2)) { 2395 *result = 4 * 1024 * 1024 / MMC_SECTOR_SIZE; 2396 break; 2397 } 2398 *result = 65535; 2399 break; 2400 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: 2401 /* 2402 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs. 2403 */ 2404 *result = 1000000; 2405 break; 2406 } 2407 return (0); 2408} 2409 2410int 2411sdhci_generic_write_ivar(device_t bus, device_t child, int which, 2412 uintptr_t value) 2413{ 2414 struct sdhci_slot *slot = device_get_ivars(child); 2415 uint32_t clock, max_clock; 2416 int i; 2417 2418 if (sdhci_debug > 1) 2419 slot_printf(slot, "%s: var=%d\n", __func__, which); 2420 switch (which) { 2421 default: 2422 return (EINVAL); 2423 case MMCBR_IVAR_BUS_MODE: 2424 slot->host.ios.bus_mode = value; 2425 break; 2426 case MMCBR_IVAR_BUS_WIDTH: 2427 slot->host.ios.bus_width = value; 2428 break; 2429 case MMCBR_IVAR_CHIP_SELECT: 2430 slot->host.ios.chip_select = value; 2431 break; 2432 case MMCBR_IVAR_CLOCK: 2433 if (value > 0) { 2434 max_clock = slot->max_clk; 2435 clock = max_clock; 2436 2437 if (slot->version < SDHCI_SPEC_300) { 2438 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 2439 i <<= 1) { 2440 if (clock <= value) 2441 break; 2442 clock >>= 1; 2443 } 2444 } else { 2445 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 2446 i += 2) { 2447 if (clock <= value) 2448 break; 2449 clock = max_clock / (i + 2); 2450 } 2451 } 2452 2453 slot->host.ios.clock = clock; 2454 } else 2455 slot->host.ios.clock = 0; 2456 break; 2457 case MMCBR_IVAR_MODE: 2458 slot->host.mode = value; 2459 break; 2460 case MMCBR_IVAR_OCR: 2461 slot->host.ocr = value; 2462 break; 2463 case MMCBR_IVAR_POWER_MODE: 2464 slot->host.ios.power_mode = value; 2465 break; 2466 case MMCBR_IVAR_VDD: 2467 slot->host.ios.vdd = value; 2468 break; 2469 case MMCBR_IVAR_VCCQ: 2470 slot->host.ios.vccq = value; 2471 break; 2472 case MMCBR_IVAR_TIMING: 2473 slot->host.ios.timing = value; 2474 break; 2475 case MMCBR_IVAR_CAPS: 2476 case MMCBR_IVAR_HOST_OCR: 2477 case MMCBR_IVAR_F_MIN: 2478 case MMCBR_IVAR_F_MAX: 2479 case MMCBR_IVAR_MAX_DATA: 2480 case MMCBR_IVAR_RETUNE_REQ: 2481 return (EINVAL); 2482 } 2483 return (0); 2484} 2485 2486#ifdef MMCCAM 2487void 2488sdhci_start_slot(struct sdhci_slot *slot) 2489{ 2490 2491 if ((slot->devq = cam_simq_alloc(1)) == NULL) 2492 goto fail; 2493 2494 mtx_init(&slot->sim_mtx, "sdhcisim", NULL, MTX_DEF); 2495 slot->sim = cam_sim_alloc(sdhci_cam_action, sdhci_cam_poll, 2496 "sdhci_slot", slot, device_get_unit(slot->bus), 2497 &slot->sim_mtx, 1, 1, slot->devq); 2498 2499 if (slot->sim == NULL) { 2500 cam_simq_free(slot->devq); 2501 slot_printf(slot, "cannot allocate CAM SIM\n"); 2502 goto fail; 2503 } 2504 2505 mtx_lock(&slot->sim_mtx); 2506 if (xpt_bus_register(slot->sim, slot->bus, 0) != 0) { 2507 slot_printf(slot, "cannot register SCSI pass-through bus\n"); 2508 cam_sim_free(slot->sim, FALSE); 2509 cam_simq_free(slot->devq); 2510 mtx_unlock(&slot->sim_mtx); 2511 goto fail; 2512 } 2513 mtx_unlock(&slot->sim_mtx); 2514 2515 /* End CAM-specific init */ 2516 slot->card_present = 0; 2517 sdhci_card_task(slot, 0); 2518 return; 2519 2520fail: 2521 if (slot->sim != NULL) { 2522 mtx_lock(&slot->sim_mtx); 2523 xpt_bus_deregister(cam_sim_path(slot->sim)); 2524 cam_sim_free(slot->sim, FALSE); 2525 mtx_unlock(&slot->sim_mtx); 2526 } 2527 2528 if (slot->devq != NULL) 2529 cam_simq_free(slot->devq); 2530} 2531 2532static void 2533sdhci_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb) 2534{ 2535 struct sdhci_slot *slot; 2536 2537 slot = cam_sim_softc(sim); 2538 2539 sdhci_cam_request(slot, ccb); 2540} 2541 2542void 2543sdhci_cam_action(struct cam_sim *sim, union ccb *ccb) 2544{ 2545 struct sdhci_slot *slot; 2546 2547 slot = cam_sim_softc(sim); 2548 if (slot == NULL) { 2549 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2550 xpt_done(ccb); 2551 return; 2552 } 2553 2554 mtx_assert(&slot->sim_mtx, MA_OWNED); 2555 2556 switch (ccb->ccb_h.func_code) { 2557 case XPT_PATH_INQ: 2558 { 2559 struct ccb_pathinq *cpi; 2560 2561 cpi = &ccb->cpi; 2562 cpi->version_num = 1; 2563 cpi->hba_inquiry = 0; 2564 cpi->target_sprt = 0; 2565 cpi->hba_misc = PIM_NOBUSRESET | PIM_SEQSCAN; 2566 cpi->hba_eng_cnt = 0; 2567 cpi->max_target = 0; 2568 cpi->max_lun = 0; 2569 cpi->initiator_id = 1; 2570 cpi->maxio = MAXPHYS; 2571 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2572 strncpy(cpi->hba_vid, "Deglitch Networks", HBA_IDLEN); 2573 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2574 cpi->unit_number = cam_sim_unit(sim); 2575 cpi->bus_id = cam_sim_bus(sim); 2576 cpi->base_transfer_speed = 100; /* XXX WTF? */ 2577 cpi->protocol = PROTO_MMCSD; 2578 cpi->protocol_version = SCSI_REV_0; 2579 cpi->transport = XPORT_MMCSD; 2580 cpi->transport_version = 0; 2581 2582 cpi->ccb_h.status = CAM_REQ_CMP; 2583 break; 2584 } 2585 case XPT_GET_TRAN_SETTINGS: 2586 { 2587 struct ccb_trans_settings *cts = &ccb->cts; 2588 2589 if (sdhci_debug > 1) 2590 slot_printf(slot, "Got XPT_GET_TRAN_SETTINGS\n"); 2591 2592 cts->protocol = PROTO_MMCSD; 2593 cts->protocol_version = 1; 2594 cts->transport = XPORT_MMCSD; 2595 cts->transport_version = 1; 2596 cts->xport_specific.valid = 0; 2597 cts->proto_specific.mmc.host_ocr = slot->host.host_ocr; 2598 cts->proto_specific.mmc.host_f_min = slot->host.f_min; 2599 cts->proto_specific.mmc.host_f_max = slot->host.f_max; 2600 cts->proto_specific.mmc.host_caps = slot->host.caps; 2601 memcpy(&cts->proto_specific.mmc.ios, &slot->host.ios, sizeof(struct mmc_ios)); 2602 ccb->ccb_h.status = CAM_REQ_CMP; 2603 break; 2604 } 2605 case XPT_SET_TRAN_SETTINGS: 2606 { 2607 if (sdhci_debug > 1) 2608 slot_printf(slot, "Got XPT_SET_TRAN_SETTINGS\n"); 2609 sdhci_cam_settran_settings(slot, ccb); 2610 ccb->ccb_h.status = CAM_REQ_CMP; 2611 break; 2612 } 2613 case XPT_RESET_BUS: 2614 if (sdhci_debug > 1) 2615 slot_printf(slot, "Got XPT_RESET_BUS, ACK it...\n"); 2616 ccb->ccb_h.status = CAM_REQ_CMP; 2617 break; 2618 case XPT_MMC_IO: 2619 /* 2620 * Here is the HW-dependent part of 2621 * sending the command to the underlying h/w 2622 * At some point in the future an interrupt comes. 2623 * Then the request will be marked as completed. 2624 */ 2625 if (__predict_false(sdhci_debug > 1)) 2626 slot_printf(slot, "Got XPT_MMC_IO\n"); 2627 ccb->ccb_h.status = CAM_REQ_INPROG; 2628 2629 sdhci_cam_handle_mmcio(sim, ccb); 2630 return; 2631 /* NOTREACHED */ 2632 break; 2633 default: 2634 ccb->ccb_h.status = CAM_REQ_INVALID; 2635 break; 2636 } 2637 xpt_done(ccb); 2638 return; 2639} 2640 2641void 2642sdhci_cam_poll(struct cam_sim *sim) 2643{ 2644 return; 2645} 2646 2647static int 2648sdhci_cam_get_possible_host_clock(const struct sdhci_slot *slot, 2649 int proposed_clock) 2650{ 2651 int max_clock, clock, i; 2652 2653 if (proposed_clock == 0) 2654 return 0; 2655 max_clock = slot->max_clk; 2656 clock = max_clock; 2657 2658 if (slot->version < SDHCI_SPEC_300) { 2659 for (i = 0; i < SDHCI_200_MAX_DIVIDER; i <<= 1) { 2660 if (clock <= proposed_clock) 2661 break; 2662 clock >>= 1; 2663 } 2664 } else { 2665 for (i = 0; i < SDHCI_300_MAX_DIVIDER; i += 2) { 2666 if (clock <= proposed_clock) 2667 break; 2668 clock = max_clock / (i + 2); 2669 } 2670 } 2671 return clock; 2672} 2673 2674static int 2675sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb) 2676{ 2677 struct mmc_ios *ios; 2678 const struct mmc_ios *new_ios; 2679 const struct ccb_trans_settings_mmc *cts; 2680 2681 ios = &slot->host.ios; 2682 cts = &ccb->cts.proto_specific.mmc; 2683 new_ios = &cts->ios; 2684 2685 /* Update only requested fields */ 2686 if (cts->ios_valid & MMC_CLK) { 2687 ios->clock = sdhci_cam_get_possible_host_clock(slot, new_ios->clock); 2688 slot_printf(slot, "Clock => %d\n", ios->clock); 2689 } 2690 if (cts->ios_valid & MMC_VDD) { 2691 ios->vdd = new_ios->vdd; 2692 slot_printf(slot, "VDD => %d\n", ios->vdd); 2693 } 2694 if (cts->ios_valid & MMC_CS) { 2695 ios->chip_select = new_ios->chip_select; 2696 slot_printf(slot, "CS => %d\n", ios->chip_select); 2697 } 2698 if (cts->ios_valid & MMC_BW) { 2699 ios->bus_width = new_ios->bus_width; 2700 slot_printf(slot, "Bus width => %d\n", ios->bus_width); 2701 } 2702 if (cts->ios_valid & MMC_PM) { 2703 ios->power_mode = new_ios->power_mode; 2704 slot_printf(slot, "Power mode => %d\n", ios->power_mode); 2705 } 2706 if (cts->ios_valid & MMC_BT) { 2707 ios->timing = new_ios->timing; 2708 slot_printf(slot, "Timing => %d\n", ios->timing); 2709 } 2710 if (cts->ios_valid & MMC_BM) { 2711 ios->bus_mode = new_ios->bus_mode; 2712 slot_printf(slot, "Bus mode => %d\n", ios->bus_mode); 2713 } 2714 2715 /* XXX Provide a way to call a chip-specific IOS update, required for TI */ 2716 return (sdhci_cam_update_ios(slot)); 2717} 2718 2719static int 2720sdhci_cam_update_ios(struct sdhci_slot *slot) 2721{ 2722 struct mmc_ios *ios = &slot->host.ios; 2723 2724 slot_printf(slot, "%s: power_mode=%d, clk=%d, bus_width=%d, timing=%d\n", 2725 __func__, ios->power_mode, ios->clock, ios->bus_width, ios->timing); 2726 SDHCI_LOCK(slot); 2727 /* Do full reset on bus power down to clear from any state. */ 2728 if (ios->power_mode == power_off) { 2729 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 2730 sdhci_init(slot); 2731 } 2732 /* Configure the bus. */ 2733 sdhci_set_clock(slot, ios->clock); 2734 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 2735 if (ios->bus_width == bus_width_8) { 2736 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 2737 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 2738 } else if (ios->bus_width == bus_width_4) { 2739 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 2740 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 2741 } else if (ios->bus_width == bus_width_1) { 2742 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 2743 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 2744 } else { 2745 panic("Invalid bus width: %d", ios->bus_width); 2746 } 2747 if (ios->timing == bus_timing_hs && 2748 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 2749 slot->hostctrl |= SDHCI_CTRL_HISPD; 2750 else 2751 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 2752 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 2753 /* Some controllers like reset after bus changes. */ 2754 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 2755 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 2756 2757 SDHCI_UNLOCK(slot); 2758 return (0); 2759} 2760 2761static int 2762sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb) 2763{ 2764 const struct ccb_mmcio *mmcio; 2765 2766 mmcio = &ccb->mmcio; 2767 2768 SDHCI_LOCK(slot); 2769/* if (slot->req != NULL) { 2770 SDHCI_UNLOCK(slot); 2771 return (EBUSY); 2772 } 2773*/ 2774 if (__predict_false(sdhci_debug > 1)) { 2775 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 2776 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 2777 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 2778 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0); 2779 } 2780 if (mmcio->cmd.data != NULL) { 2781 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 2782 panic("data->len = %d, data->flags = %d -- something is b0rked", 2783 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 2784 } 2785 slot->ccb = ccb; 2786 slot->flags = 0; 2787 sdhci_start(slot); 2788 SDHCI_UNLOCK(slot); 2789 if (dumping) { 2790 while (slot->ccb != NULL) { 2791 sdhci_generic_intr(slot); 2792 DELAY(10); 2793 } 2794 } 2795 return (0); 2796} 2797#endif /* MMCCAM */ 2798 2799MODULE_VERSION(sdhci, SDHCI_VERSION); 2800