1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2020 Rubicon Communications, LLC (Netgate) 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29#ifndef _SAFEXCEL_REGS_H_ 30#define _SAFEXCEL_REGS_H_ 31 32#define SAFEXCEL_HIA_VERSION_LE 0x35ca 33#define SAFEXCEL_HIA_VERSION_BE 0xca35 34#define EIP201_VERSION_LE 0x36c9 35#define SAFEXCEL_REG_LO16(_reg) ((_reg) & 0xffff) 36#define SAFEXCEL_REG_HI16(_reg) (((_reg) >> 16) & 0xffff) 37 38 39/* HIA, Command Descriptor Ring Manager */ 40#define CDR_BASE_ADDR_LO(x) (0x0 + ((x) << 12)) 41#define CDR_BASE_ADDR_HI(x) (0x4 + ((x) << 12)) 42#define CDR_DATA_BASE_ADDR_LO(x) (0x8 + ((x) << 12)) 43#define CDR_DATA_BASE_ADDR_HI(x) (0xC + ((x) << 12)) 44#define CDR_ACD_BASE_ADDR_LO(x) (0x10 + ((x) << 12)) 45#define CDR_ACD_BASE_ADDR_HI(x) (0x14 + ((x) << 12)) 46#define CDR_RING_SIZE(x) (0x18 + ((x) << 12)) 47#define CDR_DESC_SIZE(x) (0x1C + ((x) << 12)) 48#define CDR_CFG(x) (0x20 + ((x) << 12)) 49#define CDR_DMA_CFG(x) (0x24 + ((x) << 12)) 50#define CDR_THR(x) (0x28 + ((x) << 12)) 51#define CDR_PREP_COUNT(x) (0x2C + ((x) << 12)) 52#define CDR_PROC_COUNT(x) (0x30 + ((x) << 12)) 53#define CDR_PREP_PNTR(x) (0x34 + ((x) << 12)) 54#define CDR_PROC_PNTR(x) (0x38 + ((x) << 12)) 55#define CDR_STAT(x) (0x3C + ((x) << 12)) 56 57/* HIA, Result Descriptor Ring Manager */ 58#define RDR_BASE_ADDR_LO(x) (0x800 + ((x) << 12)) 59#define RDR_BASE_ADDR_HI(x) (0x804 + ((x) << 12)) 60#define RDR_DATA_BASE_ADDR_LO(x) (0x808 + ((x) << 12)) 61#define RDR_DATA_BASE_ADDR_HI(x) (0x80C + ((x) << 12)) 62#define RDR_ACD_BASE_ADDR_LO(x) (0x810 + ((x) << 12)) 63#define RDR_ACD_BASE_ADDR_HI(x) (0x814 + ((x) << 12)) 64#define RDR_RING_SIZE(x) (0x818 + ((x) << 12)) 65#define RDR_DESC_SIZE(x) (0x81C + ((x) << 12)) 66#define RDR_CFG(x) (0x820 + ((x) << 12)) 67#define RDR_DMA_CFG(x) (0x824 + ((x) << 12)) 68#define RDR_THR(x) (0x828 + ((x) << 12)) 69#define RDR_PREP_COUNT(x) (0x82C + ((x) << 12)) 70#define RDR_PROC_COUNT(x) (0x830 + ((x) << 12)) 71#define RDR_PREP_PNTR(x) (0x834 + ((x) << 12)) 72#define RDR_PROC_PNTR(x) (0x838 + ((x) << 12)) 73#define RDR_STAT(x) (0x83C + ((x) << 12)) 74 75/* HIA, Ring AIC */ 76#define AIC_POL_CTRL(x) (0xE000 - ((x) << 12)) 77#define AIC_TYPE_CTRL(x) (0xE004 - ((x) << 12)) 78#define AIC_ENABLE_CTRL(x) (0xE008 - ((x) << 12)) 79#define AIC_RAW_STAL(x) (0xE00C - ((x) << 12)) 80#define AIC_ENABLE_SET(x) (0xE00C - ((x) << 12)) 81#define AIC_ENABLED_STAT(x) (0xE010 - ((x) << 12)) 82#define AIC_ACK(x) (0xE010 - ((x) << 12)) 83#define AIC_ENABLE_CLR(x) (0xE014 - ((x) << 12)) 84#define AIC_OPTIONS(x) (0xE018 - ((x) << 12)) 85#define AIC_VERSION(x) (0xE01C - ((x) << 12)) 86 87/* HIA, Global AIC */ 88#define AIC_G_POL_CTRL 0xF800 89#define AIC_G_TYPE_CTRL 0xF804 90#define AIC_G_ENABLE_CTRL 0xF808 91#define AIC_G_RAW_STAT 0xF80C 92#define AIC_G_ENABLE_SET 0xF80C 93#define AIC_G_ENABLED_STAT 0xF810 94#define AIC_G_ACK 0xF810 95#define AIC_G_ENABLE_CLR 0xF814 96#define AIC_G_OPTIONS 0xF818 97#define AIC_G_VERSION 0xF81C 98 99/* HIA, Data Fetch Engine */ 100#define DFE_CFG 0xF000 101#define DFE_PRIO_0 0xF010 102#define DFE_PRIO_1 0xF014 103#define DFE_PRIO_2 0xF018 104#define DFE_PRIO_3 0xF01C 105 106/* HIA, Data Fetch Engine access monitoring for CDR */ 107#define DFE_RING_REGION_LO(x) (0xF080 + ((x) << 3)) 108#define DFE_RING_REGION_HI(x) (0xF084 + ((x) << 3)) 109 110/* HIA, Data Fetch Engine thread control and status for thread */ 111#define DFE_THR_CTRL 0xF200 112#define DFE_THR_STAT 0xF204 113#define DFE_THR_DESC_CTRL 0xF208 114#define DFE_THR_DESC_DPTR_LO 0xF210 115#define DFE_THR_DESC_DPTR_HI 0xF214 116#define DFE_THR_DESC_ACDPTR_LO 0xF218 117#define DFE_THR_DESC_ACDPTR_HI 0xF21C 118 119/* HIA, Data Store Engine */ 120#define DSE_CFG 0xF400 121#define DSE_PRIO_0 0xF410 122#define DSE_PRIO_1 0xF414 123#define DSE_PRIO_2 0xF418 124#define DSE_PRIO_3 0xF41C 125 126/* HIA, Data Store Engine access monitoring for RDR */ 127#define DSE_RING_REGION_LO(x) (0xF480 + ((x) << 3)) 128#define DSE_RING_REGION_HI(x) (0xF484 + ((x) << 3)) 129 130/* HIA, Data Store Engine thread control and status for thread */ 131#define DSE_THR_CTRL 0xF600 132#define DSE_THR_STAT 0xF604 133#define DSE_THR_DESC_CTRL 0xF608 134#define DSE_THR_DESC_DPTR_LO 0xF610 135#define DSE_THR_DESC_DPTR_HI 0xF614 136#define DSE_THR_DESC_S_DPTR_LO 0xF618 137#define DSE_THR_DESC_S_DPTR_HI 0xF61C 138#define DSE_THR_ERROR_STAT 0xF620 139 140/* HIA Global */ 141#define HIA_MST_CTRL 0xFFF4 142#define HIA_OPTIONS 0xFFF8 143#define HIA_VERSION 0xFFFC 144 145/* Processing Engine Input Side, Processing Engine */ 146#define PE_IN_DBUF_THRESH 0x10000 147#define PE_IN_TBUF_THRESH 0x10100 148 149/* Packet Engine Configuration / Status Registers */ 150#define PE_TOKEN_CTRL_STAT 0x11000 151#define PE_FUNCTION_EN 0x11004 152#define PE_CONTEXT_CTRL 0x11008 153#define PE_INTERRUPT_CTRL_STAT 0x11010 154#define PE_CONTEXT_STAT 0x1100C 155#define PE_OUT_TRANS_CTRL_STAT 0x11018 156#define PE_OUT_BUF_CTRL 0x1101C 157 158/* Packet Engine AIC */ 159#define PE_EIP96_AIC_POL_CTRL 0x113C0 160#define PE_EIP96_AIC_TYPE_CTRL 0x113C4 161#define PE_EIP96_AIC_ENABLE_CTRL 0x113C8 162#define PE_EIP96_AIC_RAW_STAT 0x113CC 163#define PE_EIP96_AIC_ENABLE_SET 0x113CC 164#define PE_EIP96_AIC_ENABLED_STAT 0x113D0 165#define PE_EIP96_AIC_ACK 0x113D0 166#define PE_EIP96_AIC_ENABLE_CLR 0x113D4 167#define PE_EIP96_AIC_OPTIONS 0x113D8 168#define PE_EIP96_AIC_VERSION 0x113DC 169 170/* Packet Engine Options & Version Registers */ 171#define PE_EIP96_OPTIONS 0x113F8 172#define PE_EIP96_VERSION 0x113FC 173 174#define SAFEXCEL_OPT 175 176/* Processing Engine Output Side */ 177#define PE_OUT_DBUF_THRESH 0x11C00 178#define PE_OUT_TBUF_THRESH 0x11D00 179 180/* Processing Engine Local AIC */ 181#define PE_AIC_POL_CTRL 0x11F00 182#define PE_AIC_TYPE_CTRL 0x11F04 183#define PE_AIC_ENABLE_CTRL 0x11F08 184#define PE_AIC_RAW_STAT 0x11F0C 185#define PE_AIC_ENABLE_SET 0x11F0C 186#define PE_AIC_ENABLED_STAT 0x11F10 187#define PE_AIC_ENABLE_CLR 0x11F14 188#define PE_AIC_OPTIONS 0x11F18 189#define PE_AIC_VERSION 0x11F1C 190 191/* Processing Engine General Configuration and Version */ 192#define PE_IN_FLIGHT 0x11FF0 193#define PE_OPTIONS 0x11FF8 194#define PE_VERSION 0x11FFC 195 196/* EIP-97 - Global */ 197#define EIP97_CLOCK_STATE 0x1FFE4 198#define EIP97_FORCE_CLOCK_ON 0x1FFE8 199#define EIP97_FORCE_CLOCK_OFF 0x1FFEC 200#define EIP97_MST_CTRL 0x1FFF4 201#define EIP97_OPTIONS 0x1FFF8 202#define EIP97_VERSION 0x1FFFC 203 204/* Register base offsets */ 205#define SAFEXCEL_HIA_AIC(_sc) ((_sc)->sc_offsets.hia_aic) 206#define SAFEXCEL_HIA_AIC_G(_sc) ((_sc)->sc_offsets.hia_aic_g) 207#define SAFEXCEL_HIA_AIC_R(_sc) ((_sc)->sc_offsets.hia_aic_r) 208#define SAFEXCEL_HIA_AIC_xDR(_sc) ((_sc)->sc_offsets.hia_aic_xdr) 209#define SAFEXCEL_HIA_DFE(_sc) ((_sc)->sc_offsets.hia_dfe) 210#define SAFEXCEL_HIA_DFE_THR(_sc) ((_sc)->sc_offsets.hia_dfe_thr) 211#define SAFEXCEL_HIA_DSE(_sc) ((_sc)->sc_offsets.hia_dse) 212#define SAFEXCEL_HIA_DSE_THR(_sc) ((_sc)->sc_offsets.hia_dse_thr) 213#define SAFEXCEL_HIA_GEN_CFG(_sc) ((_sc)->sc_offsets.hia_gen_cfg) 214#define SAFEXCEL_PE(_sc) ((_sc)->sc_offsets.pe) 215 216/* EIP197 base offsets */ 217#define SAFEXCEL_EIP197_HIA_AIC_BASE 0x90000 218#define SAFEXCEL_EIP197_HIA_AIC_G_BASE 0x90000 219#define SAFEXCEL_EIP197_HIA_AIC_R_BASE 0x90800 220#define SAFEXCEL_EIP197_HIA_AIC_xDR_BASE 0x80000 221#define SAFEXCEL_EIP197_HIA_DFE_BASE 0x8c000 222#define SAFEXCEL_EIP197_HIA_DFE_THR_BASE 0x8c040 223#define SAFEXCEL_EIP197_HIA_DSE_BASE 0x8d000 224#define SAFEXCEL_EIP197_HIA_DSE_THR_BASE 0x8d040 225#define SAFEXCEL_EIP197_HIA_GEN_CFG_BASE 0xf0000 226#define SAFEXCEL_EIP197_PE_BASE 0xa0000 227 228/* EIP97 base offsets */ 229#define SAFEXCEL_EIP97_HIA_AIC_BASE 0x0 230#define SAFEXCEL_EIP97_HIA_AIC_G_BASE 0x0 231#define SAFEXCEL_EIP97_HIA_AIC_R_BASE 0x0 232#define SAFEXCEL_EIP97_HIA_AIC_xDR_BASE 0x0 233#define SAFEXCEL_EIP97_HIA_DFE_BASE 0xf000 234#define SAFEXCEL_EIP97_HIA_DFE_THR_BASE 0xf200 235#define SAFEXCEL_EIP97_HIA_DSE_BASE 0xf400 236#define SAFEXCEL_EIP97_HIA_DSE_THR_BASE 0xf600 237#define SAFEXCEL_EIP97_HIA_GEN_CFG_BASE 0x10000 238#define SAFEXCEL_EIP97_PE_BASE 0x10000 239 240/* CDR/RDR register offsets */ 241#define SAFEXCEL_HIA_xDR_OFF(priv, r) (SAFEXCEL_HIA_AIC_xDR(priv) + (r) * 0x1000) 242#define SAFEXCEL_HIA_CDR(priv, r) (SAFEXCEL_HIA_xDR_OFF(priv, r)) 243#define SAFEXCEL_HIA_RDR(priv, r) (SAFEXCEL_HIA_xDR_OFF(priv, r) + 0x800) 244#define SAFEXCEL_HIA_xDR_RING_BASE_ADDR_LO 0x0000 245#define SAFEXCEL_HIA_xDR_RING_BASE_ADDR_HI 0x0004 246#define SAFEXCEL_HIA_xDR_RING_SIZE 0x0018 247#define SAFEXCEL_HIA_xDR_DESC_SIZE 0x001c 248#define SAFEXCEL_HIA_xDR_CFG 0x0020 249#define SAFEXCEL_HIA_xDR_DMA_CFG 0x0024 250#define SAFEXCEL_HIA_xDR_THRESH 0x0028 251#define SAFEXCEL_HIA_xDR_PREP_COUNT 0x002c 252#define SAFEXCEL_HIA_xDR_PROC_COUNT 0x0030 253#define SAFEXCEL_HIA_xDR_PREP_PNTR 0x0034 254#define SAFEXCEL_HIA_xDR_PROC_PNTR 0x0038 255#define SAFEXCEL_HIA_xDR_STAT 0x003c 256 257/* register offsets */ 258#define SAFEXCEL_HIA_DFE_CFG(n) (0x000 + (128 * (n))) 259#define SAFEXCEL_HIA_DFE_THR_CTRL(n) (0x000 + (128 * (n))) 260#define SAFEXCEL_HIA_DFE_THR_STAT(n) (0x004 + (128 * (n))) 261#define SAFEXCEL_HIA_DSE_CFG(n) (0x000 + (128 * (n))) 262#define SAFEXCEL_HIA_DSE_THR_CTRL(n) (0x000 + (128 * (n))) 263#define SAFEXCEL_HIA_DSE_THR_STAT(n) (0x004 + (128 * (n))) 264#define SAFEXCEL_HIA_RA_PE_CTRL(n) (0x010 + (8 * (n))) 265#define SAFEXCEL_HIA_RA_PE_STAT 0x0014 266#define SAFEXCEL_HIA_AIC_R_OFF(r) ((r) * 0x1000) 267#define SAFEXCEL_HIA_AIC_R_ENABLE_CTRL(r) (0xe008 - SAFEXCEL_HIA_AIC_R_OFF(r)) 268#define SAFEXCEL_HIA_AIC_R_ENABLED_STAT(r) (0xe010 - SAFEXCEL_HIA_AIC_R_OFF(r)) 269#define SAFEXCEL_HIA_AIC_R_ACK(r) (0xe010 - SAFEXCEL_HIA_AIC_R_OFF(r)) 270#define SAFEXCEL_HIA_AIC_R_ENABLE_CLR(r) (0xe014 - SAFEXCEL_HIA_AIC_R_OFF(r)) 271#define SAFEXCEL_HIA_AIC_R_VERSION(r) (0xe01c - SAFEXCEL_HIA_AIC_R_OFF(r)) 272#define SAFEXCEL_HIA_AIC_G_ENABLE_CTRL 0xf808 273#define SAFEXCEL_HIA_AIC_G_ENABLED_STAT 0xf810 274#define SAFEXCEL_HIA_AIC_G_ACK 0xf810 275#define SAFEXCEL_HIA_MST_CTRL 0xfff4 276#define SAFEXCEL_HIA_OPTIONS 0xfff8 277#define SAFEXCEL_HIA_VERSION 0xfffc 278#define SAFEXCEL_PE_IN_DBUF_THRES(n) (0x0000 + (0x2000 * (n))) 279#define SAFEXCEL_PE_IN_TBUF_THRES(n) (0x0100 + (0x2000 * (n))) 280#define SAFEXCEL_PE_ICE_SCRATCH_RAM(x, n) ((0x800 + (x) * 4) + 0x2000 * (n)) 281#define SAFEXCEL_PE_ICE_PUE_CTRL(n) (0xc80 + (0x2000 * (n))) 282#define SAFEXCEL_PE_ICE_SCRATCH_CTRL 0x0d04 283#define SAFEXCEL_PE_ICE_FPP_CTRL(n) (0xd80 + (0x2000 * (n))) 284#define SAFEXCEL_PE_ICE_RAM_CTRL(n) (0xff0 + (0x2000 * (n))) 285#define SAFEXCEL_PE_EIP96_FUNCTION_EN(n) (0x1004 + (0x2000 * (n))) 286#define SAFEXCEL_PE_EIP96_CONTEXT_CTRL(n) (0x1008 + (0x2000 * (n))) 287#define SAFEXCEL_PE_EIP96_CONTEXT_STAT(n) (0x100c + (0x2000 * (n))) 288#define SAFEXCEL_PE_EIP96_FUNCTION2_EN(n) (0x1030 + (0x2000 * (n))) 289#define SAFEXCEL_PE_OUT_DBUF_THRES(n) (0x1c00 + (0x2000 * (n))) 290#define SAFEXCEL_PE_OUT_TBUF_THRES(n) (0x1d00 + (0x2000 * (n))) 291 292/* EIP-197 Classification Engine */ 293 294/* Classification regs */ 295#define SAFEXCEL_CS_RAM_CTRL 0xf7ff0 296 297/* SAFEXCEL_HIA_xDR_DESC_SIZE */ 298#define SAFEXCEL_xDR_DESC_MODE_64BIT (1U << 31) 299#define SAFEXCEL_CDR_DESC_MODE_ADCP (1 << 30) 300#define SAFEXCEL_xDR_DESC_xD_OFFSET 16 301 302/* SAFEXCEL_DIA_xDR_CFG */ 303#define SAFEXCEL_xDR_xD_FETCH_THRESH 16 304 305/* SAFEXCEL_HIA_xDR_DMA_CFG */ 306#define SAFEXCEL_HIA_xDR_WR_RES_BUF (1 << 22) 307#define SAFEXCEL_HIA_xDR_WR_CTRL_BUF (1 << 23) 308#define SAFEXCEL_HIA_xDR_WR_OWN_BUF (1 << 24) 309#define SAFEXCEL_HIA_xDR_CFG_xD_PROT(n) (((n) & 0xf) << 4) 310#define SAFEXCEL_HIA_xDR_CFG_DATA_PROT(n) (((n) & 0xf) << 12) 311#define SAFEXCEL_HIA_xDR_CFG_ACD_PROT(n) (((n) & 0xf) << 20) 312#define SAFEXCEL_HIA_xDR_CFG_WR_CACHE(n) (((n) & 0x7) << 25) 313#define SAFEXCEL_HIA_xDR_CFG_RD_CACHE(n) (((n) & 0x7) << 29) 314 315/* SAFEXCEL_HIA_CDR_THRESH */ 316#define SAFEXCEL_HIA_CDR_THRESH_PROC_PKT(n) ((n) & 0xffff) 317#define SAFEXCEL_HIA_CDR_THRESH_PROC_MODE (1 << 22) 318#define SAFEXCEL_HIA_CDR_THRESH_PKT_MODE (1 << 23) 319 /* x256 clk cycles */ 320#define SAFEXCEL_HIA_CDR_THRESH_TIMEOUT(n) (((n) & 0xff) << 24) 321 322/* SAFEXCEL_HIA_RDR_THRESH */ 323#define SAFEXCEL_HIA_RDR_THRESH_PROC_PKT(n) ((n) & 0xffff) 324#define SAFEXCEL_HIA_RDR_THRESH_PKT_MODE (1 << 23) 325 /* x256 clk cycles */ 326#define SAFEXCEL_HIA_RDR_THRESH_TIMEOUT(n) (((n) & 0xff) << 24) 327 328/* SAFEXCEL_HIA_xDR_PREP_COUNT */ 329#define SAFEXCEL_xDR_PREP_CLR_COUNT (1U << 31) 330#define SAFEXCEL_xDR_PREP_xD_COUNT_INCR_OFFSET 2 331#define SAFEXCEL_xDR_PREP_RD_COUNT_INCR_MASK 0x3fff 332 333/* SAFEXCEL_HIA_xDR_PROC_COUNT */ 334#define SAFEXCEL_xDR_PROC_xD_PKT_OFFSET 24 335#define SAFEXCEL_xDR_PROC_xD_PKT_MASK 0x7f 336#define SAFEXCEL_xDR_PROC_xD_COUNT(n) ((n) << 2) 337#define SAFEXCEL_xDR_PROC_xD_PKT(n) \ 338 (((n) & SAFEXCEL_xDR_PROC_xD_PKT_MASK) << SAFEXCEL_xDR_PROC_xD_PKT_OFFSET) 339#define SAFEXCEL_xDR_PROC_CLR_COUNT (1U << 31) 340 341/* SAFEXCEL_HIA_xDR_STAT */ 342#define SAFEXCEL_xDR_DMA_ERR (1 << 0) 343#define SAFEXCEL_xDR_PREP_CMD_THRES (1 << 1) 344#define SAFEXCEL_xDR_ERR (1 << 2) 345#define SAFEXCEL_xDR_THRESH (1 << 4) 346#define SAFEXCEL_xDR_TIMEOUT (1 << 5) 347#define SAFEXCEL_CDR_INTR_MASK 0x3f 348#define SAFEXCEL_RDR_INTR_MASK 0xff 349 350#define SAFEXCEL_HIA_RA_PE_CTRL_RESET (1U << 31) 351#define SAFEXCEL_HIA_RA_PE_CTRL_EN (1 << 30) 352 353/* Register offsets */ 354 355/* SAFEXCEL_HIA_DSE_THR_STAT */ 356#define SAFEXCEL_DSE_THR_RDR_ID_MASK 0xf000 357 358/* SAFEXCEL_HIA_OPTIONS */ 359#define SAFEXCEL_OPT_ADDR_64 (1U << 31) 360#define SAFEXCEL_OPT_TGT_ALIGN_OFFSET 28 361#define SAFEXCEL_OPT_TGT_ALIGN_MASK 0x70000000 362#define SAFEXCEL_xDR_HDW_OFFSET 25 363#define SAFEXCEL_xDR_HDW_MASK 0x6000000 364#define SAFEXCEL_N_RINGS_MASK 0xf 365#define SAFEXCEL_N_PES_OFFSET 4 366#define SAFEXCEL_N_PES_MASK 0x1f0 367#define EIP97_N_PES_MASK 0x70 368 369/* SAFEXCEL_HIA_AIC_R_ENABLE_CTRL */ 370#define SAFEXCEL_CDR_IRQ(n) (1 << ((n) * 2)) 371#define SAFEXCEL_RDR_IRQ(n) (1 << ((n) * 2 + 1)) 372 373/* SAFEXCEL_HIA_DFE/DSE_CFG */ 374#define SAFEXCEL_HIA_DxE_CFG_MIN_DATA_SIZE(n) ((n) << 0) 375#define SAFEXCEL_HIA_DxE_CFG_DATA_CACHE_CTRL(n) (((n) & 0x7) << 4) 376#define SAFEXCEL_HIA_DxE_CFG_MAX_DATA_SIZE(n) ((n) << 8) 377#define SAFEXCEL_HIA_DSE_CFG_ALLWAYS_BUFFERABLE 0xc000 378#define SAFEXCEL_HIA_DxE_CFG_MIN_CTRL_SIZE(n) ((n) << 16) 379#define SAFEXCEL_HIA_DxE_CFG_CTRL_CACHE_CTRL(n) (((n) & 0x7) << 20) 380#define SAFEXCEL_HIA_DxE_CFG_MAX_CTRL_SIZE(n) ((n) << 24) 381#define SAFEXCEL_HIA_DFE_CFG_DIS_DEBUG 0xe0000000 382#define SAFEXCEL_HIA_DSE_CFG_EN_SINGLE_WR (1 << 29) 383#define SAFEXCEL_HIA_DSE_CFG_DIS_DEBUG 0xc0000000 384 385/* SAFEXCEL_HIA_DFE/DSE_THR_CTRL */ 386#define SAFEXCEL_DxE_THR_CTRL_EN (1 << 30) 387#define SAFEXCEL_DxE_THR_CTRL_RESET_PE (1U << 31) 388 389/* SAFEXCEL_HIA_AIC_G_ENABLED_STAT */ 390#define SAFEXCEL_G_IRQ_DFE(n) (1 << ((n) << 1)) 391#define SAFEXCEL_G_IRQ_DSE(n) (1 << (((n) << 1) + 1)) 392#define SAFEXCEL_G_IRQ_RING (1 << 16) 393#define SAFEXCEL_G_IRQ_PE(n) (1 << ((n) + 20)) 394 395/* SAFEXCEL_HIA_MST_CTRL */ 396#define RD_CACHE_3BITS 0x5U 397#define WR_CACHE_3BITS 0x3U 398#define RD_CACHE_4BITS (RD_CACHE_3BITS << 1 | (1 << 0)) 399#define WR_CACHE_4BITS (WR_CACHE_3BITS << 1 | (1 << 0)) 400#define SAFEXCEL_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0) 401#define SAFEXCEL_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4) 402#define MST_CTRL_SUPPORT_PROT(n) (((n) & 0xf) << 12) 403#define SAFEXCEL_MST_CTRL_BYTE_SWAP (1 << 24) 404#define SAFEXCEL_MST_CTRL_NO_BYTE_SWAP (1 << 25) 405 406/* SAFEXCEL_PE_IN_DBUF/TBUF_THRES */ 407#define SAFEXCEL_PE_IN_xBUF_THRES_MIN(n) ((n) << 8) 408#define SAFEXCEL_PE_IN_xBUF_THRES_MAX(n) ((n) << 12) 409 410/* SAFEXCEL_PE_OUT_DBUF_THRES */ 411#define SAFEXCEL_PE_OUT_DBUF_THRES_MIN(n) ((n) << 0) 412#define SAFEXCEL_PE_OUT_DBUF_THRES_MAX(n) ((n) << 4) 413 414/* SAFEXCEL_HIA_AIC_G_ACK */ 415#define SAFEXCEL_AIC_G_ACK_ALL_MASK 0xffffffff 416#define SAFEXCEL_AIC_G_ACK_HIA_MASK 0x7ff00000 417 418/* SAFEXCEL_HIA_AIC_R_ENABLE_CLR */ 419#define SAFEXCEL_HIA_AIC_R_ENABLE_CLR_ALL_MASK 0xffffffff 420 421/* SAFEXCEL_PE_EIP96_CONTEXT_CTRL */ 422#define SAFEXCEL_CONTEXT_SIZE(n) (n) 423#define SAFEXCEL_ADDRESS_MODE (1 << 8) 424#define SAFEXCEL_CONTROL_MODE (1 << 9) 425 426/* SAFEXCEL_PE_EIP96_FUNCTION_EN */ 427#define SAFEXCEL_FUNCTION_RSVD ((1U << 6) | (1U << 15) | (1U << 20) | (1U << 23)) 428#define SAFEXCEL_PROTOCOL_HASH_ONLY (1U << 0) 429#define SAFEXCEL_PROTOCOL_ENCRYPT_ONLY (1U << 1) 430#define SAFEXCEL_PROTOCOL_HASH_ENCRYPT (1U << 2) 431#define SAFEXCEL_PROTOCOL_HASH_DECRYPT (1U << 3) 432#define SAFEXCEL_PROTOCOL_ENCRYPT_HASH (1U << 4) 433#define SAFEXCEL_PROTOCOL_DECRYPT_HASH (1U << 5) 434#define SAFEXCEL_ALG_ARC4 (1U << 7) 435#define SAFEXCEL_ALG_AES_ECB (1U << 8) 436#define SAFEXCEL_ALG_AES_CBC (1U << 9) 437#define SAFEXCEL_ALG_AES_CTR_ICM (1U << 10) 438#define SAFEXCEL_ALG_AES_OFB (1U << 11) 439#define SAFEXCEL_ALG_AES_CFB (1U << 12) 440#define SAFEXCEL_ALG_DES_ECB (1U << 13) 441#define SAFEXCEL_ALG_DES_CBC (1U << 14) 442#define SAFEXCEL_ALG_DES_OFB (1U << 16) 443#define SAFEXCEL_ALG_DES_CFB (1U << 17) 444#define SAFEXCEL_ALG_3DES_ECB (1U << 18) 445#define SAFEXCEL_ALG_3DES_CBC (1U << 19) 446#define SAFEXCEL_ALG_3DES_OFB (1U << 21) 447#define SAFEXCEL_ALG_3DES_CFB (1U << 22) 448#define SAFEXCEL_ALG_MD5 (1U << 24) 449#define SAFEXCEL_ALG_HMAC_MD5 (1U << 25) 450#define SAFEXCEL_ALG_SHA1 (1U << 26) 451#define SAFEXCEL_ALG_HMAC_SHA1 (1U << 27) 452#define SAFEXCEL_ALG_SHA2 (1U << 28) 453#define SAFEXCEL_ALG_HMAC_SHA2 (1U << 29) 454#define SAFEXCEL_ALG_AES_XCBC_MAC (1U << 30) 455#define SAFEXCEL_ALG_GCM_HASH (1U << 31) 456 457#endif /* _SAFEXCEL_REGS_H_ */ 458