1/*- 2 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29#ifndef R12A_REG_H 30#define R12A_REG_H 31 32#include <dev/rtwn/rtl8188e/r88e_reg.h> 33 34/* 35 * MAC registers. 36 */ 37/* System Configuration. */ 38#define R12A_SDIO_CTRL 0x070 39#define R12A_RF_B_CTRL 0x076 40/* Rx DMA Configuration. */ 41#define R12A_RXDMA_PRO 0x290 42#define R12A_EARLY_MODE_CONTROL 0x2bc 43/* Protocol Configuration. */ 44#define R12A_TXPKT_EMPTY 0x41a 45#define R12A_ARFR_5G(i) (0x444 + (i) * 8) 46#define R12A_CCK_CHECK 0x454 47#define R12A_AMPDU_MAX_TIME 0x456 48#define R12A_AMPDU_MAX_LENGTH R92C_AGGLEN_LMT 49#define R12A_DATA_SEC 0x483 50#define R12A_ARFR_2G(i) (0x48c + (i) * 8) 51#define R12A_HT_SINGLE_AMPDU 0x4c7 52 53/* Bits for R92C_MAC_PHY_CTRL. */ 54#define R12A_MAC_PHY_CRYSTALCAP_M 0x7ff80000 55#define R12A_MAC_PHY_CRYSTALCAP_S 19 56 57/* Bits for R92C_LEDCFG2. */ 58#define R12A_LEDCFG2_ENA 0x20 59 60/* Bits for R12A_RXDMA_PRO. */ 61#define R12A_DMA_MODE 0x02 62#define R12A_BURST_CNT_M 0x0c 63#define R12A_BURST_CNT_S 2 64#define R12A_BURST_SZ_M 0x30 65#define R12A_BURST_SZ_S 4 66#define R12A_BURST_SZ_USB3 0 67#define R12A_BURST_SZ_USB2 1 68#define R12A_BURST_SZ_USB1 2 69 70/* Bits for R12A_CCK_CHECK. */ 71#define R12A_CCK_CHECK_BCN1 0x20 72#define R12A_CCK_CHECK_5GHZ 0x80 73 74/* Bits for R12A_DATA_SEC. */ 75#define R12A_DATA_SEC_NO_EXT 0x00 76#define R12A_DATA_SEC_PRIM_UP_20 0x01 77#define R12A_DATA_SEC_PRIM_DOWN_20 0x02 78#define R12A_DATA_SEC_PRIM_UPPER_20 0x03 79#define R12A_DATA_SEC_PRIM_LOWER_20 0x04 80#define R12A_DATA_SEC_PRIM_UP_40 0x90 81#define R12A_DATA_SEC_PRIM_DOWN_40 0xa0 82 83/* Bits for R12A_HT_SINGLE_AMPDU. */ 84#define R12A_HT_SINGLE_AMPDU_PKT_ENA 0x80 85 86/* Bits for R92C_RCR. */ 87#define R12A_RCR_DIS_CHK_14 0x00200000 88#define R12A_RCR_TCP_OFFLD_EN 0x02000000 89#define R12A_RCR_VHT_ACK 0x04000000 90 91/* 92 * Baseband registers. 93 */ 94#define R12A_CCK_RPT_FORMAT 0x804 95#define R12A_OFDMCCK_EN 0x808 96#define R12A_RX_PATH R12A_OFDMCCK_EN 97#define R12A_TX_PATH 0x80c 98#define R12A_TXAGC_TABLE_SELECT 0x82c 99#define R12A_PWED_TH 0x830 100#define R12A_BW_INDICATION 0x834 101#define R12A_CCA_ON_SEC 0x838 102#define R12A_L1_PEAK_TH 0x848 103#define R12A_FC_AREA 0x860 104#define R12A_RFMOD 0x8ac 105#define R12A_HSSI_PARAM2 0x8b0 106#define R12A_ADC_BUF_CLK 0x8c4 107#define R12A_ANTSEL_SW 0x900 108#define R12A_SINGLETONE_CONT_TX 0x914 109#define R12A_CCK_RX_PATH 0xa04 110#define R12A_HSSI_PARAM1(chain) (0xc00 + (chain) * 0x200) 111#define R12A_TX_SCALE(chain) (0xc1c + (chain) * 0x200) 112#define R12A_TXAGC_CCK11_1(chain) (0xc20 + (chain) * 0x200) 113#define R12A_TXAGC_OFDM18_6(chain) (0xc24 + (chain) * 0x200) 114#define R12A_TXAGC_OFDM54_24(chain) (0xc28 + (chain) * 0x200) 115#define R12A_TXAGC_MCS3_0(chain) (0xc2c + (chain) * 0x200) 116#define R12A_TXAGC_MCS7_4(chain) (0xc30 + (chain) * 0x200) 117#define R12A_TXAGC_MCS11_8(chain) (0xc34 + (chain) * 0x200) 118#define R12A_TXAGC_MCS15_12(chain) (0xc38 + (chain) * 0x200) 119#define R12A_TXAGC_NSS1IX3_1IX0(chain) (0xc3c + (chain) * 0x200) 120#define R12A_TXAGC_NSS1IX7_1IX4(chain) (0xc40 + (chain) * 0x200) 121#define R12A_TXAGC_NSS2IX1_1IX8(chain) (0xc44 + (chain) * 0x200) 122#define R12A_TXAGC_NSS2IX5_2IX2(chain) (0xc48 + (chain) * 0x200) 123#define R12A_TXAGC_NSS2IX9_2IX6(chain) (0xc4c + (chain) * 0x200) 124#define R12A_INITIAL_GAIN(chain) (0xc50 + (chain) * 0x200) 125#define R12A_AFE_POWER_1(chain) (0xc60 + (chain) * 0x200) 126#define R12A_AFE_POWER_2(chain) (0xc64 + (chain) * 0x200) 127#define R12A_SLEEP_NAV(chain) (0xc80 + (chain) * 0x200) 128#define R12A_PMPD(chain) (0xc84 + (chain) * 0x200) 129#define R12A_LSSI_PARAM(chain) (0xc90 + (chain) * 0x200) 130#define R12A_RFE_PINMUX(chain) (0xcb0 + (chain) * 0x200) 131#define R12A_RFE_INV(chain) (0xcb4 + (chain) * 0x200) 132#define R12A_RFE(chain) (0xcb8 + (chain) * 0x200) 133#define R12A_HSPI_READBACK(chain) (0xd04 + (chain) * 0x40) 134#define R12A_LSSI_READBACK(chain) (0xd08 + (chain) * 0x40) 135 136/* Bits for R12A_CCK_RPT_FORMAT. */ 137#define R12A_CCK_RPT_FORMAT_HIPWR 0x00010000 138 139/* Bits for R12A_OFDMCCK_EN. */ 140#define R12A_OFDMCCK_EN_CCK 0x10000000 141#define R12A_OFDMCCK_EN_OFDM 0x20000000 142 143/* Bits for R12A_CCA_ON_SEC. */ 144#define R12A_CCA_ON_SEC_EXT_CHAN_M 0xf0000000 145#define R12A_CCA_ON_SEC_EXT_CHAN_S 28 146 147/* Bits for R12A_RFE_PINMUX(i). */ 148#define R12A_RFE_PINMUX_PA_A_MASK 0x000000f0 149#define R12A_RFE_PINMUX_LNA_MASK 0x0000f000 150 151/* Bits for R12A_RFMOD. */ 152#define R12A_RFMOD_EXT_CHAN_M 0x3C 153#define R12A_RFMOD_EXT_CHAN_S 2 154 155/* Bits for R12A_HSSI_PARAM2. */ 156#define R12A_HSSI_PARAM2_READ_ADDR_MASK 0xff 157 158/* Bits for R12A_HSSI_PARAM1(i). */ 159#define R12A_HSSI_PARAM1_PI 0x00000004 160 161/* Bits for R12A_TX_SCALE(i). */ 162#define R12A_TX_SCALE_SWING_M 0xffe00000 163#define R12A_TX_SCALE_SWING_S 21 164 165/* Bits for R12A_TXAGC_CCK11_1(i). */ 166#define R12A_TXAGC_CCK1_M 0x000000ff 167#define R12A_TXAGC_CCK1_S 0 168#define R12A_TXAGC_CCK2_M 0x0000ff00 169#define R12A_TXAGC_CCK2_S 8 170#define R12A_TXAGC_CCK55_M 0x00ff0000 171#define R12A_TXAGC_CCK55_S 16 172#define R12A_TXAGC_CCK11_M 0xff000000 173#define R12A_TXAGC_CCK11_S 24 174 175/* Bits for R12A_TXAGC_OFDM18_6(i). */ 176#define R12A_TXAGC_OFDM06_M 0x000000ff 177#define R12A_TXAGC_OFDM06_S 0 178#define R12A_TXAGC_OFDM09_M 0x0000ff00 179#define R12A_TXAGC_OFDM09_S 8 180#define R12A_TXAGC_OFDM12_M 0x00ff0000 181#define R12A_TXAGC_OFDM12_S 16 182#define R12A_TXAGC_OFDM18_M 0xff000000 183#define R12A_TXAGC_OFDM18_S 24 184 185/* Bits for R12A_TXAGC_OFDM54_24(i). */ 186#define R12A_TXAGC_OFDM24_M 0x000000ff 187#define R12A_TXAGC_OFDM24_S 0 188#define R12A_TXAGC_OFDM36_M 0x0000ff00 189#define R12A_TXAGC_OFDM36_S 8 190#define R12A_TXAGC_OFDM48_M 0x00ff0000 191#define R12A_TXAGC_OFDM48_S 16 192#define R12A_TXAGC_OFDM54_M 0xff000000 193#define R12A_TXAGC_OFDM54_S 24 194 195/* Bits for R12A_TXAGC_MCS3_0(i). */ 196#define R12A_TXAGC_MCS0_M 0x000000ff 197#define R12A_TXAGC_MCS0_S 0 198#define R12A_TXAGC_MCS1_M 0x0000ff00 199#define R12A_TXAGC_MCS1_S 8 200#define R12A_TXAGC_MCS2_M 0x00ff0000 201#define R12A_TXAGC_MCS2_S 16 202#define R12A_TXAGC_MCS3_M 0xff000000 203#define R12A_TXAGC_MCS3_S 24 204 205/* Bits for R12A_TXAGC_MCS7_4(i). */ 206#define R12A_TXAGC_MCS4_M 0x000000ff 207#define R12A_TXAGC_MCS4_S 0 208#define R12A_TXAGC_MCS5_M 0x0000ff00 209#define R12A_TXAGC_MCS5_S 8 210#define R12A_TXAGC_MCS6_M 0x00ff0000 211#define R12A_TXAGC_MCS6_S 16 212#define R12A_TXAGC_MCS7_M 0xff000000 213#define R12A_TXAGC_MCS7_S 24 214 215/* Bits for R12A_TXAGC_MCS11_8(i). */ 216#define R12A_TXAGC_MCS8_M 0x000000ff 217#define R12A_TXAGC_MCS8_S 0 218#define R12A_TXAGC_MCS9_M 0x0000ff00 219#define R12A_TXAGC_MCS9_S 8 220#define R12A_TXAGC_MCS10_M 0x00ff0000 221#define R12A_TXAGC_MCS10_S 16 222#define R12A_TXAGC_MCS11_M 0xff000000 223#define R12A_TXAGC_MCS11_S 24 224 225/* Bits for R12A_TXAGC_MCS15_12(i). */ 226#define R12A_TXAGC_MCS12_M 0x000000ff 227#define R12A_TXAGC_MCS12_S 0 228#define R12A_TXAGC_MCS13_M 0x0000ff00 229#define R12A_TXAGC_MCS13_S 8 230#define R12A_TXAGC_MCS14_M 0x00ff0000 231#define R12A_TXAGC_MCS14_S 16 232#define R12A_TXAGC_MCS15_M 0xff000000 233#define R12A_TXAGC_MCS15_S 24 234 235/* 236 * RF (6052) registers. 237 */ 238#define R12A_RF_LCK 0xb4 239 240/* Bits for R12A_RF_LCK. */ 241#define R12A_RF_LCK_MODE 0x4000 242 243#endif /* R12A_REG_H */ 244