1/*- 2 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include "opt_wlan.h" 31 32#include <sys/param.h> 33#include <sys/lock.h> 34#include <sys/mutex.h> 35#include <sys/mbuf.h> 36#include <sys/kernel.h> 37#include <sys/socket.h> 38#include <sys/systm.h> 39#include <sys/malloc.h> 40#include <sys/queue.h> 41#include <sys/taskqueue.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/linker.h> 45 46#include <net/if.h> 47#include <net/ethernet.h> 48#include <net/if_media.h> 49 50#include <net80211/ieee80211_var.h> 51#include <net80211/ieee80211_radiotap.h> 52 53#include <dev/rtwn/if_rtwnreg.h> 54#include <dev/rtwn/if_rtwnvar.h> 55 56#include <dev/rtwn/if_rtwn_debug.h> 57 58#include <dev/rtwn/rtl8192c/r92c.h> 59 60#include <dev/rtwn/rtl8812a/r12a.h> 61#include <dev/rtwn/rtl8812a/r12a_priv.h> 62#include <dev/rtwn/rtl8812a/r12a_reg.h> 63#include <dev/rtwn/rtl8812a/r12a_var.h> 64 65int 66r12a_check_condition(struct rtwn_softc *sc, const uint8_t cond[]) 67{ 68 struct r12a_softc *rs = sc->sc_priv; 69 uint8_t mask[4]; 70 int i, j, nmasks; 71 72 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 73 "%s: condition byte 0: %02X; ext PA/LNA: %d/%d (2 GHz), " 74 "%d/%d (5 GHz)\n", __func__, cond[0], rs->ext_pa_2g, 75 rs->ext_lna_2g, rs->ext_pa_5g, rs->ext_lna_5g); 76 77 if (cond[0] == 0) 78 return (1); 79 80 if (!rs->ext_pa_2g && !rs->ext_lna_2g && 81 !rs->ext_pa_5g && !rs->ext_lna_5g) 82 return (0); 83 84 nmasks = 0; 85 if (rs->ext_pa_2g) { 86 mask[nmasks] = R12A_COND_GPA; 87 mask[nmasks] |= R12A_COND_TYPE(rs->type_pa_2g); 88 nmasks++; 89 } 90 if (rs->ext_pa_5g) { 91 mask[nmasks] = R12A_COND_APA; 92 mask[nmasks] |= R12A_COND_TYPE(rs->type_pa_5g); 93 nmasks++; 94 } 95 if (rs->ext_lna_2g) { 96 mask[nmasks] = R12A_COND_GLNA; 97 mask[nmasks] |= R12A_COND_TYPE(rs->type_lna_2g); 98 nmasks++; 99 } 100 if (rs->ext_lna_5g) { 101 mask[nmasks] = R12A_COND_ALNA; 102 mask[nmasks] |= R12A_COND_TYPE(rs->type_lna_5g); 103 nmasks++; 104 } 105 106 for (i = 0; i < RTWN_MAX_CONDITIONS && cond[i] != 0; i++) 107 for (j = 0; j < nmasks; j++) 108 if ((cond[i] & mask[j]) == mask[j]) 109 return (1); 110 111 return (0); 112} 113 114int 115r12a_set_page_size(struct rtwn_softc *sc) 116{ 117 return (rtwn_setbits_1(sc, R92C_PBP, R92C_PBP_PSTX_M, 118 R92C_PBP_512 << R92C_PBP_PSTX_S) == 0); 119} 120 121void 122r12a_init_edca(struct rtwn_softc *sc) 123{ 124 r92c_init_edca(sc); 125 126 /* 80 MHz clock */ 127 rtwn_write_1(sc, R92C_USTIME_TSF, 0x50); 128 rtwn_write_1(sc, R92C_USTIME_EDCA, 0x50); 129} 130 131void 132r12a_init_bb(struct rtwn_softc *sc) 133{ 134 int i, j; 135 136 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, 0, R92C_SYS_FUNC_EN_USBA); 137 138 /* Enable BB and RF. */ 139 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, 0, 140 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST); 141 142 /* PathA RF Power On. */ 143 rtwn_write_1(sc, R92C_RF_CTRL, 144 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 145 146 /* PathB RF Power On. */ 147 rtwn_write_1(sc, R12A_RF_B_CTRL, 148 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 149 150 /* Write BB initialization values. */ 151 for (i = 0; i < sc->bb_size; i++) { 152 const struct rtwn_bb_prog *bb_prog = &sc->bb_prog[i]; 153 154 while (!rtwn_check_condition(sc, bb_prog->cond)) { 155 KASSERT(bb_prog->next != NULL, 156 ("%s: wrong condition value (i %d)\n", 157 __func__, i)); 158 bb_prog = bb_prog->next; 159 } 160 161 for (j = 0; j < bb_prog->count; j++) { 162 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 163 "BB: reg 0x%03x, val 0x%08x\n", 164 bb_prog->reg[j], bb_prog->val[j]); 165 166 rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]); 167 rtwn_delay(sc, 1); 168 } 169 } 170 171 /* XXX meshpoint mode? */ 172 173 /* Write AGC values. */ 174 for (i = 0; i < sc->agc_size; i++) { 175 const struct rtwn_agc_prog *agc_prog = &sc->agc_prog[i]; 176 177 while (!rtwn_check_condition(sc, agc_prog->cond)) { 178 KASSERT(agc_prog->next != NULL, 179 ("%s: wrong condition value (2) (i %d)\n", 180 __func__, i)); 181 agc_prog = agc_prog->next; 182 } 183 184 for (j = 0; j < agc_prog->count; j++) { 185 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 186 "AGC: val 0x%08x\n", agc_prog->val[j]); 187 188 rtwn_bb_write(sc, 0x81c, agc_prog->val[j]); 189 rtwn_delay(sc, 1); 190 } 191 } 192 193 for (i = 0; i < sc->nrxchains; i++) { 194 rtwn_bb_write(sc, R12A_INITIAL_GAIN(i), 0x22); 195 rtwn_delay(sc, 1); 196 rtwn_bb_write(sc, R12A_INITIAL_GAIN(i), 0x20); 197 rtwn_delay(sc, 1); 198 } 199 200 rtwn_r12a_crystalcap_write(sc); 201 202 if (rtwn_bb_read(sc, R12A_CCK_RPT_FORMAT) & R12A_CCK_RPT_FORMAT_HIPWR) 203 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 204} 205 206void 207r12a_init_rf(struct rtwn_softc *sc) 208{ 209 int chain, i; 210 211 for (chain = 0, i = 0; chain < sc->nrxchains; chain++, i++) { 212 /* Write RF initialization values for this chain. */ 213 i += r92c_init_rf_chain(sc, &sc->rf_prog[i], chain); 214 } 215} 216 217void 218r12a_crystalcap_write(struct rtwn_softc *sc) 219{ 220 struct r12a_softc *rs = sc->sc_priv; 221 uint32_t reg; 222 uint8_t val; 223 224 val = rs->crystalcap & 0x3f; 225 reg = rtwn_bb_read(sc, R92C_MAC_PHY_CTRL); 226 reg = RW(reg, R12A_MAC_PHY_CRYSTALCAP, val | (val << 6)); 227 rtwn_bb_write(sc, R92C_MAC_PHY_CTRL, reg); 228} 229 230static void 231r12a_rf_init_workaround(struct rtwn_softc *sc) 232{ 233 234 rtwn_write_1(sc, R92C_RF_CTRL, 235 R92C_RF_CTRL_EN | R92C_RF_CTRL_SDMRSTB); 236 rtwn_write_1(sc, R92C_RF_CTRL, 237 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | 238 R92C_RF_CTRL_SDMRSTB); 239 rtwn_write_1(sc, R12A_RF_B_CTRL, 240 R92C_RF_CTRL_EN | R92C_RF_CTRL_SDMRSTB); 241 rtwn_write_1(sc, R12A_RF_B_CTRL, 242 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | 243 R92C_RF_CTRL_SDMRSTB); 244} 245 246int 247r12a_power_on(struct rtwn_softc *sc) 248{ 249#define RTWN_CHK(res) do { \ 250 if (res != 0) \ 251 return (EIO); \ 252} while(0) 253 int ntries; 254 255 r12a_rf_init_workaround(sc); 256 257 /* Force PWM mode. */ 258 RTWN_CHK(rtwn_setbits_1(sc, R92C_SPS0_CTRL + 1, 0, 0x01)); 259 260 /* Turn off ZCD. */ 261 RTWN_CHK(rtwn_setbits_2(sc, 0x014, 0x0180, 0)); 262 263 /* Enable LDO normal mode. */ 264 RTWN_CHK(rtwn_setbits_1(sc, R92C_LPLDO_CTRL, R92C_LPLDO_CTRL_SLEEP, 265 0)); 266 267 /* GPIO 0...7 input mode. */ 268 RTWN_CHK(rtwn_write_1(sc, R92C_GPIO_IOSEL, 0)); 269 270 /* GPIO 11...8 input mode. */ 271 RTWN_CHK(rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0)); 272 273 /* Enable WL suspend. */ 274 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 275 R92C_APS_FSMCO_AFSM_HSUS, 0, 1)); 276 277 /* Enable 8051. */ 278 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, 279 0, R92C_SYS_FUNC_EN_CPUEN, 1)); 280 281 /* Disable SW LPS. */ 282 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 283 R92C_APS_FSMCO_APFM_RSM, 0, 1)); 284 285 /* Wait for power ready bit. */ 286 for (ntries = 0; ntries < 5000; ntries++) { 287 if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 288 break; 289 rtwn_delay(sc, 10); 290 } 291 if (ntries == 5000) { 292 device_printf(sc->sc_dev, 293 "timeout waiting for chip power up\n"); 294 return (ETIMEDOUT); 295 } 296 297 /* Disable WL suspend. */ 298 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 299 R92C_APS_FSMCO_AFSM_HSUS, 0, 1)); 300 301 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, 302 R92C_APS_FSMCO_APFM_ONMAC, 1)); 303 for (ntries = 0; ntries < 5000; ntries++) { 304 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & 305 R92C_APS_FSMCO_APFM_ONMAC)) 306 break; 307 rtwn_delay(sc, 10); 308 } 309 if (ntries == 5000) 310 return (ETIMEDOUT); 311 312 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 313 RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0x0000)); 314 RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0, 315 R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN | 316 R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN | 317 R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN | 318 ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) | 319 R92C_CR_CALTMR_EN)); 320 321 return (0); 322} 323 324void 325r12a_power_off(struct rtwn_softc *sc) 326{ 327 struct r12a_softc *rs = sc->sc_priv; 328 int error, ntries; 329 330 /* Stop Rx. */ 331 error = rtwn_write_1(sc, R92C_CR, 0); 332 if (error == ENXIO) /* hardware gone */ 333 return; 334 335 /* Move card to Low Power state. */ 336 /* Block all Tx queues. */ 337 rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 338 339 for (ntries = 0; ntries < 10; ntries++) { 340 /* Should be zero if no packet is transmitting. */ 341 if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0) 342 break; 343 344 rtwn_delay(sc, 5000); 345 } 346 if (ntries == 10) { 347 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n", 348 __func__); 349 return; 350 } 351 352 /* Turn off 3-wire. */ 353 rtwn_write_1(sc, R12A_HSSI_PARAM1(0), 0x04); 354 rtwn_write_1(sc, R12A_HSSI_PARAM1(1), 0x04); 355 356 /* CCK and OFDM are disabled, and clock are gated. */ 357 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0); 358 359 rtwn_delay(sc, 1); 360 361 /* Reset whole BB. */ 362 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0); 363 364 /* Reset MAC TRX. */ 365 rtwn_write_1(sc, R92C_CR, 366 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN); 367 368 /* check if removed later. (?) */ 369 rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1); 370 371 /* Respond TxOK to scheduler */ 372 rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, R92C_DUAL_TSF_RST_TXOK); 373 374 /* If firmware in ram code, do reset. */ 375#ifndef RTWN_WITHOUT_UCODE 376 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 377 r12a_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN); 378#endif 379 380 /* Reset MCU. */ 381 rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_CPUEN, 382 0, 1); 383 rtwn_write_1(sc, R92C_MCUFWDL, 0); 384 385 /* Move card to Disabled state. */ 386 /* Turn off 3-wire. */ 387 rtwn_write_1(sc, R12A_HSSI_PARAM1(0), 0x04); 388 rtwn_write_1(sc, R12A_HSSI_PARAM1(1), 0x04); 389 390 /* Reset BB, close RF. */ 391 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0); 392 393 rtwn_delay(sc, 1); 394 395 /* SPS PWM mode. */ 396 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff, 397 R92C_APS_FSMCO_SOP_RCK | R92C_APS_FSMCO_SOP_ABG, 3); 398 399 /* ANA clock = 500k. */ 400 rtwn_setbits_1(sc, R92C_SYS_CLKR, R92C_SYS_CLKR_ANA8M, 0); 401 402 /* Turn off MAC by HW state machine */ 403 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_OFF, 404 1); 405 for (ntries = 0; ntries < 10; ntries++) { 406 /* Wait until it will be disabled. */ 407 if ((rtwn_read_2(sc, R92C_APS_FSMCO) & 408 R92C_APS_FSMCO_APFM_OFF) == 0) 409 break; 410 411 rtwn_delay(sc, 5000); 412 } 413 if (ntries == 10) { 414 device_printf(sc->sc_dev, "%s: could not turn off MAC\n", 415 __func__); 416 return; 417 } 418 419 /* Reset 8051. */ 420 rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_CPUEN, 421 0, 1); 422 423 /* Fill the default value of host_CPU handshake field. */ 424 rtwn_write_1(sc, R92C_MCUFWDL, 425 R92C_MCUFWDL_EN | R92C_MCUFWDL_CHKSUM_RPT); 426 427 rtwn_setbits_1(sc, R92C_GPIO_IO_SEL, 0xf0, 0xc0); 428 429 /* GPIO 11 input mode, 10...8 output mode. */ 430 rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0x07); 431 432 /* GPIO 7...0, output = input */ 433 rtwn_write_1(sc, R92C_GPIO_OUT, 0); 434 435 /* GPIO 7...0 output mode. */ 436 rtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff); 437 438 rtwn_write_1(sc, R92C_GPIO_MOD, 0); 439 440 /* Turn on ZCD. */ 441 rtwn_setbits_2(sc, 0x014, 0, 0x0180); 442 443 /* Force PFM mode. */ 444 rtwn_setbits_1(sc, R92C_SPS0_CTRL + 1, 0x01, 0); 445 446 /* LDO sleep mode. */ 447 rtwn_setbits_1(sc, R92C_LPLDO_CTRL, 0, R92C_LPLDO_CTRL_SLEEP); 448 449 /* ANA clock = 500k. */ 450 rtwn_setbits_1(sc, R92C_SYS_CLKR, R92C_SYS_CLKR_ANA8M, 0); 451 452 /* SOP option to disable BG/MB. */ 453 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff, 454 R92C_APS_FSMCO_SOP_RCK, 3); 455 456 /* Disable RFC_0. */ 457 rtwn_setbits_1(sc, R92C_RF_CTRL, R92C_RF_CTRL_RSTB, 0); 458 459 /* Disable RFC_1. */ 460 rtwn_setbits_1(sc, R12A_RF_B_CTRL, R92C_RF_CTRL_RSTB, 0); 461 462 /* Enable WL suspend. */ 463 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_AFSM_HSUS, 464 1); 465 466 rs->rs_flags &= ~R12A_IQK_RUNNING; 467} 468 469void 470r12a_init_intr(struct rtwn_softc *sc) 471{ 472 rtwn_write_4(sc, R88E_HIMR, 0); 473 rtwn_write_4(sc, R88E_HIMRE, 0); 474} 475 476void 477r12a_init_antsel(struct rtwn_softc *sc) 478{ 479 uint32_t reg; 480 481 rtwn_write_1(sc, R92C_LEDCFG2, 0x82); 482 rtwn_bb_setbits(sc, R92C_FPGA0_RFPARAM(0), 0, 0x2000); 483 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0)); 484 sc->sc_ant = MS(reg, R92C_FPGA0_RFIFACEOE0_ANT); 485} 486