1/*- 2 * Copyright (c) 2016 Alexander Motin <mav@FreeBSD.org> 3 * Copyright (C) 2013 Intel Corporation 4 * Copyright (C) 2015 EMC Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31#ifndef _NTB_REGS_H_ 32#define _NTB_REGS_H_ 33#include <sys/types.h> 34#include <sys/stdint.h> 35 36/*--------------------------------------------------------------------------- 37 * Macro: M*_M : Create a mask to isolate a bit field of a data word. 38 * M*_F : Extract value from a bit field of a data word. 39 * M*_I : Insert value into a bit field of a data word. 40 * 41 * Purpose: Bit field manipulation macros for mask, insert and extract for 42 * 8-bit, 16-bit, 32-bit and 64-bit data words. 43 * 44 * Params: [in] P = Bit position of start of the bit field (lsb is 0). 45 * [in] N = Size of the bit field in bits. 46 * [in] X = Value to insert or remove from the bit field. 47 *--------------------------------------------------------------------------- 48 */ 49#define M8_M(P, N) ((UINT8_MAX >> (8 - (N))) << (P)) 50#define M8_F(X, P, N) (((uint8_t)(X) & M8_M(P, N)) >> (P)) 51#define M8_I(X, P, N) (((uint8_t)(X) << (P)) & M8_M(P, N)) 52 53#define NTB_LINK_STATUS_ACTIVE 0x2000 54#define NTB_LINK_SPEED_MASK 0x000f 55#define NTB_LINK_WIDTH_MASK 0x03f0 56#define NTB_LNK_STA_WIDTH(sta) (((sta) & NTB_LINK_WIDTH_MASK) >> 4) 57 58#define XEON_SNB_MW_COUNT 2 59#define XEON_HSX_SPLIT_MW_COUNT 3 60/* Reserve the uppermost bit for link interrupt */ 61#define XEON_DB_COUNT 15 62#define XEON_DB_TOTAL_SHIFT 16 63#define XEON_DB_LINK 15 64#define XEON_DB_MSIX_VECTOR_COUNT 4 65#define XEON_DB_MSIX_VECTOR_SHIFT 5 66#define XEON_DB_LINK_BIT (1 << XEON_DB_LINK) 67#define XEON_NONLINK_DB_MSIX_BITS 3 68 69#define XEON_SPCICMD_OFFSET 0x0504 70#define XEON_DEVCTRL_OFFSET 0x0598 71#define XEON_DEVSTS_OFFSET 0x059a 72#define XEON_LINK_STATUS_OFFSET 0x01a2 73#define XEON_SLINK_STATUS_OFFSET 0x05a2 74 75#define XEON_PBAR2LMT_OFFSET 0x0000 76#define XEON_PBAR4LMT_OFFSET 0x0008 77#define XEON_PBAR5LMT_OFFSET 0x000c 78#define XEON_PBAR2XLAT_OFFSET 0x0010 79#define XEON_PBAR4XLAT_OFFSET 0x0018 80#define XEON_PBAR5XLAT_OFFSET 0x001c 81#define XEON_SBAR2LMT_OFFSET 0x0020 82#define XEON_SBAR4LMT_OFFSET 0x0028 83#define XEON_SBAR5LMT_OFFSET 0x002c 84#define XEON_SBAR2XLAT_OFFSET 0x0030 85#define XEON_SBAR4XLAT_OFFSET 0x0038 86#define XEON_SBAR5XLAT_OFFSET 0x003c 87#define XEON_SBAR0BASE_OFFSET 0x0040 88#define XEON_SBAR2BASE_OFFSET 0x0048 89#define XEON_SBAR4BASE_OFFSET 0x0050 90#define XEON_SBAR5BASE_OFFSET 0x0054 91#define XEON_NTBCNTL_OFFSET 0x0058 92#define XEON_SBDF_OFFSET 0x005c 93#define XEON_PDOORBELL_OFFSET 0x0060 94#define XEON_PDBMSK_OFFSET 0x0062 95#define XEON_SDOORBELL_OFFSET 0x0064 96#define XEON_SDBMSK_OFFSET 0x0066 97#define XEON_USMEMMISS_OFFSET 0x0070 98#define XEON_SPAD_OFFSET 0x0080 99#define XEON_SPAD_COUNT 16 100#define XEON_SPADSEMA4_OFFSET 0x00c0 101#define XEON_WCCNTRL_OFFSET 0x00e0 102#define XEON_UNCERRSTS_OFFSET 0x014c 103#define XEON_CORERRSTS_OFFSET 0x0158 104#define XEON_B2B_SPAD_OFFSET 0x0100 105#define XEON_B2B_DOORBELL_OFFSET 0x0140 106#define XEON_B2B_XLAT_OFFSETL 0x0144 107#define XEON_B2B_XLAT_OFFSETU 0x0148 108 109#define ATOM_MW_COUNT 2 110#define ATOM_DB_COUNT 34 111#define ATOM_DB_MSIX_VECTOR_COUNT 34 112#define ATOM_DB_MSIX_VECTOR_SHIFT 1 113 114#define ATOM_SPCICMD_OFFSET 0xb004 115#define ATOM_MBAR23_OFFSET 0xb018 116#define ATOM_MBAR45_OFFSET 0xb020 117#define ATOM_DEVCTRL_OFFSET 0xb048 118#define ATOM_LINK_STATUS_OFFSET 0xb052 119#define ATOM_ERRCORSTS_OFFSET 0xb110 120 121#define ATOM_SBAR2XLAT_OFFSET 0x0008 122#define ATOM_SBAR4XLAT_OFFSET 0x0010 123#define ATOM_PDOORBELL_OFFSET 0x0020 124#define ATOM_PDBMSK_OFFSET 0x0028 125#define ATOM_NTBCNTL_OFFSET 0x0060 126#define ATOM_EBDF_OFFSET 0x0064 127#define ATOM_SPAD_OFFSET 0x0080 128#define ATOM_SPAD_COUNT 16 129#define ATOM_SPADSEMA_OFFSET 0x00c0 130#define ATOM_STKYSPAD_OFFSET 0x00c4 131#define ATOM_PBAR2XLAT_OFFSET 0x8008 132#define ATOM_PBAR4XLAT_OFFSET 0x8010 133#define ATOM_B2B_DOORBELL_OFFSET 0x8020 134#define ATOM_B2B_SPAD_OFFSET 0x8080 135#define ATOM_B2B_SPADSEMA_OFFSET 0x80c0 136#define ATOM_B2B_STKYSPAD_OFFSET 0x80c4 137 138#define ATOM_MODPHY_PCSREG4 0x1c004 139#define ATOM_MODPHY_PCSREG6 0x1c006 140 141#define ATOM_IP_BASE 0xc000 142#define ATOM_DESKEWSTS_OFFSET (ATOM_IP_BASE + 0x3024) 143#define ATOM_LTSSMERRSTS0_OFFSET (ATOM_IP_BASE + 0x3180) 144#define ATOM_LTSSMSTATEJMP_OFFSET (ATOM_IP_BASE + 0x3040) 145#define ATOM_IBSTERRRCRVSTS0_OFFSET (ATOM_IP_BASE + 0x3324) 146 147#define ATOM_DESKEWSTS_DBERR (1 << 15) 148#define ATOM_LTSSMERRSTS0_UNEXPECTEDEI (1 << 20) 149#define ATOM_LTSSMSTATEJMP_FORCEDETECT (1 << 2) 150#define ATOM_IBIST_ERR_OFLOW 0x7fff7fff 151 152#define NTB_CNTL_CFG_LOCK (1 << 0) 153#define NTB_CNTL_LINK_DISABLE (1 << 1) 154#define NTB_CNTL_S2P_BAR23_SNOOP (1 << 2) 155#define NTB_CNTL_P2S_BAR23_SNOOP (1 << 4) 156#define NTB_CNTL_S2P_BAR4_SNOOP (1 << 6) 157#define NTB_CNTL_P2S_BAR4_SNOOP (1 << 8) 158#define NTB_CNTL_S2P_BAR5_SNOOP (1 << 12) 159#define NTB_CNTL_P2S_BAR5_SNOOP (1 << 14) 160#define ATOM_CNTL_LINK_DOWN (1 << 16) 161 162#define XEON_PBAR23SZ_OFFSET 0x00d0 163#define XEON_PBAR45SZ_OFFSET 0x00d1 164#define XEON_PBAR4SZ_OFFSET 0x00d1 165#define XEON_PBAR5SZ_OFFSET 0x00d5 166#define XEON_SBAR23SZ_OFFSET 0x00d2 167#define XEON_SBAR4SZ_OFFSET 0x00d3 168#define XEON_SBAR5SZ_OFFSET 0x00d6 169#define NTB_PPD_OFFSET 0x00d4 170#define XEON_PPD_CONN_TYPE 0x0003 171#define XEON_PPD_DEV_TYPE 0x0010 172#define XEON_PPD_SPLIT_BAR 0x0040 173#define ATOM_PPD_INIT_LINK 0x0008 174#define ATOM_PPD_CONN_TYPE 0x0300 175#define ATOM_PPD_DEV_TYPE 0x1000 176 177/* All addresses are in low 32-bit space so 32-bit BARs can function */ 178#define XEON_B2B_BAR0_ADDR 0x1000000000000000ull 179#define XEON_B2B_BAR2_ADDR64 0x2000000000000000ull 180#define XEON_B2B_BAR4_ADDR64 0x4000000000000000ull 181#define XEON_B2B_BAR4_ADDR32 0x20000000ull 182#define XEON_B2B_BAR5_ADDR32 0x40000000ull 183 184/* The peer ntb secondary config space is 32KB fixed size */ 185#define XEON_B2B_MIN_SIZE 0x8000 186#define XEON_GEN3_MW_COUNT 2 187#define XEON_GEN3_SPLIT_MW_COUNT 3 188#define XEON_GEN3_SPAD_COUNT 16 189#define XEON_GEN3_DB_COUNT 32 190#define XEON_GEN3_DB_LINK 32 191#define XEON_GEN3_DB_LINK_BIT (1ULL << XEON_GEN3_DB_LINK) 192#define XEON_GEN3_DB_MSIX_VECTOR_COUNT 33 193#define XEON_GEN3_DB_MSIX_VECTOR_SHIFT 1 194 195#define XEON_GEN3_LINK_VECTOR_INDEX 31 196 197/* Xeon Skylake NTB register definitions */ 198 199/* 200 * Internal EndPoint Configuration Registers 201 */ 202#define XEON_GEN3_INT_REG_BAR0BASE 0x10 203#define XEON_GEN3_INT_REG_BAR1BASE 0x18 204#define XEON_GEN3_INT_REG_BAR2BASE 0x20 205#define XEON_GEN3_INT_REG_IMBAR1SZ 0xd0 206#define XEON_GEN3_INT_REG_IMBAR2SZ 0xd1 207#define XEON_GEN3_INT_REG_EMBAR1SZ 0xd2 208#define XEON_GEN3_INT_REG_EMBAR2SZ 0xd3 209#define XEON_GEN3_INT_REG_PPD 0xd4 210#define XEON_GEN3_INT_LNK_STS_OFFSET 0x01a2 211 212/* 213 * External EndPoint Configuration Registers 214 * These are located within BAR0 of the internal endpoint. 215 */ 216#define XEON_GEN3_EXT_REG_PCI_CMD 0x4504 217#define XEON_GEN3_EXT_REG_BAR0BASE 0x4510 218#define XEON_GEN3_EXT_REG_BAR1BASE 0x4518 219#define XEON_GEN3_EXT_REG_BAR2BASE 0x4520 220 221/* 222 * Internal Endpoint Memory Mapped Registers 223 */ 224#define XEON_GEN3_REG_IMNTB_CTRL 0x0000 225#define XEON_GEN3_REG_IMBAR1XBASE 0x0010 226#define XEON_GEN3_REG_IMBAR1XLIMIT 0x0018 227#define XEON_GEN3_REG_IMBAR2XBASE 0x0020 228#define XEON_GEN3_REG_IMBAR2XLIMIT 0x0028 229#define XEON_GEN3_REG_IMINT_STATUS 0x0040 230#define XEON_GEN3_REG_IMINT_DISABLE 0x0048 231#define XEON_GEN3_REG_IMSPAD 0x0080 232#define XEON_GEN3_REG_IMINTVEC00 0x00d0 233#define XEON_GEN3_REG_IMDOORBELL 0x0100 234#define XEON_GEN3_REG_IMB2B_SSPAD 0x0180 /* Pseudo SP registers */ 235 236/* 237 * External Endpoint Memory Mapped Registers 238 */ 239#define XEON_GEN3_REG_EMBAR0XBASE 0x4008 240#define XEON_GEN3_REG_EMBAR1XBASE 0x4010 241#define XEON_GEN3_REG_EMBAR1XLIMIT 0x4018 242#define XEON_GEN3_REG_EMBAR2XBASE 0x4020 243#define XEON_GEN3_REG_EMBAR2XLIMIT 0x4028 244#define XEON_GEN3_REG_EMINT_STATUS 0x4040 245#define XEON_GEN3_REG_EMINT_DISABLE 0x4048 246#define XEON_GEN3_REG_EMSPAD 0x4080 247#define XEON_GEN3_REG_EMDOORBELL 0x4100 248 249/* XEON_GEN3_INT_REG_PPD: PPD register */ 250#define XEON_GEN3_REG_PPD_PORT_DEF_F(X) M8_F(X, 0, 2) 251#define XEON_GEN3_REG_PPD_CONF_STS_F(X) M8_F(X, 4, 1) 252#define XEON_GEN3_REG_PPD_ONE_MSIX_F(X) M8_F(X, 5, 1) 253#define XEON_GEN3_REG_PPD_BAR45_SPL_F(X) M8_F(X, 6, 1) 254 255#endif /* _NTB_REGS_H_ */ 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