1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD$"); 31 32#include <sys/param.h> 33#include <sys/module.h> 34#include <sys/systm.h> 35#include <sys/kernel.h> 36#include <sys/bus.h> 37#include <sys/endian.h> 38#include <sys/malloc.h> 39#include <sys/lock.h> 40#include <sys/mutex.h> 41#include <vm/uma.h> 42#include <machine/stdarg.h> 43#include <machine/resource.h> 44#include <machine/bus.h> 45#include <sys/rman.h> 46#include <arm/mv/mvreg.h> 47#include <arm/mv/mvvar.h> 48#include <dev/ofw/ofw_bus.h> 49#include <dev/ofw/ofw_bus_subr.h> 50#include "mvs.h" 51 52/* local prototypes */ 53static int mvs_setup_interrupt(device_t dev); 54static void mvs_intr(void *data); 55static int mvs_suspend(device_t dev); 56static int mvs_resume(device_t dev); 57static int mvs_ctlr_setup(device_t dev); 58 59static struct { 60 uint32_t id; 61 uint8_t rev; 62 const char *name; 63 int ports; 64 int quirks; 65} mvs_ids[] = { 66 {MV_DEV_88F5182, 0x00, "Marvell 88F5182", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 67 {MV_DEV_88F6281, 0x00, "Marvell 88F6281", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 68 {MV_DEV_88F6282, 0x00, "Marvell 88F6282", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 69 {MV_DEV_MV78100, 0x00, "Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 70 {MV_DEV_MV78100_Z0, 0x00,"Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 71 {MV_DEV_MV78260, 0x00, "Marvell MV78260", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 72 {MV_DEV_MV78460, 0x00, "Marvell MV78460", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 73 {0, 0x00, NULL, 0, 0} 74}; 75 76static int 77mvs_probe(device_t dev) 78{ 79 char buf[64]; 80 int i; 81 uint32_t devid, revid; 82 83 if (!ofw_bus_status_okay(dev)) 84 return (ENXIO); 85 86 if (!ofw_bus_is_compatible(dev, "mrvl,sata")) 87 return (ENXIO); 88 89 soc_id(&devid, &revid); 90 for (i = 0; mvs_ids[i].id != 0; i++) { 91 if (mvs_ids[i].id == devid && 92 mvs_ids[i].rev <= revid) { 93 snprintf(buf, sizeof(buf), "%s SATA controller", 94 mvs_ids[i].name); 95 device_set_desc_copy(dev, buf); 96 return (BUS_PROBE_DEFAULT); 97 } 98 } 99 return (ENXIO); 100} 101 102static int 103mvs_attach(device_t dev) 104{ 105 struct mvs_controller *ctlr = device_get_softc(dev); 106 device_t child; 107 int error, unit, i; 108 uint32_t devid, revid; 109 110 soc_id(&devid, &revid); 111 ctlr->dev = dev; 112 i = 0; 113 while (mvs_ids[i].id != 0 && 114 (mvs_ids[i].id != devid || 115 mvs_ids[i].rev > revid)) 116 i++; 117 ctlr->channels = mvs_ids[i].ports; 118 ctlr->quirks = mvs_ids[i].quirks; 119 ctlr->ccc = 0; 120 resource_int_value(device_get_name(dev), 121 device_get_unit(dev), "ccc", &ctlr->ccc); 122 ctlr->cccc = 8; 123 resource_int_value(device_get_name(dev), 124 device_get_unit(dev), "cccc", &ctlr->cccc); 125 if (ctlr->ccc == 0 || ctlr->cccc == 0) { 126 ctlr->ccc = 0; 127 ctlr->cccc = 0; 128 } 129 if (ctlr->ccc > 100000) 130 ctlr->ccc = 100000; 131 device_printf(dev, 132 "Gen-%s, %d %sGbps ports, Port Multiplier %s%s\n", 133 ((ctlr->quirks & MVS_Q_GENI) ? "I" : 134 ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")), 135 ctlr->channels, 136 ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"), 137 ((ctlr->quirks & MVS_Q_GENI) ? 138 "not supported" : "supported"), 139 ((ctlr->quirks & MVS_Q_GENIIE) ? 140 " with FBS" : "")); 141 mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF); 142 /* We should have a memory BAR(0). */ 143 ctlr->r_rid = 0; 144 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 145 &ctlr->r_rid, RF_ACTIVE))) 146 return ENXIO; 147 if (ATA_INL(ctlr->r_mem, PORT_BASE(0) + SATA_PHYCFG_OFS) != 0) 148 ctlr->quirks |= MVS_Q_SOC65; 149 /* Setup our own memory management for channels. */ 150 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 151 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 152 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 153 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 154 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 155 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 156 return (error); 157 } 158 if ((error = rman_manage_region(&ctlr->sc_iomem, 159 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 160 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 161 rman_fini(&ctlr->sc_iomem); 162 return (error); 163 } 164 mvs_ctlr_setup(dev); 165 /* Setup interrupts. */ 166 if (mvs_setup_interrupt(dev)) { 167 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 168 rman_fini(&ctlr->sc_iomem); 169 return ENXIO; 170 } 171 /* Attach all channels on this controller */ 172 for (unit = 0; unit < ctlr->channels; unit++) { 173 child = device_add_child(dev, "mvsch", -1); 174 if (child == NULL) 175 device_printf(dev, "failed to add channel device\n"); 176 else 177 device_set_ivars(child, (void *)(intptr_t)unit); 178 } 179 bus_generic_attach(dev); 180 return 0; 181} 182 183static int 184mvs_detach(device_t dev) 185{ 186 struct mvs_controller *ctlr = device_get_softc(dev); 187 188 /* Detach & delete all children */ 189 device_delete_children(dev); 190 191 /* Free interrupt. */ 192 if (ctlr->irq.r_irq) { 193 bus_teardown_intr(dev, ctlr->irq.r_irq, 194 ctlr->irq.handle); 195 bus_release_resource(dev, SYS_RES_IRQ, 196 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 197 } 198 /* Free memory. */ 199 rman_fini(&ctlr->sc_iomem); 200 if (ctlr->r_mem) 201 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 202 mtx_destroy(&ctlr->mtx); 203 return (0); 204} 205 206static int 207mvs_ctlr_setup(device_t dev) 208{ 209 struct mvs_controller *ctlr = device_get_softc(dev); 210 int ccc = ctlr->ccc, cccc = ctlr->cccc, ccim = 0; 211 212 /* Mask chip interrupts */ 213 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 214 /* Clear HC interrupts */ 215 ATA_OUTL(ctlr->r_mem, HC_IC, 0x00000000); 216 /* Clear chip interrupts */ 217 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIC, 0); 218 /* Configure per-HC CCC */ 219 if (ccc && bootverbose) { 220 device_printf(dev, 221 "CCC with %dus/%dcmd enabled\n", 222 ctlr->ccc, ctlr->cccc); 223 } 224 ccc *= 150; 225 ATA_OUTL(ctlr->r_mem, HC_ICT, cccc); 226 ATA_OUTL(ctlr->r_mem, HC_ITT, ccc); 227 if (ccc) 228 ccim |= IC_HC0_COAL_DONE; 229 /* Enable chip interrupts */ 230 ctlr->gmim = ((ccc ? IC_HC0_COAL_DONE : 231 (IC_DONE_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels))) | 232 (IC_ERR_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels))); 233 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 234 return (0); 235} 236 237static void 238mvs_edma(device_t dev, device_t child, int mode) 239{ 240 struct mvs_controller *ctlr = device_get_softc(dev); 241 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 242 int bit = IC_DONE_IRQ << (unit * 2); 243 244 if (ctlr->ccc == 0) 245 return; 246 /* CCC is not working for non-EDMA mode. Unmask device interrupts. */ 247 mtx_lock(&ctlr->mtx); 248 if (mode == MVS_EDMA_OFF) 249 ctlr->pmim |= bit; 250 else 251 ctlr->pmim &= ~bit; 252 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 253 mtx_unlock(&ctlr->mtx); 254} 255 256static int 257mvs_suspend(device_t dev) 258{ 259 struct mvs_controller *ctlr = device_get_softc(dev); 260 261 bus_generic_suspend(dev); 262 /* Mask chip interrupts */ 263 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 264 return 0; 265} 266 267static int 268mvs_resume(device_t dev) 269{ 270 271 mvs_ctlr_setup(dev); 272 return (bus_generic_resume(dev)); 273} 274 275static int 276mvs_setup_interrupt(device_t dev) 277{ 278 struct mvs_controller *ctlr = device_get_softc(dev); 279 280 /* Allocate all IRQs. */ 281 ctlr->irq.r_irq_rid = 0; 282 if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 283 &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 284 device_printf(dev, "unable to map interrupt\n"); 285 return (ENXIO); 286 } 287 if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL, 288 mvs_intr, ctlr, &ctlr->irq.handle))) { 289 device_printf(dev, "unable to setup interrupt\n"); 290 bus_release_resource(dev, SYS_RES_IRQ, 291 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 292 ctlr->irq.r_irq = NULL; 293 return (ENXIO); 294 } 295 return (0); 296} 297 298/* 299 * Common case interrupt handler. 300 */ 301static void 302mvs_intr(void *data) 303{ 304 struct mvs_controller *ctlr = data; 305 struct mvs_intr_arg arg; 306 void (*function)(void *); 307 int p, chan_num; 308 u_int32_t ic, aic; 309 310 ic = ATA_INL(ctlr->r_mem, CHIP_SOC_MIC); 311 if ((ic & IC_HC0) == 0) 312 return; 313 314 /* Acknowledge interrupts of this HC. */ 315 aic = 0; 316 317 /* Processing interrupts from each initialized channel */ 318 for (chan_num = 0; chan_num < ctlr->channels; chan_num++) { 319 if (ic & (IC_DONE_IRQ << (chan_num * 2))) 320 aic |= HC_IC_DONE(chan_num) | HC_IC_DEV(chan_num); 321 } 322 323 if (ic & IC_HC0_COAL_DONE) 324 aic |= HC_IC_COAL; 325 ATA_OUTL(ctlr->r_mem, HC_IC, ~aic); 326 327 /* Call per-port interrupt handler. */ 328 for (p = 0; p < ctlr->channels; p++) { 329 arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ); 330 if ((arg.cause != 0) && 331 (function = ctlr->interrupt[p].function)) { 332 arg.arg = ctlr->interrupt[p].argument; 333 function(&arg); 334 } 335 ic >>= 2; 336 } 337} 338 339static struct resource * 340mvs_alloc_resource(device_t dev, device_t child, int type, int *rid, 341 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 342{ 343 struct mvs_controller *ctlr = device_get_softc(dev); 344 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 345 struct resource *res = NULL; 346 int offset = PORT_BASE(unit & 0x03); 347 rman_res_t st; 348 349 switch (type) { 350 case SYS_RES_MEMORY: 351 st = rman_get_start(ctlr->r_mem); 352 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 353 st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child); 354 if (res) { 355 bus_space_handle_t bsh; 356 bus_space_tag_t bst; 357 bsh = rman_get_bushandle(ctlr->r_mem); 358 bst = rman_get_bustag(ctlr->r_mem); 359 bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh); 360 rman_set_bushandle(res, bsh); 361 rman_set_bustag(res, bst); 362 } 363 break; 364 case SYS_RES_IRQ: 365 if (*rid == ATA_IRQ_RID) 366 res = ctlr->irq.r_irq; 367 break; 368 } 369 return (res); 370} 371 372static int 373mvs_release_resource(device_t dev, device_t child, int type, int rid, 374 struct resource *r) 375{ 376 377 switch (type) { 378 case SYS_RES_MEMORY: 379 rman_release_resource(r); 380 return (0); 381 case SYS_RES_IRQ: 382 if (rid != ATA_IRQ_RID) 383 return ENOENT; 384 return (0); 385 } 386 return (EINVAL); 387} 388 389static int 390mvs_setup_intr(device_t dev, device_t child, struct resource *irq, 391 int flags, driver_filter_t *filter, driver_intr_t *function, 392 void *argument, void **cookiep) 393{ 394 struct mvs_controller *ctlr = device_get_softc(dev); 395 int unit = (intptr_t)device_get_ivars(child); 396 397 if (filter != NULL) { 398 printf("mvs.c: we cannot use a filter here\n"); 399 return (EINVAL); 400 } 401 ctlr->interrupt[unit].function = function; 402 ctlr->interrupt[unit].argument = argument; 403 return (0); 404} 405 406static int 407mvs_teardown_intr(device_t dev, device_t child, struct resource *irq, 408 void *cookie) 409{ 410 struct mvs_controller *ctlr = device_get_softc(dev); 411 int unit = (intptr_t)device_get_ivars(child); 412 413 ctlr->interrupt[unit].function = NULL; 414 ctlr->interrupt[unit].argument = NULL; 415 return (0); 416} 417 418static int 419mvs_print_child(device_t dev, device_t child) 420{ 421 int retval; 422 423 retval = bus_print_child_header(dev, child); 424 retval += printf(" at channel %d", 425 (int)(intptr_t)device_get_ivars(child)); 426 retval += bus_print_child_footer(dev, child); 427 428 return (retval); 429} 430 431static int 432mvs_child_location_str(device_t dev, device_t child, char *buf, 433 size_t buflen) 434{ 435 436 snprintf(buf, buflen, "channel=%d", 437 (int)(intptr_t)device_get_ivars(child)); 438 return (0); 439} 440 441static bus_dma_tag_t 442mvs_get_dma_tag(device_t bus, device_t child) 443{ 444 445 return (bus_get_dma_tag(bus)); 446} 447 448static device_method_t mvs_methods[] = { 449 DEVMETHOD(device_probe, mvs_probe), 450 DEVMETHOD(device_attach, mvs_attach), 451 DEVMETHOD(device_detach, mvs_detach), 452 DEVMETHOD(device_suspend, mvs_suspend), 453 DEVMETHOD(device_resume, mvs_resume), 454 DEVMETHOD(bus_print_child, mvs_print_child), 455 DEVMETHOD(bus_alloc_resource, mvs_alloc_resource), 456 DEVMETHOD(bus_release_resource, mvs_release_resource), 457 DEVMETHOD(bus_setup_intr, mvs_setup_intr), 458 DEVMETHOD(bus_teardown_intr,mvs_teardown_intr), 459 DEVMETHOD(bus_child_location_str, mvs_child_location_str), 460 DEVMETHOD(bus_get_dma_tag, mvs_get_dma_tag), 461 DEVMETHOD(mvs_edma, mvs_edma), 462 { 0, 0 } 463}; 464static driver_t mvs_driver = { 465 "mvs", 466 mvs_methods, 467 sizeof(struct mvs_controller) 468}; 469DRIVER_MODULE(mvs, simplebus, mvs_driver, mvs_devclass, 0, 0); 470MODULE_VERSION(mvs, 1); 471MODULE_DEPEND(mvs, cam, 1, 1, 1); 472