1/*- 2 * Copyright (c) 2009 Yahoo! Inc. 3 * Copyright (c) 2011-2015 LSI Corp. 4 * Copyright (c) 2013-2016 Avago Technologies 5 * Copyright 2000-2020 Broadcom Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD 30 * 31 * $FreeBSD$ 32 */ 33 34#ifndef _MPRVAR_H 35#define _MPRVAR_H 36 37#define MPR_DRIVER_VERSION "23.00.00.00-fbsd" 38 39#define MPR_DB_MAX_WAIT 2500 40 41#define MPR_REQ_FRAMES 2048 42#define MPR_PRI_REQ_FRAMES 128 43#define MPR_EVT_REPLY_FRAMES 32 44#define MPR_REPLY_FRAMES MPR_REQ_FRAMES 45#define MPR_CHAIN_FRAMES 16384 46#define MPR_MAXIO_PAGES (-1) 47#define MPR_SENSE_LEN SSD_FULL_SIZE 48#define MPR_MSI_MAX 1 49#define MPR_MSIX_MAX 96 50#define MPR_SGE64_SIZE 12 51#define MPR_SGE32_SIZE 8 52#define MPR_SGC_SIZE 8 53#define MPR_DEFAULT_CHAIN_SEG_SIZE 8 54#define MPR_MAX_CHAIN_ELEMENT_SIZE 16 55 56/* 57 * PCIe NVMe Specific defines 58 */ 59//SLM-for now just use the same value as a SAS disk 60#define NVME_QDEPTH MPR_REQ_FRAMES 61#define PRP_ENTRY_SIZE 8 62#define NVME_CMD_PRP1_OFFSET 24 /* PRP1 offset in NVMe cmd */ 63#define NVME_CMD_PRP2_OFFSET 32 /* PRP2 offset in NVMe cmd */ 64#define NVME_ERROR_RESPONSE_SIZE 16 /* Max NVME Error Response */ 65#define HOST_PAGE_SIZE_4K 12 66 67#define MPR_FUNCTRACE(sc) \ 68 mpr_dprint((sc), MPR_TRACE, "%s\n", __func__) 69 70#define CAN_SLEEP 1 71#define NO_SLEEP 0 72 73#define MPR_PERIODIC_DELAY 1 /* 1 second heartbeat/watchdog check */ 74#define MPR_ATA_ID_TIMEOUT 5 /* 5 second timeout for SATA ID cmd */ 75#define MPR_MISSING_CHECK_DELAY 10 /* 10 seconds between missing check */ 76 77#define IFAULT_IOP_OVER_TEMP_THRESHOLD_EXCEEDED 0x2810 78 79#define MPR_SCSI_RI_INVALID_FRAME (0x00000002) 80 81#define DEFAULT_SPINUP_WAIT 3 /* seconds to wait for spinup */ 82 83#include <sys/endian.h> 84 85/* 86 * host mapping related macro definitions 87 */ 88#define MPR_MAPTABLE_BAD_IDX 0xFFFFFFFF 89#define MPR_DPM_BAD_IDX 0xFFFF 90#define MPR_ENCTABLE_BAD_IDX 0xFF 91#define MPR_MAX_MISSING_COUNT 0x0F 92#define MPR_DEV_RESERVED 0x20000000 93#define MPR_MAP_IN_USE 0x10000000 94#define MPR_MAP_BAD_ID 0xFFFFFFFF 95 96typedef uint8_t u8; 97typedef uint16_t u16; 98typedef uint32_t u32; 99typedef uint64_t u64; 100 101typedef struct _MPI2_CONFIG_PAGE_MAN_11 102{ 103 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 104 U8 FlashTime; /* 0x04 */ 105 U8 NVTime; /* 0x05 */ 106 U16 Flag; /* 0x06 */ 107 U8 RFIoTimeout; /* 0x08 */ 108 U8 EEDPTagMode; /* 0x09 */ 109 U8 AWTValue; /* 0x0A */ 110 U8 Reserve1; /* 0x0B */ 111 U8 MaxCmdFrames; /* 0x0C */ 112 U8 Reserve2; /* 0x0D */ 113 U16 AddlFlags; /* 0x0E */ 114 U32 SysRefClk; /* 0x10 */ 115 U64 Reserve3[3]; /* 0x14 */ 116 U16 AddlFlags2; /* 0x2C */ 117 U8 AddlFlags3; /* 0x2E */ 118 U8 Reserve4; /* 0x2F */ 119 U64 opDebugEnable; /* 0x30 */ 120 U64 PlDebugEnable; /* 0x38 */ 121 U64 IrDebugEnable; /* 0x40 */ 122 U32 BoardPowerRequirement; /* 0x48 */ 123 U8 NVMeAbortTO; /* 0x4C */ 124 U8 Reserve5; /* 0x4D */ 125 U16 Reserve6; /* 0x4E */ 126 U32 Reserve7[3]; /* 0x50 */ 127} MPI2_CONFIG_PAGE_MAN_11, 128 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_11, 129 Mpi2ManufacturingPage11_t, MPI2_POINTER pMpi2ManufacturingPage11_t; 130 131#define MPI2_MAN_PG11_ADDLFLAGS2_CUSTOM_TM_HANDLING_MASK (0x0010) 132 133/** 134 * struct dev_mapping_table - device mapping information 135 * @physical_id: SAS address for drives or WWID for RAID volumes 136 * @device_info: bitfield provides detailed info about the device 137 * @phy_bits: bitfields indicating controller phys 138 * @dpm_entry_num: index of this device in device persistent map table 139 * @dev_handle: device handle for the device pointed by this entry 140 * @id: target id 141 * @missing_count: number of times the device not detected by driver 142 * @hide_flag: Hide this physical disk/not (foreign configuration) 143 * @init_complete: Whether the start of the day checks completed or not 144 * @TLR_bits: Turn TLR support on or off 145 */ 146struct dev_mapping_table { 147 u64 physical_id; 148 u32 device_info; 149 u32 phy_bits; 150 u16 dpm_entry_num; 151 u16 dev_handle; 152 u16 reserved1; 153 u16 id; 154 u8 missing_count; 155 u8 init_complete; 156 u8 TLR_bits; 157 u8 reserved2; 158}; 159 160/** 161 * struct enc_mapping_table - mapping information about an enclosure 162 * @enclosure_id: Logical ID of this enclosure 163 * @start_index: index to the entry in dev_mapping_table 164 * @phy_bits: bitfields indicating controller phys 165 * @dpm_entry_num: index of this enclosure in device persistent map table 166 * @enc_handle: device handle for the enclosure pointed by this entry 167 * @num_slots: number of slots in the enclosure 168 * @start_slot: Starting slot id 169 * @missing_count: number of times the device not detected by driver 170 * @removal_flag: used to mark the device for removal 171 * @skip_search: used as a flag to include/exclude enclosure for search 172 * @init_complete: Whether the start of the day checks completed or not 173 */ 174struct enc_mapping_table { 175 u64 enclosure_id; 176 u32 start_index; 177 u32 phy_bits; 178 u16 dpm_entry_num; 179 u16 enc_handle; 180 u16 num_slots; 181 u16 start_slot; 182 u8 missing_count; 183 u8 removal_flag; 184 u8 skip_search; 185 u8 init_complete; 186}; 187 188/** 189 * struct map_removal_table - entries to be removed from mapping table 190 * @dpm_entry_num: index of this device in device persistent map table 191 * @dev_handle: device handle for the device pointed by this entry 192 */ 193struct map_removal_table{ 194 u16 dpm_entry_num; 195 u16 dev_handle; 196}; 197 198typedef struct mpr_fw_diagnostic_buffer { 199 size_t size; 200 uint8_t extended_type; 201 uint8_t buffer_type; 202 uint8_t force_release; 203 uint32_t product_specific[23]; 204 uint8_t immediate; 205 uint8_t enabled; 206 uint8_t valid_data; 207 uint8_t owned_by_firmware; 208 uint32_t unique_id; 209} mpr_fw_diagnostic_buffer_t; 210 211struct mpr_softc; 212struct mpr_command; 213struct mprsas_softc; 214union ccb; 215struct mprsas_target; 216struct mpr_column_map; 217 218MALLOC_DECLARE(M_MPR); 219 220typedef void mpr_evt_callback_t(struct mpr_softc *, uintptr_t, 221 MPI2_EVENT_NOTIFICATION_REPLY *reply); 222typedef void mpr_command_callback_t(struct mpr_softc *, struct mpr_command *cm); 223 224struct mpr_chain { 225 TAILQ_ENTRY(mpr_chain) chain_link; 226 void *chain; 227 uint64_t chain_busaddr; 228}; 229 230struct mpr_prp_page { 231 TAILQ_ENTRY(mpr_prp_page) prp_page_link; 232 uint64_t *prp_page; 233 uint64_t prp_page_busaddr; 234}; 235 236/* 237 * This needs to be at least 2 to support SMP passthrough. 238 */ 239#define MPR_IOVEC_COUNT 2 240 241struct mpr_command { 242 TAILQ_ENTRY(mpr_command) cm_link; 243 TAILQ_ENTRY(mpr_command) cm_recovery; 244 struct mpr_softc *cm_sc; 245 union ccb *cm_ccb; 246 void *cm_data; 247 u_int cm_length; 248 u_int cm_out_len; 249 struct uio cm_uio; 250 struct iovec cm_iovec[MPR_IOVEC_COUNT]; 251 u_int cm_max_segs; 252 u_int cm_sglsize; 253 void *cm_sge; 254 uint8_t *cm_req; 255 uint8_t *cm_reply; 256 uint32_t cm_reply_data; 257 mpr_command_callback_t *cm_complete; 258 void *cm_complete_data; 259 struct mprsas_target *cm_targ; 260 MPI2_REQUEST_DESCRIPTOR_UNION cm_desc; 261 u_int cm_lun; 262 u_int cm_flags; 263#define MPR_CM_FLAGS_POLLED (1 << 0) 264#define MPR_CM_FLAGS_COMPLETE (1 << 1) 265#define MPR_CM_FLAGS_SGE_SIMPLE (1 << 2) 266#define MPR_CM_FLAGS_DATAOUT (1 << 3) 267#define MPR_CM_FLAGS_DATAIN (1 << 4) 268#define MPR_CM_FLAGS_WAKEUP (1 << 5) 269#define MPR_CM_FLAGS_USE_UIO (1 << 6) 270#define MPR_CM_FLAGS_SMP_PASS (1 << 7) 271#define MPR_CM_FLAGS_CHAIN_FAILED (1 << 8) 272#define MPR_CM_FLAGS_ERROR_MASK MPR_CM_FLAGS_CHAIN_FAILED 273#define MPR_CM_FLAGS_USE_CCB (1 << 9) 274#define MPR_CM_FLAGS_SATA_ID_TIMEOUT (1 << 10) 275#define MPR_CM_FLAGS_ON_RECOVERY (1 << 12) 276#define MPR_CM_FLAGS_TIMEDOUT (1 << 13) 277 u_int cm_state; 278#define MPR_CM_STATE_FREE 0 279#define MPR_CM_STATE_BUSY 1 280#define MPR_CM_STATE_INQUEUE 2 281 bus_dmamap_t cm_dmamap; 282 struct scsi_sense_data *cm_sense; 283 uint64_t *nvme_error_response; 284 TAILQ_HEAD(, mpr_chain) cm_chain_list; 285 TAILQ_HEAD(, mpr_prp_page) cm_prp_page_list; 286 uint32_t cm_req_busaddr; 287 bus_addr_t cm_sense_busaddr; 288 struct callout cm_callout; 289 mpr_command_callback_t *cm_timeout_handler; 290}; 291 292struct mpr_column_map { 293 uint16_t dev_handle; 294 uint8_t phys_disk_num; 295}; 296 297struct mpr_event_handle { 298 TAILQ_ENTRY(mpr_event_handle) eh_list; 299 mpr_evt_callback_t *callback; 300 void *data; 301 uint8_t mask[16]; 302}; 303 304struct mpr_busdma_context { 305 int completed; 306 int abandoned; 307 int error; 308 bus_addr_t *addr; 309 struct mpr_softc *softc; 310 bus_dmamap_t buffer_dmamap; 311 bus_dma_tag_t buffer_dmat; 312}; 313 314struct mpr_queue { 315 struct mpr_softc *sc; 316 int qnum; 317 MPI2_REPLY_DESCRIPTORS_UNION *post_queue; 318 int replypostindex; 319#ifdef notyet 320 ck_ring_buffer_t *ringmem; 321 ck_ring_buffer_t *chainmem; 322 ck_ring_t req_ring; 323 ck_ring_t chain_ring; 324#endif 325 bus_dma_tag_t buffer_dmat; 326 int io_cmds_highwater; 327 int chain_free_lowwater; 328 int chain_alloc_fail; 329 struct resource *irq; 330 void *intrhand; 331 int irq_rid; 332}; 333 334struct mpr_softc { 335 device_t mpr_dev; 336 struct cdev *mpr_cdev; 337 u_int mpr_flags; 338#define MPR_FLAGS_INTX (1 << 0) 339#define MPR_FLAGS_MSI (1 << 1) 340#define MPR_FLAGS_BUSY (1 << 2) 341#define MPR_FLAGS_SHUTDOWN (1 << 3) 342#define MPR_FLAGS_DIAGRESET (1 << 4) 343#define MPR_FLAGS_ATTACH_DONE (1 << 5) 344#define MPR_FLAGS_GEN35_IOC (1 << 6) 345#define MPR_FLAGS_REALLOCATED (1 << 7) 346#define MPR_FLAGS_SEA_IOC (1 << 8) 347 u_int mpr_debug; 348 int msi_msgs; 349 u_int reqframesz; 350 u_int replyframesz; 351 u_int atomic_desc_capable; 352 int tm_cmds_active; 353 int io_cmds_active; 354 int io_cmds_highwater; 355 int chain_free; 356 int max_chains; 357 int max_io_pages; 358 u_int maxio; 359 int chain_free_lowwater; 360 uint32_t chain_frame_size; 361 int prp_buffer_size; 362 int prp_pages_free; 363 int prp_pages_free_lowwater; 364 u_int enable_ssu; 365 int spinup_wait_time; 366 int use_phynum; 367 uint64_t chain_alloc_fail; 368 uint64_t prp_page_alloc_fail; 369 struct sysctl_ctx_list sysctl_ctx; 370 struct sysctl_oid *sysctl_tree; 371 char fw_version[16]; 372 struct mpr_command *commands; 373 struct mpr_chain *chains; 374 struct mpr_prp_page *prps; 375 struct callout periodic; 376 struct callout device_check_callout; 377 struct mpr_queue *queues; 378 379 struct mprsas_softc *sassc; 380 TAILQ_HEAD(, mpr_command) req_list; 381 TAILQ_HEAD(, mpr_command) high_priority_req_list; 382 TAILQ_HEAD(, mpr_chain) chain_list; 383 TAILQ_HEAD(, mpr_prp_page) prp_page_list; 384 TAILQ_HEAD(, mpr_command) tm_list; 385 int replypostindex; 386 int replyfreeindex; 387 388 struct resource *mpr_regs_resource; 389 bus_space_handle_t mpr_bhandle; 390 bus_space_tag_t mpr_btag; 391 int mpr_regs_rid; 392 393 bus_dma_tag_t mpr_parent_dmat; 394 bus_dma_tag_t buffer_dmat; 395 396 MPI2_IOC_FACTS_REPLY *facts; 397 int num_reqs; 398 int num_prireqs; 399 int num_replies; 400 int num_chains; 401 int fqdepth; /* Free queue */ 402 int pqdepth; /* Post queue */ 403 404 uint8_t event_mask[16]; 405 TAILQ_HEAD(, mpr_event_handle) event_list; 406 struct mpr_event_handle *mpr_log_eh; 407 408 struct mtx mpr_mtx; 409 struct intr_config_hook mpr_ich; 410 411 uint8_t *req_frames; 412 bus_addr_t req_busaddr; 413 bus_dma_tag_t req_dmat; 414 bus_dmamap_t req_map; 415 416 uint8_t *reply_frames; 417 bus_addr_t reply_busaddr; 418 bus_dma_tag_t reply_dmat; 419 bus_dmamap_t reply_map; 420 421 struct scsi_sense_data *sense_frames; 422 bus_addr_t sense_busaddr; 423 bus_dma_tag_t sense_dmat; 424 bus_dmamap_t sense_map; 425 426 uint8_t *chain_frames; 427 bus_dma_tag_t chain_dmat; 428 bus_dmamap_t chain_map; 429 430 uint8_t *prp_pages; 431 bus_addr_t prp_page_busaddr; 432 bus_dma_tag_t prp_page_dmat; 433 bus_dmamap_t prp_page_map; 434 435 MPI2_REPLY_DESCRIPTORS_UNION *post_queue; 436 bus_addr_t post_busaddr; 437 uint32_t *free_queue; 438 bus_addr_t free_busaddr; 439 bus_dma_tag_t queues_dmat; 440 bus_dmamap_t queues_map; 441 442 uint8_t *fw_diag_buffer; 443 bus_addr_t fw_diag_busaddr; 444 bus_dma_tag_t fw_diag_dmat; 445 bus_dmamap_t fw_diag_map; 446 447 uint8_t ir_firmware; 448 449 /* static config pages */ 450 Mpi2IOCPage8_t ioc_pg8; 451 Mpi2IOUnitPage8_t iounit_pg8; 452 453 /* host mapping support */ 454 struct dev_mapping_table *mapping_table; 455 struct enc_mapping_table *enclosure_table; 456 struct map_removal_table *removal_table; 457 uint8_t *dpm_entry_used; 458 uint8_t *dpm_flush_entry; 459 Mpi2DriverMappingPage0_t *dpm_pg0; 460 uint16_t max_devices; 461 uint16_t max_enclosures; 462 uint16_t max_expanders; 463 uint8_t max_volumes; 464 uint8_t num_enc_table_entries; 465 uint8_t num_rsvd_entries; 466 uint16_t max_dpm_entries; 467 uint8_t is_dpm_enable; 468 uint8_t track_mapping_events; 469 uint32_t pending_map_events; 470 471 /* FW diag Buffer List */ 472 mpr_fw_diagnostic_buffer_t 473 fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT]; 474 475 /* Event Recording IOCTL support */ 476 uint32_t events_to_record[4]; 477 mpr_event_entry_t recorded_events[MPR_EVENT_QUEUE_SIZE]; 478 uint8_t event_index; 479 uint32_t event_number; 480 481 /* EEDP and TLR support */ 482 uint8_t eedp_enabled; 483 uint8_t control_TLR; 484 485 /* Shutdown Event Handler */ 486 eventhandler_tag shutdown_eh; 487 488 /* To track topo events during reset */ 489#define MPR_DIAG_RESET_TIMEOUT 300000 490 uint8_t wait_for_port_enable; 491 uint8_t port_enable_complete; 492 uint8_t msleep_fake_chan; 493 494 /* StartStopUnit command handling at shutdown */ 495 uint32_t SSU_refcount; 496 uint8_t SSU_started; 497 498 /* Configuration tunables */ 499 u_int disable_msix; 500 u_int disable_msi; 501 u_int max_msix; 502 u_int max_reqframes; 503 u_int max_prireqframes; 504 u_int max_replyframes; 505 u_int max_evtframes; 506 char exclude_ids[80]; 507 508 struct timeval lastfail; 509 uint8_t custom_nvme_tm_handling; 510 uint8_t nvme_abort_timeout; 511}; 512 513struct mpr_config_params { 514 MPI2_CONFIG_EXT_PAGE_HEADER_UNION hdr; 515 u_int action; 516 u_int page_address; /* Attributes, not a phys address */ 517 u_int status; 518 void *buffer; 519 u_int length; 520 int timeout; 521 void (*callback)(struct mpr_softc *, struct mpr_config_params *); 522 void *cbdata; 523}; 524 525struct scsi_read_capacity_eedp 526{ 527 uint8_t addr[8]; 528 uint8_t length[4]; 529 uint8_t protect; 530}; 531 532static __inline uint32_t 533mpr_regread(struct mpr_softc *sc, uint32_t offset) 534{ 535 uint32_t ret_val, i = 0; 536 do { 537 ret_val = 538 bus_space_read_4(sc->mpr_btag, sc->mpr_bhandle, offset); 539 } while((sc->mpr_flags & MPR_FLAGS_SEA_IOC) && 540 (ret_val == 0) && (++i < 3)); 541 542 return ret_val; 543} 544 545static __inline void 546mpr_regwrite(struct mpr_softc *sc, uint32_t offset, uint32_t val) 547{ 548 bus_space_write_4(sc->mpr_btag, sc->mpr_bhandle, offset, val); 549} 550 551/* free_queue must have Little Endian address 552 * TODO- cm_reply_data is unwanted. We can remove it. 553 * */ 554static __inline void 555mpr_free_reply(struct mpr_softc *sc, uint32_t busaddr) 556{ 557 if (++sc->replyfreeindex >= sc->fqdepth) 558 sc->replyfreeindex = 0; 559 sc->free_queue[sc->replyfreeindex] = htole32(busaddr); 560 mpr_regwrite(sc, MPI2_REPLY_FREE_HOST_INDEX_OFFSET, sc->replyfreeindex); 561} 562 563static __inline struct mpr_chain * 564mpr_alloc_chain(struct mpr_softc *sc) 565{ 566 struct mpr_chain *chain; 567 568 if ((chain = TAILQ_FIRST(&sc->chain_list)) != NULL) { 569 TAILQ_REMOVE(&sc->chain_list, chain, chain_link); 570 sc->chain_free--; 571 if (sc->chain_free < sc->chain_free_lowwater) 572 sc->chain_free_lowwater = sc->chain_free; 573 } else 574 sc->chain_alloc_fail++; 575 return (chain); 576} 577 578static __inline void 579mpr_free_chain(struct mpr_softc *sc, struct mpr_chain *chain) 580{ 581#if 0 582 bzero(chain->chain, 128); 583#endif 584 sc->chain_free++; 585 TAILQ_INSERT_TAIL(&sc->chain_list, chain, chain_link); 586} 587 588static __inline struct mpr_prp_page * 589mpr_alloc_prp_page(struct mpr_softc *sc) 590{ 591 struct mpr_prp_page *prp_page; 592 593 if ((prp_page = TAILQ_FIRST(&sc->prp_page_list)) != NULL) { 594 TAILQ_REMOVE(&sc->prp_page_list, prp_page, prp_page_link); 595 sc->prp_pages_free--; 596 if (sc->prp_pages_free < sc->prp_pages_free_lowwater) 597 sc->prp_pages_free_lowwater = sc->prp_pages_free; 598 } else 599 sc->prp_page_alloc_fail++; 600 return (prp_page); 601} 602 603static __inline void 604mpr_free_prp_page(struct mpr_softc *sc, struct mpr_prp_page *prp_page) 605{ 606 sc->prp_pages_free++; 607 TAILQ_INSERT_TAIL(&sc->prp_page_list, prp_page, prp_page_link); 608} 609 610static __inline void 611mpr_free_command(struct mpr_softc *sc, struct mpr_command *cm) 612{ 613 struct mpr_chain *chain, *chain_temp; 614 struct mpr_prp_page *prp_page, *prp_page_temp; 615 616 KASSERT(cm->cm_state == MPR_CM_STATE_BUSY, ("state not busy\n")); 617 618 if (cm->cm_reply != NULL) 619 mpr_free_reply(sc, cm->cm_reply_data); 620 cm->cm_reply = NULL; 621 cm->cm_flags = 0; 622 cm->cm_complete = NULL; 623 cm->cm_complete_data = NULL; 624 cm->cm_ccb = NULL; 625 cm->cm_targ = NULL; 626 cm->cm_max_segs = 0; 627 cm->cm_lun = 0; 628 cm->cm_state = MPR_CM_STATE_FREE; 629 cm->cm_data = NULL; 630 cm->cm_length = 0; 631 cm->cm_out_len = 0; 632 cm->cm_sglsize = 0; 633 cm->cm_sge = NULL; 634 635 TAILQ_FOREACH_SAFE(chain, &cm->cm_chain_list, chain_link, chain_temp) { 636 TAILQ_REMOVE(&cm->cm_chain_list, chain, chain_link); 637 mpr_free_chain(sc, chain); 638 } 639 TAILQ_FOREACH_SAFE(prp_page, &cm->cm_prp_page_list, prp_page_link, 640 prp_page_temp) { 641 TAILQ_REMOVE(&cm->cm_prp_page_list, prp_page, prp_page_link); 642 mpr_free_prp_page(sc, prp_page); 643 } 644 TAILQ_INSERT_TAIL(&sc->req_list, cm, cm_link); 645} 646 647static __inline struct mpr_command * 648mpr_alloc_command(struct mpr_softc *sc) 649{ 650 struct mpr_command *cm; 651 652 cm = TAILQ_FIRST(&sc->req_list); 653 if (cm == NULL) 654 return (NULL); 655 656 KASSERT(cm->cm_state == MPR_CM_STATE_FREE, 657 ("mpr: Allocating busy command\n")); 658 659 TAILQ_REMOVE(&sc->req_list, cm, cm_link); 660 cm->cm_state = MPR_CM_STATE_BUSY; 661 cm->cm_timeout_handler = NULL; 662 return (cm); 663} 664 665static __inline void 666mpr_free_high_priority_command(struct mpr_softc *sc, struct mpr_command *cm) 667{ 668 struct mpr_chain *chain, *chain_temp; 669 670 KASSERT(cm->cm_state == MPR_CM_STATE_BUSY, ("state not busy\n")); 671 672 if (cm->cm_reply != NULL) 673 mpr_free_reply(sc, cm->cm_reply_data); 674 cm->cm_reply = NULL; 675 cm->cm_flags = 0; 676 cm->cm_complete = NULL; 677 cm->cm_complete_data = NULL; 678 cm->cm_ccb = NULL; 679 cm->cm_targ = NULL; 680 cm->cm_lun = 0; 681 cm->cm_state = MPR_CM_STATE_FREE; 682 TAILQ_FOREACH_SAFE(chain, &cm->cm_chain_list, chain_link, chain_temp) { 683 TAILQ_REMOVE(&cm->cm_chain_list, chain, chain_link); 684 mpr_free_chain(sc, chain); 685 } 686 TAILQ_INSERT_TAIL(&sc->high_priority_req_list, cm, cm_link); 687} 688 689static __inline struct mpr_command * 690mpr_alloc_high_priority_command(struct mpr_softc *sc) 691{ 692 struct mpr_command *cm; 693 694 cm = TAILQ_FIRST(&sc->high_priority_req_list); 695 if (cm == NULL) 696 return (NULL); 697 698 KASSERT(cm->cm_state == MPR_CM_STATE_FREE, 699 ("mpr: Allocating busy command\n")); 700 701 TAILQ_REMOVE(&sc->high_priority_req_list, cm, cm_link); 702 cm->cm_state = MPR_CM_STATE_BUSY; 703 cm->cm_timeout_handler = NULL; 704 cm->cm_desc.HighPriority.RequestFlags = 705 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY; 706 return (cm); 707} 708 709static __inline void 710mpr_lock(struct mpr_softc *sc) 711{ 712 mtx_lock(&sc->mpr_mtx); 713} 714 715static __inline void 716mpr_unlock(struct mpr_softc *sc) 717{ 718 mtx_unlock(&sc->mpr_mtx); 719} 720 721#define MPR_INFO (1 << 0) /* Basic info */ 722#define MPR_FAULT (1 << 1) /* Hardware faults */ 723#define MPR_EVENT (1 << 2) /* Event data from the controller */ 724#define MPR_LOG (1 << 3) /* Log data from the controller */ 725#define MPR_RECOVERY (1 << 4) /* Command error recovery tracing */ 726#define MPR_ERROR (1 << 5) /* Parameter errors, programming bugs */ 727#define MPR_INIT (1 << 6) /* Things related to system init */ 728#define MPR_XINFO (1 << 7) /* More detailed/noisy info */ 729#define MPR_USER (1 << 8) /* Trace user-generated commands */ 730#define MPR_MAPPING (1 << 9) /* Trace device mappings */ 731#define MPR_TRACE (1 << 10) /* Function-by-function trace */ 732 733#define MPR_SSU_DISABLE_SSD_DISABLE_HDD 0 734#define MPR_SSU_ENABLE_SSD_DISABLE_HDD 1 735#define MPR_SSU_DISABLE_SSD_ENABLE_HDD 2 736#define MPR_SSU_ENABLE_SSD_ENABLE_HDD 3 737 738#define mpr_printf(sc, args...) \ 739 device_printf((sc)->mpr_dev, ##args) 740 741#define mpr_print_field(sc, msg, args...) \ 742 printf("\t" msg, ##args) 743 744#define mpr_vprintf(sc, args...) \ 745do { \ 746 if (bootverbose) \ 747 mpr_printf(sc, ##args); \ 748} while (0) 749 750#define mpr_dprint(sc, level, msg, args...) \ 751do { \ 752 if ((sc)->mpr_debug & (level)) \ 753 device_printf((sc)->mpr_dev, msg, ##args); \ 754} while (0) 755 756#define MPR_PRINTFIELD_START(sc, tag...) \ 757 mpr_printf((sc), ##tag); \ 758 mpr_print_field((sc), ":\n") 759#define MPR_PRINTFIELD_END(sc, tag) \ 760 mpr_printf((sc), tag "\n") 761#define MPR_PRINTFIELD(sc, facts, attr, fmt) \ 762 mpr_print_field((sc), #attr ": " #fmt "\n", (facts)->attr) 763 764static __inline void 765mpr_from_u64(uint64_t data, U64 *mpr) 766{ 767 (mpr)->High = htole32((uint32_t)((data) >> 32)); 768 (mpr)->Low = htole32((uint32_t)((data) & 0xffffffff)); 769} 770 771static __inline uint64_t 772mpr_to_u64(U64 *data) 773{ 774 return (((uint64_t)le32toh(data->High) << 32) | le32toh(data->Low)); 775} 776 777static __inline void 778mpr_mask_intr(struct mpr_softc *sc) 779{ 780 uint32_t mask; 781 782 mask = mpr_regread(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET); 783 mask |= MPI2_HIM_REPLY_INT_MASK; 784 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET, mask); 785} 786 787static __inline void 788mpr_unmask_intr(struct mpr_softc *sc) 789{ 790 uint32_t mask; 791 792 mask = mpr_regread(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET); 793 mask &= ~MPI2_HIM_REPLY_INT_MASK; 794 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET, mask); 795} 796 797int mpr_pci_setup_interrupts(struct mpr_softc *sc); 798void mpr_pci_free_interrupts(struct mpr_softc *sc); 799int mpr_pci_restore(struct mpr_softc *sc); 800 801void mpr_get_tunables(struct mpr_softc *sc); 802int mpr_attach(struct mpr_softc *sc); 803int mpr_free(struct mpr_softc *sc); 804void mpr_intr(void *); 805void mpr_intr_msi(void *); 806void mpr_intr_locked(void *); 807int mpr_register_events(struct mpr_softc *, uint8_t *, mpr_evt_callback_t *, 808 void *, struct mpr_event_handle **); 809int mpr_restart(struct mpr_softc *); 810int mpr_update_events(struct mpr_softc *, struct mpr_event_handle *, uint8_t *); 811int mpr_deregister_events(struct mpr_softc *, struct mpr_event_handle *); 812void mpr_build_nvme_prp(struct mpr_softc *sc, struct mpr_command *cm, 813 Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request, void *data, 814 uint32_t data_in_sz, uint32_t data_out_sz); 815int mpr_push_sge(struct mpr_command *, MPI2_SGE_SIMPLE64 *, size_t, int); 816int mpr_push_ieee_sge(struct mpr_command *, void *, int); 817int mpr_add_dmaseg(struct mpr_command *, vm_paddr_t, size_t, u_int, int); 818int mpr_attach_sas(struct mpr_softc *sc); 819int mpr_detach_sas(struct mpr_softc *sc); 820int mpr_read_config_page(struct mpr_softc *, struct mpr_config_params *); 821int mpr_write_config_page(struct mpr_softc *, struct mpr_config_params *); 822void mpr_memaddr_cb(void *, bus_dma_segment_t *, int , int ); 823void mpr_memaddr_wait_cb(void *, bus_dma_segment_t *, int , int ); 824void mpr_init_sge(struct mpr_command *cm, void *req, void *sge); 825int mpr_attach_user(struct mpr_softc *); 826void mpr_detach_user(struct mpr_softc *); 827void mprsas_record_event(struct mpr_softc *sc, 828 MPI2_EVENT_NOTIFICATION_REPLY *event_reply); 829 830int mpr_map_command(struct mpr_softc *sc, struct mpr_command *cm); 831int mpr_wait_command(struct mpr_softc *sc, struct mpr_command **cm, int timeout, 832 int sleep_flag); 833int mpr_request_polled(struct mpr_softc *sc, struct mpr_command **cm); 834 835int mpr_config_get_bios_pg3(struct mpr_softc *sc, Mpi2ConfigReply_t 836 *mpi_reply, Mpi2BiosPage3_t *config_page); 837int mpr_config_get_raid_volume_pg0(struct mpr_softc *sc, Mpi2ConfigReply_t 838 *mpi_reply, Mpi2RaidVolPage0_t *config_page, u32 page_address); 839int mpr_config_get_ioc_pg8(struct mpr_softc *sc, Mpi2ConfigReply_t *, 840 Mpi2IOCPage8_t *); 841int mpr_config_get_iounit_pg8(struct mpr_softc *sc, 842 Mpi2ConfigReply_t *mpi_reply, Mpi2IOUnitPage8_t *config_page); 843int mpr_config_get_sas_device_pg0(struct mpr_softc *, Mpi2ConfigReply_t *, 844 Mpi2SasDevicePage0_t *, u32 , u16 ); 845int mpr_config_get_pcie_device_pg0(struct mpr_softc *sc, Mpi2ConfigReply_t 846 *mpi_reply, Mpi26PCIeDevicePage0_t *config_page, u32 form, u16 handle); 847int mpr_config_get_pcie_device_pg2(struct mpr_softc *sc, Mpi2ConfigReply_t 848 *mpi_reply, Mpi26PCIeDevicePage2_t *config_page, u32 form, u16 handle); 849int mpr_config_get_dpm_pg0(struct mpr_softc *, Mpi2ConfigReply_t *, 850 Mpi2DriverMappingPage0_t *, u16 ); 851int mpr_config_get_raid_volume_pg1(struct mpr_softc *sc, 852 Mpi2ConfigReply_t *mpi_reply, Mpi2RaidVolPage1_t *config_page, u32 form, 853 u16 handle); 854int mpr_config_get_volume_wwid(struct mpr_softc *sc, u16 volume_handle, 855 u64 *wwid); 856int mpr_config_get_raid_pd_pg0(struct mpr_softc *sc, 857 Mpi2ConfigReply_t *mpi_reply, Mpi2RaidPhysDiskPage0_t *config_page, 858 u32 page_address); 859int mpr_config_get_man_pg11(struct mpr_softc *sc, Mpi2ConfigReply_t *mpi_reply, 860 Mpi2ManufacturingPage11_t *config_page); 861void mprsas_ir_shutdown(struct mpr_softc *sc, int howto); 862 863int mpr_reinit(struct mpr_softc *sc); 864void mprsas_handle_reinit(struct mpr_softc *sc); 865 866void mpr_base_static_config_pages(struct mpr_softc *sc); 867 868int mpr_mapping_initialize(struct mpr_softc *); 869void mpr_mapping_topology_change_event(struct mpr_softc *, 870 Mpi2EventDataSasTopologyChangeList_t *); 871void mpr_mapping_pcie_topology_change_event(struct mpr_softc *sc, 872 Mpi26EventDataPCIeTopologyChangeList_t *event_data); 873void mpr_mapping_free_memory(struct mpr_softc *sc); 874int mpr_config_set_dpm_pg0(struct mpr_softc *, Mpi2ConfigReply_t *, 875 Mpi2DriverMappingPage0_t *, u16 ); 876void mpr_mapping_exit(struct mpr_softc *); 877void mpr_mapping_check_devices(void *); 878int mpr_mapping_allocate_memory(struct mpr_softc *sc); 879unsigned int mpr_mapping_get_tid(struct mpr_softc *, uint64_t , u16); 880unsigned int mpr_mapping_get_tid_from_handle(struct mpr_softc *sc, 881 u16 handle); 882unsigned int mpr_mapping_get_raid_tid(struct mpr_softc *sc, u64 wwid, 883 u16 volHandle); 884unsigned int mpr_mapping_get_raid_tid_from_handle(struct mpr_softc *sc, 885 u16 volHandle); 886void mpr_mapping_enclosure_dev_status_change_event(struct mpr_softc *, 887 Mpi2EventDataSasEnclDevStatusChange_t *event_data); 888void mpr_mapping_ir_config_change_event(struct mpr_softc *sc, 889 Mpi2EventDataIrConfigChangeList_t *event_data); 890 891void mprsas_evt_handler(struct mpr_softc *sc, uintptr_t data, 892 MPI2_EVENT_NOTIFICATION_REPLY *event); 893void mprsas_prepare_remove(struct mprsas_softc *sassc, uint16_t handle); 894void mprsas_prepare_volume_remove(struct mprsas_softc *sassc, uint16_t handle); 895int mprsas_startup(struct mpr_softc *sc); 896struct mprsas_target * mprsas_find_target_by_handle(struct mprsas_softc *, int, 897 uint16_t); 898void mprsas_realloc_targets(struct mpr_softc *sc, int maxtargets); 899struct mpr_command * mprsas_alloc_tm(struct mpr_softc *sc); 900void mprsas_free_tm(struct mpr_softc *sc, struct mpr_command *tm); 901void mprsas_release_simq_reinit(struct mprsas_softc *sassc); 902int mprsas_send_reset(struct mpr_softc *sc, struct mpr_command *tm, 903 uint8_t type); 904 905SYSCTL_DECL(_hw_mpr); 906 907/* Compatibility shims for different OS versions */ 908#if __FreeBSD_version >= 800001 909#define mpr_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 910 kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 911#define mpr_kproc_exit(arg) kproc_exit(arg) 912#else 913#define mpr_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 914 kthread_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 915#define mpr_kproc_exit(arg) kthread_exit(arg) 916#endif 917 918#if defined(CAM_PRIORITY_XPT) 919#define MPR_PRIORITY_XPT CAM_PRIORITY_XPT 920#else 921#define MPR_PRIORITY_XPT 5 922#endif 923 924#if __FreeBSD_version < 800107 925// Prior to FreeBSD-8.0 scp3_flags was not defined. 926#define spc3_flags reserved 927 928#define SPC3_SID_PROTECT 0x01 929#define SPC3_SID_3PC 0x08 930#define SPC3_SID_TPGS_MASK 0x30 931#define SPC3_SID_TPGS_IMPLICIT 0x10 932#define SPC3_SID_TPGS_EXPLICIT 0x20 933#define SPC3_SID_ACC 0x40 934#define SPC3_SID_SCCS 0x80 935 936#define CAM_PRIORITY_NORMAL CAM_PRIORITY_NONE 937#endif 938 939/* Definitions for SCSI unmap translation to NVMe DSM command */ 940 941/* UNMAP block descriptor structure */ 942struct unmap_blk_desc { 943 uint64_t slba; 944 uint32_t nlb; 945 uint32_t resv; 946}; 947 948/* UNMAP command's data */ 949struct unmap_parm_list { 950 uint16_t unmap_data_len; 951 uint16_t unmap_blk_desc_data_len; 952 uint32_t resv; 953 struct unmap_blk_desc desc[0]; 954}; 955 956/* SCSI ADDITIONAL SENSE Codes */ 957#define FIXED_SENSE_DATA 0x70 958#define SCSI_ASC_NO_SENSE 0x00 959#define SCSI_ASC_PERIPHERAL_DEV_WRITE_FAULT 0x03 960#define SCSI_ASC_LUN_NOT_READY 0x04 961#define SCSI_ASC_WARNING 0x0B 962#define SCSI_ASC_LOG_BLOCK_GUARD_CHECK_FAILED 0x10 963#define SCSI_ASC_LOG_BLOCK_APPTAG_CHECK_FAILED 0x10 964#define SCSI_ASC_LOG_BLOCK_REFTAG_CHECK_FAILED 0x10 965#define SCSI_ASC_UNRECOVERED_READ_ERROR 0x11 966#define SCSI_ASC_MISCOMPARE_DURING_VERIFY 0x1D 967#define SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID 0x20 968#define SCSI_ASC_ILLEGAL_COMMAND 0x20 969#define SCSI_ASC_ILLEGAL_BLOCK 0x21 970#define SCSI_ASC_INVALID_CDB 0x24 971#define SCSI_ASC_INVALID_LUN 0x25 972#define SCSI_ASC_INVALID_PARAMETER 0x26 973#define SCSI_ASC_FORMAT_COMMAND_FAILED 0x31 974#define SCSI_ASC_INTERNAL_TARGET_FAILURE 0x44 975 976/* SCSI ADDITIONAL SENSE Code Qualifiers */ 977#define SCSI_ASCQ_CAUSE_NOT_REPORTABLE 0x00 978#define SCSI_ASCQ_FORMAT_COMMAND_FAILED 0x01 979#define SCSI_ASCQ_LOG_BLOCK_GUARD_CHECK_FAILED 0x01 980#define SCSI_ASCQ_LOG_BLOCK_APPTAG_CHECK_FAILED 0x02 981#define SCSI_ASCQ_LOG_BLOCK_REFTAG_CHECK_FAILED 0x03 982#define SCSI_ASCQ_FORMAT_IN_PROGRESS 0x04 983#define SCSI_ASCQ_POWER_LOSS_EXPECTED 0x08 984#define SCSI_ASCQ_INVALID_LUN_ID 0x09 985 986#endif 987 988