1/*- 2 * SPDX-License-Identifier: MIT-CMU 3 * 4 * Copyright (c) 1995 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Permission to use, copy, modify and distribute this software and 8 * its documentation is hereby granted, provided that both the copyright 9 * notice and this permission notice appear in all copies of the 10 * software, derivative works or modified versions, and any portions 11 * thereof, and that both notices appear in supporting documentation. 12 * 13 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 14 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 15 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 16 * 17 * Carnegie Mellon requests users of this software to return to 18 * 19 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 20 * School of Computer Science 21 * Carnegie Mellon University 22 * Pittsburgh PA 15213-3890 23 * 24 * any improvements or extensions that they make and grant Carnegie the 25 * rights to redistribute these changes. 26 * 27 * $NetBSD: mc146818reg.h,v 1.9 2006/03/08 23:46:25 lukem Exp $ 28 * 29 * $FreeBSD$ 30 */ 31 32/* 33 * Definitions for the Motorola MC146818A Real Time Clock. 34 * They also apply for the (compatible) Dallas Semiconductor DS1287A RTC. 35 * 36 * Though there are undoubtedly other (better) sources, this material was 37 * culled from the DEC "KN121 System Module Programmer's Reference 38 * Information." 39 * 40 * The MC146818A has 16 registers. The first 10 contain time-of-year 41 * and alarm data. The rest contain various control and status bits. 42 * 43 * To read or write the registers, one writes the register number to 44 * the RTC's control port, then either reads from or writes the new 45 * data to the RTC's data port. Since the locations of these ports 46 * and the method used to access them can be machine-dependent, the 47 * low-level details of reading and writing the RTC's registers are 48 * handled by machine-specific functions. 49 * 50 * The time-of-year and alarm data can be expressed in either binary 51 * or BCD, and they are selected by a bit in register B. 52 * 53 * The "hour" time-of-year and alarm fields can either be expressed in 54 * AM/PM format, or in 24-hour format. If AM/PM format is chosen, the 55 * hour fields can have the values: 1-12 and 81-92 (the latter being 56 * PM). If the 24-hour format is chosen, they can have the values 57 * 0-24. The hour format is selectable by a bit in register B. 58 * (XXX IS AM/PM MODE DESCRIPTION CORRECT?) 59 * 60 * It is assumed the if systems are going to use BCD (rather than 61 * binary) mode, or AM/PM hour format, they'll do the appropriate 62 * conversions in machine-dependent code. Also, if the clock is 63 * switched between BCD and binary mode, or between AM/PM mode and 64 * 24-hour mode, the time-of-day and alarm registers are NOT 65 * automatically reset; they must be reprogrammed with correct values. 66 */ 67 68/* 69 * The registers, and the bits within each register. 70 */ 71 72#define MC_SEC 0x0 /* Time of year: seconds (0-59) */ 73#define MC_ASEC 0x1 /* Alarm: seconds */ 74#define MC_MIN 0x2 /* Time of year: minutes (0-59) */ 75#define MC_AMIN 0x3 /* Alarm: minutes */ 76#define MC_HOUR 0x4 /* Time of year: hour (see above) */ 77#define MC_AHOUR 0x5 /* Alarm: hour */ 78#define MC_DOW 0x6 /* Time of year: day of week (1-7) */ 79#define MC_DOM 0x7 /* Time of year: day of month (1-31) */ 80#define MC_MONTH 0x8 /* Time of year: month (1-12) */ 81#define MC_YEAR 0x9 /* Time of year: year in century (0-99) */ 82 83#define MC_REGA 0xa /* Control register A */ 84 85#define MC_REGA_RSMASK 0x0f /* Interrupt rate select mask (see below) */ 86#define MC_REGA_DVMASK 0x70 /* Divisor select mask (see below) */ 87#define MC_REGA_DV0 0x10 /* Divisor 0 */ 88#define MC_REGA_DV1 0x20 /* Divisor 1 */ 89#define MC_REGA_DV2 0x40 /* Divisor 2 */ 90#define MC_REGA_UIP 0x80 /* Update in progress; read only. */ 91 92#define MC_REGB 0xb /* Control register B */ 93 94#define MC_REGB_DSE 0x01 /* Daylight Savings Enable */ 95#define MC_REGB_24HR 0x02 /* 24-hour mode (AM/PM mode when clear) */ 96#define MC_REGB_BINARY 0x04 /* Binary mode (BCD mode when clear) */ 97#define MC_REGB_SQWE 0x08 /* Square Wave Enable */ 98#define MC_REGB_UIE 0x10 /* Update End interrupt enable */ 99#define MC_REGB_AIE 0x20 /* Alarm interrupt enable */ 100#define MC_REGB_PIE 0x40 /* Periodic interrupt enable */ 101#define MC_REGB_SET 0x80 /* Allow time to be set; stops updates */ 102 103#define MC_REGC 0xc /* Control register C */ 104 105/* MC_REGC_UNUSED 0x0f UNUSED */ 106#define MC_REGC_UF 0x10 /* Update End interrupt flag */ 107#define MC_REGC_AF 0x20 /* Alarm interrupt flag */ 108#define MC_REGC_PF 0x40 /* Periodic interrupt flag */ 109#define MC_REGC_IRQF 0x80 /* Interrupt request pending flag */ 110 111#define MC_REGD 0xd /* Control register D */ 112 113/* MC_REGD_UNUSED 0x7f UNUSED */ 114#define MC_REGD_VRT 0x80 /* Valid RAM and Time bit */ 115 116 117#define MC_NREGS 0xe /* 14 registers; CMOS follows */ 118#define MC_NTODREGS 0xa /* 10 of those regs are for TOD and alarm */ 119 120#define MC_NVRAM_START 0xe /* start of NVRAM: offset 14 */ 121#define MC_NVRAM_SIZE 50 /* 50 bytes of NVRAM */ 122 123/* 124 * Periodic Interrupt Rate Select constants (Control register A) 125 */ 126#define MC_RATE_NONE 0x0 /* No periodic interrupt */ 127#define MC_RATE_1 0x1 /* 256 Hz if MC_BASE_32_KHz, else 32768 Hz */ 128#define MC_RATE_2 0x2 /* 128 Hz if MC_BASE_32_KHz, else 16384 Hz */ 129#define MC_RATE_8192_Hz 0x3 /* 122.070 us period */ 130#define MC_RATE_4096_Hz 0x4 /* 244.141 us period */ 131#define MC_RATE_2048_Hz 0x5 /* 488.281 us period */ 132#define MC_RATE_1024_Hz 0x6 /* 976.562 us period */ 133#define MC_RATE_512_Hz 0x7 /* 1.953125 ms period */ 134#define MC_RATE_256_Hz 0x8 /* 3.90625 ms period */ 135#define MC_RATE_128_Hz 0x9 /* 7.8125 ms period */ 136#define MC_RATE_64_Hz 0xa /* 15.625 ms period */ 137#define MC_RATE_32_Hz 0xb /* 31.25 ms period */ 138#define MC_RATE_16_Hz 0xc /* 62.5 ms period */ 139#define MC_RATE_8_Hz 0xd /* 125 ms period */ 140#define MC_RATE_4_Hz 0xe /* 250 ms period */ 141#define MC_RATE_2_Hz 0xf /* 500 ms period */ 142 143/* 144 * Time base (divisor select) constants (Control register A) 145 */ 146#define MC_BASE_4_MHz 0x00 /* 4 MHz crystal */ 147#define MC_BASE_1_MHz MC_REGA_DV0 /* 1 MHz crystal */ 148#define MC_BASE_32_KHz MC_REGA_DV1 /* 32 KHz crystal */ 149#define MC_BASE_NONE (MC_REGA_DV2 | MC_REGA_DV1) /* actually also resets */ 150#define MC_BASE_RESET (MC_REGA_DV2 | MC_REGA_DV1 | MC_REGA_DV0) 151