1/*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
3 *
4 * This file is provided under a dual BSD/GPLv2 license.  When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
23 * The full GNU General Public License is included in this distribution
24 * in the file called LICENSE.GPL.
25 *
26 * BSD LICENSE
27 *
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
29 * All rights reserved.
30 *
31 * Redistribution and use in source and binary forms, with or without
32 * modification, are permitted provided that the following conditions
33 * are met:
34 *
35 *   * Redistributions of source code must retain the above copyright
36 *     notice, this list of conditions and the following disclaimer.
37 *   * Redistributions in binary form must reproduce the above copyright
38 *     notice, this list of conditions and the following disclaimer in
39 *     the documentation and/or other materials provided with the
40 *     distribution.
41 *
42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
43 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
44 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
45 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
46 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
47 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
48 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
49 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
50 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
51 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
52 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53 */
54
55#include <sys/cdefs.h>
56__FBSDID("$FreeBSD$");
57
58/**
59 * @file
60 *
61 * @brief This file contains the method implementations utilized in writing
62 *        out PCI data for the SCI core.
63 */
64
65#include <dev/isci/scil/scic_user_callback.h>
66
67#include <dev/isci/scil/scic_sds_pci.h>
68#include <dev/isci/scil/scic_sds_controller.h>
69
70/**
71 * @brief This method reads from the driver the BARs that are needed to
72 *        determine the virtual memory space for the controller registers
73 *
74 * @param[in] this_controller The controller for which to read the base
75 *            address registers.
76 */
77void scic_sds_pci_bar_initialization(
78   SCIC_SDS_CONTROLLER_T* this_controller
79)
80{
81#ifdef ARLINGTON_BUILD
82
83   #define ARLINGTON_LEX_BAR  0
84   #define ARLINGTON_SMU_BAR  1
85   #define ARLINGTON_SCU_BAR  2
86   #define LEX_REGISTER_OFFSET 0x40000
87
88   this_controller->lex_registers =
89      ((char *)scic_cb_pci_get_bar(
90                     this_controller, ARLINGTON_LEX_BAR) + LEX_REGISTER_OFFSET);
91   this_controller->smu_registers =
92      (SMU_REGISTERS_T *)scic_cb_pci_get_bar(this_controller, ARLINGTON_SMU_BAR);
93   this_controller->scu_registers =
94      (SCU_REGISTERS_T *)scic_cb_pci_get_bar(this_controller, ARLINGTON_SCU_BAR);
95
96#else // !ARLINGTON_BUILD
97
98#if !defined(ENABLE_PCI_IO_SPACE_ACCESS)
99
100   this_controller->smu_registers =
101      (SMU_REGISTERS_T *)(
102         (char *)scic_cb_pci_get_bar(this_controller, PATSBURG_SMU_BAR)
103                +(0x4000 * this_controller->controller_index));
104   this_controller->scu_registers =
105      (SCU_REGISTERS_T *)(
106         (char *)scic_cb_pci_get_bar(this_controller, PATSBURG_SCU_BAR)
107                +(0x400000 * this_controller->controller_index));
108
109#else // !defined(ENABLE_PCI_IO_SPACE_ACCESS)
110
111   if (this_controller->controller_index == 0)
112   {
113      this_controller->smu_registers = (SMU_REGISTERS_T *)
114         scic_cb_pci_get_bar(this_controller, PATSBURG_IO_SPACE_BAR0);
115   }
116   else
117   {
118      if (this_controller->pci_revision == SCU_PBG_HBA_REV_B0)
119      {
120         // SCU B0 violates PCI spec for size of IO bar this is corrected
121         // in subsequent version of the hardware so we can safely use the
122         // else condition below.
123         this_controller->smu_registers = (SMU_REGISTERS_T *)
124            (scic_cb_pci_get_bar(this_controller, PATSBURG_IO_SPACE_BAR0) + 0x100);
125      }
126      else
127      {
128         this_controller->smu_registers = (SMU_REGISTERS_T *)
129            scic_cb_pci_get_bar(this_controller, PATSBURG_IO_SPACE_BAR1);
130      }
131   }
132
133   // No need to get the bar.  We will be using the offset to write to
134   // input/output ports via 0xA0 and 0xA4.
135   this_controller->scu_registers = (SCU_REGISTERS_T *) 0;
136
137#endif // !defined(ENABLE_PCI_IO_SPACE_ACCESS)
138
139#endif // ARLINGTON_BUILD
140}
141
142#if defined(ENABLE_PCI_IO_SPACE_ACCESS) && !defined(ARLINGTON_BUILD)
143
144/**
145 * @brief This method will read from PCI memory for the SMU register
146 *        space via IO space access.
147 *
148 * @param[in]  controller The controller for which to read a DWORD.
149 * @param[in]  address This parameter depicts the address from
150 *             which to read.
151 *
152 * @return The value being returned from the PCI memory location.
153 *
154 * @todo This PCI memory access calls likely need to be optimized into macro?
155 */
156U32 scic_sds_pci_read_smu_dword(
157   SCI_CONTROLLER_HANDLE_T   controller,
158   void                    * address
159)
160{
161   return scic_cb_pci_read_dword(controller, address);
162}
163
164/**
165 * @brief This method will write to PCI memory for the SMU register
166 *        space via IO space access.
167 *
168 * @param[in]  controller The controller for which to read a DWORD.
169 * @param[in]  address This parameter depicts the address into
170 *             which to write.
171 * @param[out] write_value This parameter depicts the value being written
172 *             into the PCI memory location.
173 *
174 * @todo This PCI memory access calls likely need to be optimized into macro?
175 */
176void scic_sds_pci_write_smu_dword(
177   SCI_CONTROLLER_HANDLE_T   controller,
178   void                    * address,
179   U32                       write_value
180)
181{
182   scic_cb_pci_write_dword(controller, address, write_value);
183}
184
185/**
186 * @brief This method will read from PCI memory for the SCU register
187 *        space via IO space access.
188 *
189 * @param[in]  controller The controller for which to read a DWORD.
190 * @param[in]  address This parameter depicts the address from
191 *             which to read.
192 *
193 * @return The value being returned from the PCI memory location.
194 *
195 * @todo This PCI memory access calls likely need to be optimized into macro?
196 */
197U32 scic_sds_pci_read_scu_dword(
198   SCI_CONTROLLER_HANDLE_T   controller,
199   void                    * address
200)
201{
202   SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
203
204   scic_cb_pci_write_dword(
205      controller,
206      (void*) ((char *)(this_controller->smu_registers) + SCU_MMR_ADDRESS_WINDOW_OFFSET),
207      (U32) address
208   );
209
210   return scic_cb_pci_read_dword(
211             controller,
212             (void*) ((char *)(this_controller->smu_registers) + SCU_MMR_DATA_WINDOW_OFFSET)
213          );
214}
215
216/**
217 * @brief This method will write to PCI memory for the SCU register
218 *        space via IO space access.
219 *
220 * @param[in]  controller The controller for which to read a DWORD.
221 * @param[in]  address This parameter depicts the address into
222 *             which to write.
223 * @param[out] write_value This parameter depicts the value being written
224 *             into the PCI memory location.
225 *
226 * @todo This PCI memory access calls likely need to be optimized into macro?
227 */
228void scic_sds_pci_write_scu_dword(
229   SCI_CONTROLLER_HANDLE_T   controller,
230   void                    * address,
231   U32                       write_value
232)
233{
234   SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
235
236   scic_cb_pci_write_dword(
237      controller,
238      (void*) ((char *)(this_controller->smu_registers) + SCU_MMR_ADDRESS_WINDOW_OFFSET),
239      (U32) address
240   );
241
242   scic_cb_pci_write_dword(
243      controller,
244      (void*) ((char *)(this_controller->smu_registers) + SCU_MMR_DATA_WINDOW_OFFSET),
245      write_value
246   );
247}
248
249#endif // defined(ENABLE_PCI_IO_SPACE_ACCESS)
250