1/*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27__FBSDID("$FreeBSD$"); 28 29#ifndef __IOAT_H__ 30#define __IOAT_H__ 31 32#include <sys/param.h> 33#include <machine/bus.h> 34 35/* 36 * This file defines the public interface to the IOAT driver. 37 */ 38 39/* 40 * Enables an interrupt for this operation. Typically, you would only enable 41 * this on the last operation in a group 42 */ 43#define DMA_INT_EN 0x1 44/* 45 * Like M_NOWAIT. Operations will return NULL if they cannot allocate a 46 * descriptor without blocking. 47 */ 48#define DMA_NO_WAIT 0x2 49/* 50 * Disallow prefetching the source of the following operation. Ordinarily, DMA 51 * operations can be pipelined on some hardware. E.g., operation 2's source 52 * may be prefetched before operation 1 completes. 53 */ 54#define DMA_FENCE 0x4 55#define _DMA_GENERIC_FLAGS (DMA_INT_EN | DMA_NO_WAIT | DMA_FENCE) 56 57/* 58 * Emit a CRC32C as the result of a ioat_copy_crc() or ioat_crc(). 59 */ 60#define DMA_CRC_STORE 0x8 61 62/* 63 * Compare the CRC32C of a ioat_copy_crc() or ioat_crc() against an expeceted 64 * value. It is invalid to specify both TEST and STORE. 65 */ 66#define DMA_CRC_TEST 0x10 67#define _DMA_CRC_TESTSTORE (DMA_CRC_STORE | DMA_CRC_TEST) 68 69/* 70 * Use an inline comparison CRC32C or emit an inline CRC32C result. Invalid 71 * without one of STORE or TEST. 72 */ 73#define DMA_CRC_INLINE 0x20 74#define _DMA_CRC_FLAGS (DMA_CRC_STORE | DMA_CRC_TEST | DMA_CRC_INLINE) 75 76/* 77 * Hardware revision number. Different hardware revisions support different 78 * features. For example, 3.2 cannot read from MMIO space, while 3.3 can. 79 */ 80#define IOAT_VER_3_0 0x30 81#define IOAT_VER_3_2 0x32 82#define IOAT_VER_3_3 0x33 83 84/* 85 * Hardware capabilities. Different hardware revisions support different 86 * features. It is often useful to detect specific features than try to infer 87 * them from hardware version. 88 * 89 * Different channels may support different features too; for example, 'PQ' may 90 * only be supported on the first two channels of some hardware. 91 */ 92#define IOAT_DMACAP_PB (1 << 0) 93#define IOAT_DMACAP_CRC (1 << 1) 94#define IOAT_DMACAP_MARKER_SKIP (1 << 2) 95#define IOAT_DMACAP_OLD_XOR (1 << 3) 96#define IOAT_DMACAP_DCA (1 << 4) 97#define IOAT_DMACAP_MOVECRC (1 << 5) 98#define IOAT_DMACAP_BFILL (1 << 6) 99#define IOAT_DMACAP_EXT_APIC (1 << 7) 100#define IOAT_DMACAP_XOR (1 << 8) 101#define IOAT_DMACAP_PQ (1 << 9) 102#define IOAT_DMACAP_DMA_DIF (1 << 10) 103#define IOAT_DMACAP_DWBES (1 << 13) 104#define IOAT_DMACAP_RAID16SS (1 << 17) 105#define IOAT_DMACAP_DMAMC (1 << 18) 106#define IOAT_DMACAP_CTOS (1 << 19) 107 108#define IOAT_DMACAP_STR \ 109 "\20\24Completion_Timeout_Support\23DMA_with_Multicasting_Support" \ 110 "\22RAID_Super_descriptors\16Descriptor_Write_Back_Error_Support" \ 111 "\13DMA_with_DIF\12PQ\11XOR\10Extended_APIC_ID\07Block_Fill\06Move_CRC" \ 112 "\05DCA\04Old_XOR\03Marker_Skipping\02CRC\01Page_Break" 113 114typedef void *bus_dmaengine_t; 115struct bus_dmadesc; 116typedef void (*bus_dmaengine_callback_t)(void *arg, int error); 117 118unsigned ioat_get_nchannels(void); 119 120/* 121 * Called first to acquire a reference to the DMA channel 122 * 123 * Flags may be M_WAITOK or M_NOWAIT. 124 */ 125bus_dmaengine_t ioat_get_dmaengine(uint32_t channel_index, int flags); 126 127/* Release the DMA channel */ 128void ioat_put_dmaengine(bus_dmaengine_t dmaengine); 129 130/* Check the DMA engine's HW version */ 131int ioat_get_hwversion(bus_dmaengine_t dmaengine); 132size_t ioat_get_max_io_size(bus_dmaengine_t dmaengine); 133uint32_t ioat_get_capabilities(bus_dmaengine_t dmaengine); 134int ioat_get_domain(bus_dmaengine_t dmaengine, int *domain); 135 136/* 137 * Set interrupt coalescing on a DMA channel. 138 * 139 * The argument is in microseconds. A zero value disables coalescing. Any 140 * other value delays interrupt generation for N microseconds to provide 141 * opportunity to coalesce multiple operations into a single interrupt. 142 * 143 * Returns an error status, or zero on success. 144 * 145 * - ERANGE if the given value exceeds the delay supported by the hardware. 146 * (All current hardware supports a maximum of 0x3fff microseconds delay.) 147 * - ENODEV if the hardware does not support interrupt coalescing. 148 */ 149int ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay); 150 151/* 152 * Return the maximum supported coalescing period, for use in 153 * ioat_set_interrupt_coalesce(). If the hardware does not support coalescing, 154 * returns zero. 155 */ 156uint16_t ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine); 157 158/* 159 * Acquire must be called before issuing an operation to perform. Release is 160 * called after. Multiple operations can be issued within the context of one 161 * acquire and release 162 */ 163void ioat_acquire(bus_dmaengine_t dmaengine); 164void ioat_release(bus_dmaengine_t dmaengine); 165 166/* 167 * Acquire_reserve can be called to ensure there is room for N descriptors. If 168 * it succeeds, the next N valid operations will successfully enqueue. 169 * 170 * It may fail with: 171 * - ENXIO if the channel is in an errored state, or the driver is being 172 * unloaded 173 * - EAGAIN if mflags included M_NOWAIT 174 * 175 * On failure, the caller does not hold the dmaengine. 176 */ 177int ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags) 178 __result_use_check; 179 180/* 181 * Issue a blockfill operation. The 64-bit pattern 'fillpattern' is written to 182 * 'len' physically contiguous bytes at 'dst'. 183 * 184 * Only supported on devices with the BFILL capability. 185 */ 186struct bus_dmadesc *ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, 187 uint64_t fillpattern, bus_size_t len, bus_dmaengine_callback_t callback_fn, 188 void *callback_arg, uint32_t flags); 189 190/* Issues the copy data operation */ 191struct bus_dmadesc *ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 192 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 193 void *callback_arg, uint32_t flags); 194 195/* 196 * Issue a copy data operation, with constraints: 197 * - src1, src2, dst1, dst2 are all page-aligned addresses 198 * - The quantity to copy is exactly 2 pages; 199 * - src1 -> dst1, src2 -> dst2 200 * 201 * Why use this instead of normal _copy()? You can copy two non-contiguous 202 * pages (src, dst, or both) with one descriptor. 203 */ 204struct bus_dmadesc *ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, 205 bus_addr_t dst1, bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 206 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags); 207 208/* 209 * Copy len bytes from dst to src, like ioat_copy(). 210 * 211 * Additionally, accumulate a CRC32C of the data. 212 * 213 * If initialseed is not NULL, the value it points to is used to seed the 214 * initial value of the CRC32C. 215 * 216 * If flags include DMA_CRC_STORE and not DMA_CRC_INLINE, crcptr is written 217 * with the 32-bit CRC32C result (in wire format). 218 * 219 * If flags include DMA_CRC_TEST and not DMA_CRC_INLINE, the computed CRC32C is 220 * compared with the 32-bit CRC32C pointed to by crcptr. If they do not match, 221 * a channel error is raised. 222 * 223 * If the DMA_CRC_INLINE flag is set, crcptr is ignored and the DMA engine uses 224 * the 4 bytes trailing the source data (TEST) or the destination data (STORE). 225 */ 226struct bus_dmadesc *ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, 227 bus_addr_t src, bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr, 228 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags); 229 230/* 231 * ioat_crc() is nearly identical to ioat_copy_crc(), but does not actually 232 * move data around. 233 * 234 * Like ioat_copy_crc, ioat_crc computes a CRC32C over len bytes pointed to by 235 * src. The flags affect its operation in the same way, with one exception: 236 * 237 * If flags includes both DMA_CRC_STORE and DMA_CRC_INLINE, the computed CRC32C 238 * is written to the 4 bytes trailing the *source* data. 239 */ 240struct bus_dmadesc *ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, 241 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr, 242 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags); 243 244/* 245 * Issues a null operation. This issues the operation to the hardware, but the 246 * hardware doesn't do anything with it. 247 */ 248struct bus_dmadesc *ioat_null(bus_dmaengine_t dmaengine, 249 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags); 250 251 252#endif /* __IOAT_H__ */ 253 254