1/* SPDX-License-Identifier: BSD-3-Clause */ 2/* Copyright (c) 2020, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31/*$FreeBSD$*/ 32 33#ifndef _ICE_COMMON_H_ 34#define _ICE_COMMON_H_ 35 36#include "ice_type.h" 37#include "ice_nvm.h" 38#include "ice_flex_pipe.h" 39#include "virtchnl.h" 40#include "ice_switch.h" 41 42enum ice_fw_modes { 43 ICE_FW_MODE_NORMAL, 44 ICE_FW_MODE_DBG, 45 ICE_FW_MODE_REC, 46 ICE_FW_MODE_ROLLBACK 47}; 48 49void ice_idle_aq(struct ice_hw *hw, struct ice_ctl_q_info *cq); 50bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq); 51 52enum ice_status ice_init_hw(struct ice_hw *hw); 53void ice_deinit_hw(struct ice_hw *hw); 54enum ice_status ice_check_reset(struct ice_hw *hw); 55enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req); 56 57enum ice_status ice_create_all_ctrlq(struct ice_hw *hw); 58enum ice_status ice_init_all_ctrlq(struct ice_hw *hw); 59void ice_shutdown_all_ctrlq(struct ice_hw *hw); 60void ice_destroy_all_ctrlq(struct ice_hw *hw); 61enum ice_status 62ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq, 63 struct ice_rq_event_info *e, u16 *pending); 64enum ice_status 65ice_get_link_status(struct ice_port_info *pi, bool *link_up); 66enum ice_status ice_update_link_info(struct ice_port_info *pi); 67enum ice_status 68ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 69 enum ice_aq_res_access_type access, u32 timeout); 70void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res); 71enum ice_status 72ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res); 73enum ice_status 74ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res); 75enum ice_status 76ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 77 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 78 enum ice_adminq_opc opc, struct ice_sq_cd *cd); 79enum ice_status 80ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, 81 struct ice_aq_desc *desc, void *buf, u16 buf_size, 82 struct ice_sq_cd *cd); 83void ice_clear_pxe_mode(struct ice_hw *hw); 84 85enum ice_status ice_get_caps(struct ice_hw *hw); 86 87void ice_set_safe_mode_caps(struct ice_hw *hw); 88 89enum ice_status ice_set_mac_type(struct ice_hw *hw); 90 91/* Define a macro that will align a pointer to point to the next memory address 92 * that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For 93 * example, given the variable pointer = 0x1006, then after the following call: 94 * 95 * pointer = ICE_ALIGN(pointer, 4) 96 * 97 * ... the value of pointer would equal 0x1008, since 0x1008 is the next 98 * address after 0x1006 which is divisible by 4. 99 */ 100#define ICE_ALIGN(ptr, align) (((ptr) + ((align) - 1)) & ~((align) - 1)) 101 102enum ice_status 103ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 104 u32 rxq_index); 105enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index); 106enum ice_status 107ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index); 108enum ice_status 109ice_write_tx_cmpltnq_ctx(struct ice_hw *hw, 110 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx, 111 u32 tx_cmpltnq_index); 112enum ice_status 113ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index); 114enum ice_status 115ice_write_tx_drbell_q_ctx(struct ice_hw *hw, 116 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx, 117 u32 tx_drbell_q_index); 118 119enum ice_status 120ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, u8 *lut, 121 u16 lut_size); 122enum ice_status 123ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, u8 *lut, 124 u16 lut_size); 125enum ice_status 126ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 127 struct ice_aqc_get_set_rss_keys *keys); 128enum ice_status 129ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 130 struct ice_aqc_get_set_rss_keys *keys); 131enum ice_status 132ice_aq_add_lan_txq(struct ice_hw *hw, u8 count, 133 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 134 struct ice_sq_cd *cd); 135enum ice_status 136ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move, 137 bool is_tc_change, bool subseq_call, bool flush_pipe, 138 u8 timeout, u32 *blocked_cgds, 139 struct ice_aqc_move_txqs_data *buf, u16 buf_size, 140 u8 *txqs_moved, struct ice_sq_cd *cd); 141 142bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq); 143enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading); 144void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode); 145extern const struct ice_ctx_ele ice_tlan_ctx_info[]; 146enum ice_status 147ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 148 const struct ice_ctx_ele *ce_info); 149 150enum ice_status 151ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, 152 void *buf, u16 buf_size, struct ice_sq_cd *cd); 153enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd); 154 155enum ice_status 156ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 157 struct ice_sq_cd *cd); 158enum ice_status 159ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi, 160 bool save_bad_pac, bool pad_short_pac, bool double_vlan, 161 struct ice_sq_cd *cd); 162enum ice_status 163ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 164 struct ice_aqc_get_phy_caps_data *caps, 165 struct ice_sq_cd *cd); 166void 167ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 168 u16 link_speeds_bitmap); 169enum ice_status 170ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 171 struct ice_sq_cd *cd); 172enum ice_status 173ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 174 struct ice_sq_cd *cd); 175 176enum ice_status ice_clear_pf_cfg(struct ice_hw *hw); 177enum ice_status 178ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 179 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd); 180bool ice_fw_supports_link_override(struct ice_hw *hw); 181enum ice_status 182ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 183 struct ice_port_info *pi); 184bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps); 185 186enum ice_fc_mode ice_caps_to_fc_mode(u8 caps); 187enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options); 188enum ice_status 189ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, 190 bool ena_auto_link_update); 191bool 192ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps, 193 struct ice_aqc_set_phy_cfg_data *cfg); 194void 195ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 196 struct ice_aqc_get_phy_caps_data *caps, 197 struct ice_aqc_set_phy_cfg_data *cfg); 198enum ice_status 199ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 200 enum ice_fec_mode fec); 201enum ice_status 202ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 203 struct ice_sq_cd *cd); 204enum ice_status 205ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd); 206enum ice_status 207ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 208 struct ice_link_status *link, struct ice_sq_cd *cd); 209enum ice_status 210ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 211 struct ice_sq_cd *cd); 212enum ice_status 213ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd); 214 215enum ice_status 216ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 217 struct ice_sq_cd *cd); 218enum ice_status 219ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 220 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 221 bool write, struct ice_sq_cd *cd); 222 223enum ice_status 224ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info); 225enum ice_status 226__ice_write_sr_word(struct ice_hw *hw, u32 offset, const u16 *data); 227enum ice_status 228__ice_write_sr_buf(struct ice_hw *hw, u32 offset, u16 words, const u16 *data); 229enum ice_status 230ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 231 u16 *q_handle, u16 *q_ids, u32 *q_teids, 232 enum ice_disq_rst_src rst_src, u16 vmvf_num, 233 struct ice_sq_cd *cd); 234enum ice_status 235ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 236 u16 *max_lanqs); 237enum ice_status 238ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 239 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 240 struct ice_sq_cd *cd); 241enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle); 242void ice_replay_post(struct ice_hw *hw); 243void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw); 244void ice_sched_replay_agg(struct ice_hw *hw); 245enum ice_status ice_sched_replay_tc_node_bw(struct ice_port_info *pi); 246enum ice_status ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle); 247enum ice_status ice_sched_replay_root_node_bw(struct ice_port_info *pi); 248enum ice_status 249ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx); 250struct ice_q_ctx * 251ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle); 252void 253ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 254 u64 *prev_stat, u64 *cur_stat); 255void 256ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 257 u64 *prev_stat, u64 *cur_stat); 258void 259ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded, 260 struct ice_eth_stats *cur_stats); 261enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw); 262void ice_print_rollback_msg(struct ice_hw *hw); 263enum ice_status 264ice_aq_alternate_write(struct ice_hw *hw, u32 reg_addr0, u32 reg_val0, 265 u32 reg_addr1, u32 reg_val1); 266enum ice_status 267ice_aq_alternate_read(struct ice_hw *hw, u32 reg_addr0, u32 *reg_val0, 268 u32 reg_addr1, u32 *reg_val1); 269enum ice_status 270ice_aq_alternate_write_done(struct ice_hw *hw, u8 bios_mode, 271 bool *reset_needed); 272enum ice_status ice_aq_alternate_clear(struct ice_hw *hw); 273enum ice_status 274ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 275 struct ice_aqc_txsched_elem_data *buf); 276enum ice_status 277ice_get_cur_lldp_persist_status(struct ice_hw *hw, u32 *lldp_status); 278enum ice_status 279ice_get_dflt_lldp_persist_status(struct ice_hw *hw, u32 *lldp_status); 280enum ice_status ice_get_netlist_ver_info(struct ice_hw *hw); 281enum ice_status 282ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 283 struct ice_sq_cd *cd); 284bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw); 285enum ice_status 286ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add); 287#endif /* _ICE_COMMON_H_ */ 288