1/*- 2 * Copyright (c) 2015 Semihalf 3 * Copyright (c) 2015 Stormshield 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31#ifndef _E6000SWREG_H_ 32#define _E6000SWREG_H_ 33 34struct atu_opt { 35 uint16_t mac_01; 36 uint16_t mac_23; 37 uint16_t mac_45; 38 uint16_t fid; 39}; 40 41/* 42 * Definitions for the Marvell 88E6000 series Ethernet Switch. 43 */ 44 45/* Switch IDs. */ 46#define MV88E6141 0x3400 47#define MV88E6341 0x3410 48#define MV88E6352 0x3520 49#define MV88E6172 0x1720 50#define MV88E6176 0x1760 51 52#define MVSWITCH(_sc, id) ((_sc)->swid == (id)) 53 54/* 55 * Switch Registers 56 */ 57#define REG_GLOBAL 0x1b 58#define REG_GLOBAL2 0x1c 59#define REG_PORT(p) (0x10 + (p)) 60 61#define REG_NUM_MAX 31 62 63/* 64 * Per-Port Switch Registers 65 */ 66#define PORT_STATUS 0x0 67#define PORT_STATUS_SPEED_MASK 0x300 68#define PORT_STATUS_SPEED_10 0 69#define PORT_STATUS_SPEED_100 1 70#define PORT_STATUS_SPEED_1000 2 71#define PORT_STATUS_DUPLEX_MASK (1 << 10) 72#define PORT_STATUS_LINK_MASK (1 << 11) 73#define PORT_STATUS_PHY_DETECT_MASK (1 << 12) 74 75#define PSC_CONTROL 0x1 76#define PSC_CONTROL_FORCED_SPD (1 << 13) 77#define PSC_CONTROL_EEE_ON (1 << 9) 78#define PSC_CONTROL_FORCED_EEE (1 << 8) 79#define PSC_CONTROL_FC_ON (1 << 7) 80#define PSC_CONTROL_FORCED_FC (1 << 6) 81#define PSC_CONTROL_LINK_UP (1 << 5) 82#define PSC_CONTROL_FORCED_LINK (1 << 4) 83#define PSC_CONTROL_FULLDPX (1 << 3) 84#define PSC_CONTROL_FORCED_DPX (1 << 2) 85#define PSC_CONTROL_SPD2500 0x3 86#define PSC_CONTROL_SPD1000 0x2 87#define SWITCH_ID 0x3 88#define PORT_CONTROL 0x4 89#define PORT_CONTROL_1 0x5 90#define PORT_CONTROL_1_FID_MASK 0xf 91#define PORT_VLAN_MAP 0x6 92#define PORT_VID 0x7 93#define PORT_ASSOCIATION_VECTOR 0xb 94#define PORT_ATU_CTRL 0xc 95#define RX_COUNTER 0x12 96#define TX_COUNTER 0x13 97 98#define PORT_VID_DEF_VID 0 99#define PORT_VID_DEF_VID_MASK 0xfff 100#define PORT_VID_PRIORITY_MASK 0xc00 101 102#define PORT_CONTROL_ENABLE 0x3 103 104/* PORT_VLAN fields */ 105#define PORT_VLAN_MAP_TABLE_MASK 0x7f 106#define PORT_VLAN_MAP_FID 12 107#define PORT_VLAN_MAP_FID_MASK 0xf000 108 109/* 110 * Switch Global Register 1 accessed via REG_GLOBAL_ADDR 111 */ 112#define SWITCH_GLOBAL_STATUS 0 113#define SWITCH_GLOBAL_CONTROL 4 114#define SWITCH_GLOBAL_CONTROL2 28 115 116#define MONITOR_CONTROL 26 117 118/* ATU operation */ 119#define ATU_FID 1 120#define ATU_CONTROL 10 121#define ATU_OPERATION 11 122#define ATU_DATA 12 123#define ATU_MAC_ADDR01 13 124#define ATU_MAC_ADDR23 14 125#define ATU_MAC_ADDR45 15 126 127#define ATU_UNIT_BUSY (1 << 15) 128#define ENTRY_STATE 0xf 129 130/* ATU_CONTROL fields */ 131#define ATU_CONTROL_AGETIME 4 132#define ATU_CONTROL_AGETIME_MASK 0xff0 133#define ATU_CONTROL_LEARN2ALL 3 134 135/* ATU opcode */ 136#define NO_OPERATION (0 << 0) 137#define FLUSH_ALL (1 << 0) 138#define FLUSH_NON_STATIC (1 << 1) 139#define LOAD_FROM_FIB (3 << 0) 140#define PURGE_FROM_FIB (3 << 0) 141#define GET_NEXT_IN_FIB (1 << 2) 142#define FLUSH_ALL_IN_FIB (5 << 0) 143#define FLUSH_NON_STATIC_IN_FIB (3 << 1) 144#define GET_VIOLATION_DATA (7 << 0) 145#define CLEAR_VIOLATION_DATA (7 << 0) 146 147/* ATU Stats */ 148#define COUNT_ALL (0 << 0) 149 150/* 151 * Switch Global Register 2 accessed via REG_GLOBAL2_ADDR 152 */ 153#define MGMT_EN_2x 2 154#define MGMT_EN_0x 3 155#define SWITCH_MGMT 5 156#define ATU_STATS 14 157 158#define MGMT_EN_ALL 0xffff 159 160/* SWITCH_MGMT fields */ 161 162#define SWITCH_MGMT_PRI 0 163#define SWITCH_MGMT_PRI_MASK 7 164#define SWITCH_MGMT_RSVD2CPU 3 165#define SWITCH_MGMT_FC_PRI 4 166#define SWITCH_MGMT_FC_PRI_MASK (7 << 4) 167#define SWITCH_MGMT_FORCEFLOW 7 168 169/* ATU_STATS fields */ 170 171#define ATU_STATS_BIN 14 172#define ATU_STATS_FLAG 12 173 174/* 175 * PHY registers accessed via 'Switch Global Registers' (REG_GLOBAL2). 176 */ 177#define SMI_PHY_CMD_REG 0x18 178#define SMI_PHY_DATA_REG 0x19 179 180#define PHY_DATA_MASK 0xffff 181 182#define PHY_CMD_SMI_BUSY 15 183#define PHY_CMD_MODE 12 184#define PHY_CMD_MODE_MDIO 1 185#define PHY_CMD_MODE_XMDIO 0 186#define PHY_CMD_OPCODE 10 187#define PHY_CMD_OPCODE_WRITE 1 188#define PHY_CMD_OPCODE_READ 2 189#define PHY_CMD_DEV_ADDR 5 190#define PHY_CMD_DEV_ADDR_MASK 0x3e0 191#define PHY_CMD_REG_ADDR 0 192#define PHY_CMD_REG_ADDR_MASK 0x1f 193 194#define PHY_PAGE_REG 22 195 196/* 197 * Scratch and Misc register accessed via 198 * 'Switch Global Registers' (REG_GLOBAL2) 199 */ 200#define SCR_AND_MISC_REG 0x1a 201 202#define SCR_AND_MISC_PTR_CFG 0x7000 203#define SCR_AND_MISC_DATA_CFG_MASK 0xf0 204 205#define E6000SW_NUM_PHY_REGS 29 206#define E6000SW_MAX_PORTS 8 207#define E6000SW_DEFAULT_AGETIME 20 208#define E6000SW_RETRIES 100 209#define E6000SW_SMI_TIMEOUT 16 210 211#endif /* _E6000SWREG_H_ */ 212