1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1995, David Greenman 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32#ifndef SYS_DEV_ED_IF_EDVAR_H 33#define SYS_DEV_ED_IF_EDVAR_H 34 35#include <dev/mii/mii_bitbang.h> 36 37/* 38 * ed_softc: per line info and status 39 */ 40struct ed_softc { 41 struct ifnet *ifp; 42 struct ifmedia ifmedia; /* Media info */ 43 device_t dev; 44 struct mtx sc_mtx; 45 46 char *type_str; /* pointer to type string */ 47 u_char vendor; /* interface vendor */ 48 u_char type; /* interface type code */ 49 u_char chip_type; /* the type of chip (one of ED_CHIP_TYPE_*) */ 50 u_char isa16bit; /* width of access to card 0=8 or 1=16 */ 51 u_char mem_shared; /* NIC memory is shared with host */ 52 u_char xmit_busy; /* transmitter is busy */ 53 u_char enaddr[6]; 54 55 int port_used; /* nonzero if ports used */ 56 struct resource* port_res; /* resource for port range */ 57 struct resource* port_res2; /* resource for port range */ 58 bus_space_tag_t port_bst; 59 bus_space_handle_t port_bsh; 60 int mem_used; /* nonzero if memory used */ 61 struct resource* mem_res; /* resource for memory range */ 62 bus_space_tag_t mem_bst; 63 bus_space_handle_t mem_bsh; 64 struct resource* irq_res; /* resource for irq */ 65 void* irq_handle; /* handle for irq handler */ 66 int (*sc_media_ioctl)(struct ed_softc *sc, struct ifreq *ifr, 67 u_long command); 68 void (*sc_mediachg)(struct ed_softc *); 69 device_t miibus; /* MII bus for cards with MII. */ 70 mii_bitbang_ops_t mii_bitbang_ops; 71 struct callout tick_ch; 72 void (*sc_tick)(struct ed_softc *); 73 void (*readmem)(struct ed_softc *sc, bus_size_t src, uint8_t *dst, 74 uint16_t amount); 75 u_short (*sc_write_mbufs)(struct ed_softc *, struct mbuf *, bus_size_t); 76 77 int tx_timer; 78 int nic_offset; /* NIC (DS8390) I/O bus address offset */ 79 int asic_offset; /* ASIC I/O bus address offset */ 80 81/* 82 * The following 'proto' variable is part of a work-around for 8013EBT asics 83 * being write-only. It's sort of a prototype/shadow of the real thing. 84 */ 85 u_char wd_laar_proto; 86 u_char cr_proto; 87 88/* 89 * HP PC LAN PLUS card support. 90 */ 91 92 u_short hpp_options; /* flags controlling behaviour of the HP card */ 93 u_short hpp_id; /* software revision and other fields */ 94 caddr_t hpp_mem_start; /* Memory-mapped IO register address */ 95 96 bus_size_t mem_start; /* NIC memory start address */ 97 bus_size_t mem_end; /* NIC memory end address */ 98 uint32_t mem_size; /* total NIC memory size */ 99 bus_size_t mem_ring; /* start of RX ring-buffer (in NIC mem) */ 100 101 u_char txb_cnt; /* number of transmit buffers */ 102 u_char txb_inuse; /* number of TX buffers currently in-use */ 103 104 u_char txb_new; /* pointer to where new buffer will be added */ 105 u_char txb_next_tx; /* pointer to next buffer ready to xmit */ 106 u_short txb_len[8]; /* buffered xmit buffer lengths */ 107 u_char tx_page_start; /* first page of TX buffer area */ 108 u_char rec_page_start; /* first page of RX ring-buffer */ 109 u_char rec_page_stop; /* last page of RX ring-buffer */ 110 u_char next_packet; /* pointer to next unread RX packet */ 111 u_int tx_mem; /* Total amount of RAM for tx */ 112 u_int rx_mem; /* Total amount of RAM for rx */ 113 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 114}; 115 116#define ed_nic_barrier(sc, port, length, flags) \ 117 bus_space_barrier(sc->port_bst, sc->port_bsh, \ 118 (sc)->nic_offset + (port), (length), (flags)) 119 120#define ed_nic_inb(sc, port) \ 121 bus_space_read_1(sc->port_bst, sc->port_bsh, (sc)->nic_offset + (port)) 122 123#define ed_nic_outb(sc, port, value) \ 124 bus_space_write_1(sc->port_bst, sc->port_bsh, \ 125 (sc)->nic_offset + (port), (value)) 126 127#define ed_nic_inw(sc, port) \ 128 bus_space_read_2(sc->port_bst, sc->port_bsh, (sc)->nic_offset + (port)) 129 130#define ed_nic_outw(sc, port, value) \ 131 bus_space_write_2(sc->port_bst, sc->port_bsh, \ 132 (sc)->nic_offset + (port), (value)) 133 134#define ed_nic_insb(sc, port, addr, count) \ 135 bus_space_read_multi_1(sc->port_bst, sc->port_bsh, \ 136 (sc)->nic_offset + (port), (addr), (count)) 137 138#define ed_nic_outsb(sc, port, addr, count) \ 139 bus_space_write_multi_1(sc->port_bst, sc->port_bsh, \ 140 (sc)->nic_offset + (port), (addr), (count)) 141 142#define ed_nic_insw(sc, port, addr, count) \ 143 bus_space_read_multi_2(sc->port_bst, sc->port_bsh, \ 144 (sc)->nic_offset + (port), (uint16_t *)(addr), (count)) 145 146#define ed_nic_outsw(sc, port, addr, count) \ 147 bus_space_write_multi_2(sc->port_bst, sc->port_bsh, \ 148 (sc)->nic_offset + (port), (uint16_t *)(addr), (count)) 149 150#define ed_nic_insl(sc, port, addr, count) \ 151 bus_space_read_multi_4(sc->port_bst, sc->port_bsh, \ 152 (sc)->nic_offset + (port), (uint32_t *)(addr), (count)) 153 154#define ed_nic_outsl(sc, port, addr, count) \ 155 bus_space_write_multi_4(sc->port_bst, sc->port_bsh, \ 156 (sc)->nic_offset + (port), (uint32_t *)(addr), (count)) 157 158#define ed_asic_barrier(sc, port, length, flags) \ 159 bus_space_barrier(sc->port_bst, sc->port_bsh, \ 160 (sc)->asic_offset + (port), (length), (flags)) 161 162#define ed_asic_inb(sc, port) \ 163 bus_space_read_1(sc->port_bst, sc->port_bsh, \ 164 (sc)->asic_offset + (port)) 165 166#define ed_asic_outb(sc, port, value) \ 167 bus_space_write_1(sc->port_bst, sc->port_bsh, \ 168 (sc)->asic_offset + (port), (value)) 169 170#define ed_asic_inw(sc, port) \ 171 bus_space_read_2(sc->port_bst, sc->port_bsh, \ 172 (sc)->asic_offset + (port)) 173 174#define ed_asic_outw(sc, port, value) \ 175 bus_space_write_2(sc->port_bst, sc->port_bsh, \ 176 (sc)->asic_offset + (port), (value)) 177 178#define ed_asic_insb(sc, port, addr, count) \ 179 bus_space_read_multi_1(sc->port_bst, sc->port_bsh, \ 180 (sc)->asic_offset + (port), (addr), (count)) 181 182#define ed_asic_outsb(sc, port, addr, count) \ 183 bus_space_write_multi_1(sc->port_bst, sc->port_bsh, \ 184 (sc)->asic_offset + (port), (addr), (count)) 185 186#define ed_asic_insw(sc, port, addr, count) \ 187 bus_space_read_multi_2(sc->port_bst, sc->port_bsh, \ 188 (sc)->asic_offset + (port), (uint16_t *)(addr), (count)) 189 190#define ed_asic_outsw(sc, port, addr, count) \ 191 bus_space_write_multi_2(sc->port_bst, sc->port_bsh, \ 192 (sc)->asic_offset + (port), (uint16_t *)(addr), (count)) 193 194#define ed_asic_insl(sc, port, addr, count) \ 195 bus_space_read_multi_4(sc->port_bst, sc->port_bsh, \ 196 (sc)->asic_offset + (port), (uint32_t *)(addr), (count)) 197 198#define ed_asic_outsl(sc, port, addr, count) \ 199 bus_space_write_multi_4(sc->port_bst, sc->port_bsh, \ 200 (sc)->asic_offset + (port), (uint32_t *)(addr), (count)) 201 202void ed_release_resources(device_t); 203int ed_alloc_port(device_t, int, int); 204int ed_alloc_memory(device_t, int, int); 205int ed_alloc_irq(device_t, int, int); 206 207int ed_probe_generic8390(struct ed_softc *); 208int ed_probe_WD80x3(device_t, int, int); 209int ed_probe_WD80x3_generic(device_t, int, uint16_t *[]); 210int ed_probe_RTL80x9(device_t, int, int); 211#ifdef ED_3C503 212int ed_probe_3Com(device_t, int, int); 213#endif 214#ifdef ED_SIC 215int ed_probe_SIC(device_t, int, int); 216#endif 217int ed_probe_Novell_generic(device_t, int); 218int ed_probe_Novell(device_t, int, int); 219void ed_Novell_read_mac(struct ed_softc *); 220#ifdef ED_HPP 221int ed_probe_HP_pclanp(device_t, int, int); 222#endif 223 224int ed_attach(device_t); 225int ed_detach(device_t); 226int ed_clear_memory(device_t); 227int ed_isa_mem_ok(device_t, u_long, u_int); /* XXX isa specific */ 228void ed_stop(struct ed_softc *); 229void ed_shmem_readmem16(struct ed_softc *, bus_size_t, uint8_t *, uint16_t); 230void ed_shmem_readmem8(struct ed_softc *, bus_size_t, uint8_t *, uint16_t); 231u_short ed_shmem_write_mbufs(struct ed_softc *, struct mbuf *, bus_size_t); 232void ed_pio_readmem(struct ed_softc *, bus_size_t, uint8_t *, uint16_t); 233void ed_pio_writemem(struct ed_softc *, uint8_t *, uint16_t, uint16_t); 234u_short ed_pio_write_mbufs(struct ed_softc *, struct mbuf *, bus_size_t); 235 236void ed_disable_16bit_access(struct ed_softc *); 237void ed_enable_16bit_access(struct ed_softc *); 238 239void ed_gen_ifmedia_init(struct ed_softc *); 240 241driver_intr_t edintr; 242 243extern devclass_t ed_devclass; 244 245 246/* 247 * Vendor types 248 */ 249#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */ 250#define ED_VENDOR_3COM 0x01 /* 3Com */ 251#define ED_VENDOR_NOVELL 0x02 /* Novell */ 252#define ED_VENDOR_HP 0x03 /* Hewlett Packard */ 253#define ED_VENDOR_SIC 0x04 /* Allied-Telesis SIC */ 254 255/* 256 * Configure time flags 257 */ 258/* 259 * this sets the default for enabling/disabling the transceiver 260 */ 261#define ED_FLAGS_DISABLE_TRANCEIVER 0x0001 262 263/* 264 * This forces the board to be used in 8/16bit mode even if it 265 * autoconfigs differently 266 */ 267#define ED_FLAGS_FORCE_8BIT_MODE 0x0002 268#define ED_FLAGS_FORCE_16BIT_MODE 0x0004 269 270/* 271 * This disables the use of double transmit buffers. 272 */ 273#define ED_FLAGS_NO_MULTI_BUFFERING 0x0008 274 275/* 276 * This forces all operations with the NIC memory to use Programmed 277 * I/O (i.e. not via shared memory) 278 */ 279#define ED_FLAGS_FORCE_PIO 0x0010 280 281/* 282 * This forces a PC Card, and disables ISA memory range checks 283 */ 284#define ED_FLAGS_PCCARD 0x0020 285 286/* 287 * These are flags describing the chip type. 288 */ 289#define ED_FLAGS_TOSH_ETHER 0x10000 290#define ED_FLAGS_GWETHER 0x20000 291 292#define ED_FLAGS_GETTYPE(flg) ((flg) & 0xff0000) 293 294#define ED_MUTEX(_sc) (&(_sc)->sc_mtx) 295#define ED_LOCK(_sc) mtx_lock(ED_MUTEX(_sc)) 296#define ED_UNLOCK(_sc) mtx_unlock(ED_MUTEX(_sc)) 297#define ED_LOCK_INIT(_sc) \ 298 mtx_init(ED_MUTEX(_sc), device_get_nameunit(_sc->dev), \ 299 MTX_NETWORK_LOCK, MTX_DEF) 300#define ED_LOCK_DESTROY(_sc) mtx_destroy(ED_MUTEX(_sc)); 301#define ED_ASSERT_LOCKED(_sc) mtx_assert(ED_MUTEX(_sc), MA_OWNED); 302#define ED_ASSERT_UNLOCKED(_sc) mtx_assert(ED_MUTEX(_sc), MA_NOTOWNED); 303 304#endif /* SYS_DEV_ED_IF_EDVAR_H */ 305