1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2005, M. Warner Losh 5 * Copyright (c) 1995, David Greenman 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33/* 34 * Notes for adding media support. Each chipset is somewhat different 35 * from the others. Linux has a table of OIDs that it uses to see what 36 * supports the misc register of the NS83903. But a sampling of datasheets 37 * I could dig up on cards I own paints a different picture. 38 * 39 * Chipset specific details: 40 * NS 83903/902A paired 41 * ccr base 0x1020 42 * id register at 0x1000: 7-3 = 0, 2-0 = 1. 43 * (maybe this test is too week) 44 * misc register at 0x018: 45 * 6 WAIT_TOUTENABLE enable watchdog timeout 46 * 3 AUI/TPI 1 AUX, 0 TPI 47 * 2 loopback 48 * 1 gdlink (tpi mode only) 1 tp good, 0 tp bad 49 * 0 0-no mam, 1 mam connected 50 * 51 * NS83926 appears to be a NS pcmcia glue chip used on the IBM Ethernet II 52 * and the NEC PC9801N-J12 ccr base 0x2000! 53 * 54 * winbond 289c926 55 * ccr base 0xfd0 56 * cfb (am 0xff2): 57 * 0-1 PHY01 00 TPI, 01 10B2, 10 10B5, 11 TPI (reduced squ) 58 * 2 LNKEN 0 - enable link and auto switch, 1 disable 59 * 3 LNKSTS TPI + LNKEN=0 + link good == 1, else 0 60 * sr (am 0xff4) 61 * 88 00 88 00 88 00, etc 62 * 63 * TMI tc3299a (cr PHY01 == 0) 64 * ccr base 0x3f8 65 * cra (io 0xa) 66 * crb (io 0xb) 67 * 0-1 PHY01 00 auto, 01 res, 10 10B5, 11 TPI 68 * 2 GDLINK 1 disable checking of link 69 * 6 LINK 0 bad link, 1 good link 70 * 71 * EN5017A, EN5020 no data, but very popular 72 * Other chips? 73 * NetBSD supports RTL8019, but none have surfaced that I can see 74 */ 75 76#include <sys/param.h> 77#include <sys/systm.h> 78#include <sys/socket.h> 79#include <sys/kernel.h> 80#include <sys/module.h> 81#include <sys/bus.h> 82#include <machine/bus.h> 83#include <sys/rman.h> 84#include <machine/resource.h> 85 86#include <net/ethernet.h> 87#include <net/if.h> 88#include <net/if_var.h> 89#include <net/if_arp.h> 90#include <net/if_mib.h> 91#include <net/if_media.h> 92 93#include <dev/ed/if_edreg.h> 94#include <dev/ed/if_edvar.h> 95#include <dev/ed/ax88x90reg.h> 96#include <dev/ed/dl100xxreg.h> 97#include <dev/ed/tc5299jreg.h> 98#include <dev/pccard/pccardvar.h> 99#include <dev/pccard/pccardreg.h> 100#include <dev/pccard/pccard_cis.h> 101#include <dev/mii/mii.h> 102#include <dev/mii/miivar.h> 103 104#include "card_if.h" 105/* "device miibus" required. See GENERIC if you get errors here. */ 106#include "miibus_if.h" 107#include "pccarddevs.h" 108 109/* 110 * NE-2000 based PC Cards have a number of ways to get the MAC address. 111 * Some cards encode this as a FUNCE. Others have this in the ROMs the 112 * same way that ISA cards do. Some have it encoded in the attribute 113 * memory somewhere that isn't in the CIS. Some new chipsets have it 114 * in special registers in the ASIC part of the chip. 115 * 116 * For those cards that have the MAC adress stored in attribute memory 117 * outside of a FUNCE entry in the CIS, nearly all of them have it at 118 * a fixed offset (0xff0). We use that offset as a source of last 119 * resource if other offsets have failed. This is the address of the 120 * National Semiconductor DP83903A, which is the only chip's datasheet 121 * I've found. 122 */ 123#define ED_DEFAULT_MAC_OFFSET 0xff0 124 125static const struct ed_product { 126 struct pccard_product prod; 127 int flags; 128#define NE2000DVF_DL100XX 0x0001 /* chip is D-Link DL10019/22 */ 129#define NE2000DVF_AX88X90 0x0002 /* chip is ASIX AX88[17]90 */ 130#define NE2000DVF_TC5299J 0x0004 /* chip is Tamarack TC5299J */ 131#define NE2000DVF_TOSHIBA 0x0008 /* Toshiba DP83902A */ 132#define NE2000DVF_ENADDR 0x0100 /* Get MAC from attr mem */ 133#define NE2000DVF_ANYFUNC 0x0200 /* Allow any function type */ 134#define NE2000DVF_MODEM 0x0400 /* Has a modem/serial */ 135 int enoff; 136} ed_pccard_products[] = { 137 { PCMCIA_CARD(ACCTON, EN2212), 0}, 138 { PCMCIA_CARD(ACCTON, EN2216), 0}, 139 { PCMCIA_CARD(ALLIEDTELESIS, LA_PCM), 0}, 140 { PCMCIA_CARD(AMBICOM, AMB8002), 0}, 141 { PCMCIA_CARD(AMBICOM, AMB8002T), 0}, 142 { PCMCIA_CARD(AMBICOM, AMB8010), 0}, 143 { PCMCIA_CARD(AMBICOM, AMB8010_ALT), 0}, 144 { PCMCIA_CARD(AMBICOM, AMB8610), 0}, 145 { PCMCIA_CARD(BILLIONTON, CFLT10N), 0}, 146 { PCMCIA_CARD(BILLIONTON, LNA100B), NE2000DVF_AX88X90}, 147 { PCMCIA_CARD(BILLIONTON, LNT10TB), 0}, 148 { PCMCIA_CARD(BILLIONTON, LNT10TN), 0}, 149 { PCMCIA_CARD(BROMAX, AXNET), NE2000DVF_AX88X90}, 150 { PCMCIA_CARD(BROMAX, IPORT), 0}, 151 { PCMCIA_CARD(BROMAX, IPORT2), 0}, 152 { PCMCIA_CARD(BUFFALO, LPC2_CLT), 0}, 153 { PCMCIA_CARD(BUFFALO, LPC3_CLT), 0}, 154 { PCMCIA_CARD(BUFFALO, LPC3_CLX), NE2000DVF_AX88X90}, 155 { PCMCIA_CARD(BUFFALO, LPC4_TX), NE2000DVF_AX88X90}, 156 { PCMCIA_CARD(BUFFALO, LPC4_CLX), NE2000DVF_AX88X90}, 157 { PCMCIA_CARD(BUFFALO, LPC_CF_CLT), 0}, 158 { PCMCIA_CARD(CNET, NE2000), 0}, 159 { PCMCIA_CARD(COMPEX, AX88190), NE2000DVF_AX88X90}, 160 { PCMCIA_CARD(COMPEX, LANMODEM), 0}, 161 { PCMCIA_CARD(COMPEX, LINKPORT_ENET_B), 0}, 162 { PCMCIA_CARD(COREGA, ETHER_II_PCC_T), 0}, 163 { PCMCIA_CARD(COREGA, ETHER_II_PCC_TD), 0}, 164 { PCMCIA_CARD(COREGA, ETHER_PCC_T), 0}, 165 { PCMCIA_CARD(COREGA, ETHER_PCC_TD), 0}, 166 { PCMCIA_CARD(COREGA, FAST_ETHER_PCC_TX), NE2000DVF_DL100XX}, 167 { PCMCIA_CARD(COREGA, FETHER_PCC_TXD), NE2000DVF_AX88X90}, 168 { PCMCIA_CARD(COREGA, FETHER_PCC_TXF), NE2000DVF_DL100XX}, 169 { PCMCIA_CARD(COREGA, FETHER_II_PCC_TXD), NE2000DVF_AX88X90}, 170 { PCMCIA_CARD(COREGA, LAPCCTXD), 0}, 171 { PCMCIA_CARD(DAYNA, COMMUNICARD_E_1), 0}, 172 { PCMCIA_CARD(DAYNA, COMMUNICARD_E_2), 0}, 173 { PCMCIA_CARD(DLINK, DE650), NE2000DVF_ANYFUNC }, 174 { PCMCIA_CARD(DLINK, DE660), 0 }, 175 { PCMCIA_CARD(DLINK, DE660PLUS), 0}, 176 { PCMCIA_CARD(DYNALINK, L10C), 0}, 177 { PCMCIA_CARD(EDIMAX, EP4000A), 0}, 178 { PCMCIA_CARD(EPSON, EEN10B), 0}, 179 { PCMCIA_CARD(EXP, THINLANCOMBO), 0}, 180 { PCMCIA_CARD(GLOBALVILLAGE, LANMODEM), 0}, 181 { PCMCIA_CARD(GREY_CELL, TDK3000), 0}, 182 { PCMCIA_CARD(GREY_CELL, DMF650TX), 183 NE2000DVF_ANYFUNC | NE2000DVF_DL100XX | NE2000DVF_MODEM}, 184 { PCMCIA_CARD(GVC, NIC_2000P), 0}, 185 { PCMCIA_CARD(IBM, HOME_AND_AWAY), 0}, 186 { PCMCIA_CARD(IBM, INFOMOVER), 0}, 187 { PCMCIA_CARD(IODATA3, PCLAT), 0}, 188 { PCMCIA_CARD(KINGSTON, CIO10T), 0}, 189 { PCMCIA_CARD(KINGSTON, KNE2), 0}, 190 { PCMCIA_CARD(LANTECH, FASTNETTX), NE2000DVF_AX88X90}, 191 /* Same ID for many different cards, including generic NE2000 */ 192 { PCMCIA_CARD(LINKSYS, COMBO_ECARD), 193 NE2000DVF_DL100XX | NE2000DVF_AX88X90}, 194 { PCMCIA_CARD(LINKSYS, ECARD_1), 0}, 195 { PCMCIA_CARD(LINKSYS, ECARD_2), 0}, 196 { PCMCIA_CARD(LINKSYS, ETHERFAST), NE2000DVF_DL100XX}, 197 { PCMCIA_CARD(LINKSYS, TRUST_COMBO_ECARD), 0}, 198 { PCMCIA_CARD(MACNICA, ME1_JEIDA), 0}, 199 { PCMCIA_CARD(MAGICRAM, ETHER), 0}, 200 { PCMCIA_CARD(MELCO, LPC3_CLX), NE2000DVF_AX88X90}, 201 { PCMCIA_CARD(MELCO, LPC3_TX), NE2000DVF_AX88X90}, 202 { PCMCIA_CARD(MELCO2, LPC2_T), 0}, 203 { PCMCIA_CARD(MELCO2, LPC2_TX), 0}, 204 { PCMCIA_CARD(MITSUBISHI, B8895), NE2000DVF_ANYFUNC}, /* NG */ 205 { PCMCIA_CARD(MICRORESEARCH, MR10TPC), 0}, 206 { PCMCIA_CARD(NDC, ND5100_E), 0}, 207 { PCMCIA_CARD(NETGEAR, FA410TXC), NE2000DVF_DL100XX}, 208 /* Same ID as DLINK DFE-670TXD. 670 has DL10022, fa411 has ax88790 */ 209 { PCMCIA_CARD(NETGEAR, FA411), NE2000DVF_AX88X90 | NE2000DVF_DL100XX}, 210 { PCMCIA_CARD(NEXTCOM, NEXTHAWK), 0}, 211 { PCMCIA_CARD(NEWMEDIA, LANSURFER), NE2000DVF_ANYFUNC}, 212 { PCMCIA_CARD(NEWMEDIA, LIVEWIRE), 0}, 213 { PCMCIA_CARD(OEM2, 100BASE), NE2000DVF_AX88X90}, 214 { PCMCIA_CARD(OEM2, ETHERNET), 0}, 215 { PCMCIA_CARD(OEM2, FAST_ETHERNET), NE2000DVF_AX88X90}, 216 { PCMCIA_CARD(OEM2, NE2000), 0}, 217 { PCMCIA_CARD(PLANET, SMARTCOM2000), 0 }, 218 { PCMCIA_CARD(PREMAX, PE200), 0}, 219 { PCMCIA_CARD(PSION, LANGLOBAL), 220 NE2000DVF_ANYFUNC | NE2000DVF_AX88X90 | NE2000DVF_MODEM}, 221 { PCMCIA_CARD(RACORE, ETHERNET), 0}, 222 { PCMCIA_CARD(RACORE, FASTENET), NE2000DVF_AX88X90}, 223 { PCMCIA_CARD(RACORE, 8041TX), NE2000DVF_AX88X90 | NE2000DVF_TC5299J}, 224 { PCMCIA_CARD(RELIA, COMBO), 0}, 225 { PCMCIA_CARD(RIOS, PCCARD3), 0}, 226 { PCMCIA_CARD(RPTI, EP400), 0}, 227 { PCMCIA_CARD(RPTI, EP401), 0}, 228 { PCMCIA_CARD(SMC, EZCARD), 0}, 229 { PCMCIA_CARD(SOCKET, EA_ETHER), 0}, 230 { PCMCIA_CARD(SOCKET, ES_1000), 0}, 231 { PCMCIA_CARD(SOCKET, LP_ETHER), 0}, 232 { PCMCIA_CARD(SOCKET, LP_ETHER_CF), 0}, 233 { PCMCIA_CARD(SOCKET, LP_ETH_10_100_CF), NE2000DVF_DL100XX}, 234 { PCMCIA_CARD(SVEC, COMBOCARD), 0}, 235 { PCMCIA_CARD(SVEC, LANCARD), 0}, 236 { PCMCIA_CARD(TAMARACK, ETHERNET), 0}, 237 { PCMCIA_CARD(TDK, CFE_10), 0}, 238 { PCMCIA_CARD(TDK, LAK_CD031), 0}, 239 { PCMCIA_CARD(TDK, DFL5610WS), 0}, 240 { PCMCIA_CARD(TELECOMDEVICE, LM5LT), 0 }, 241 { PCMCIA_CARD(TELECOMDEVICE, TCD_HPC100), NE2000DVF_AX88X90}, 242 { PCMCIA_CARD(TJ, PTJ_LAN_T), 0 }, 243 { PCMCIA_CARD(TOSHIBA2, LANCT00A), NE2000DVF_ANYFUNC | NE2000DVF_TOSHIBA}, 244 { PCMCIA_CARD(ZONET, ZEN), 0}, 245 { { NULL } } 246}; 247 248/* 249 * MII bit-bang glue 250 */ 251static uint32_t ed_pccard_dl100xx_mii_bitbang_read(device_t dev); 252static void ed_pccard_dl100xx_mii_bitbang_write(device_t dev, uint32_t val); 253 254static const struct mii_bitbang_ops ed_pccard_dl100xx_mii_bitbang_ops = { 255 ed_pccard_dl100xx_mii_bitbang_read, 256 ed_pccard_dl100xx_mii_bitbang_write, 257 { 258 ED_DL100XX_MII_DATAOUT, /* MII_BIT_MDO */ 259 ED_DL100XX_MII_DATAIN, /* MII_BIT_MDI */ 260 ED_DL100XX_MII_CLK, /* MII_BIT_MDC */ 261 ED_DL100XX_MII_DIROUT, /* MII_BIT_DIR_HOST_PHY */ 262 0 /* MII_BIT_DIR_PHY_HOST */ 263 } 264}; 265 266static uint32_t ed_pccard_ax88x90_mii_bitbang_read(device_t dev); 267static void ed_pccard_ax88x90_mii_bitbang_write(device_t dev, uint32_t val); 268 269static const struct mii_bitbang_ops ed_pccard_ax88x90_mii_bitbang_ops = { 270 ed_pccard_ax88x90_mii_bitbang_read, 271 ed_pccard_ax88x90_mii_bitbang_write, 272 { 273 ED_AX88X90_MII_DATAOUT, /* MII_BIT_MDO */ 274 ED_AX88X90_MII_DATAIN, /* MII_BIT_MDI */ 275 ED_AX88X90_MII_CLK, /* MII_BIT_MDC */ 276 0, /* MII_BIT_DIR_HOST_PHY */ 277 ED_AX88X90_MII_DIRIN /* MII_BIT_DIR_PHY_HOST */ 278 } 279}; 280 281static uint32_t ed_pccard_tc5299j_mii_bitbang_read(device_t dev); 282static void ed_pccard_tc5299j_mii_bitbang_write(device_t dev, uint32_t val); 283 284static const struct mii_bitbang_ops ed_pccard_tc5299j_mii_bitbang_ops = { 285 ed_pccard_tc5299j_mii_bitbang_read, 286 ed_pccard_tc5299j_mii_bitbang_write, 287 { 288 ED_TC5299J_MII_DATAOUT, /* MII_BIT_MDO */ 289 ED_TC5299J_MII_DATAIN, /* MII_BIT_MDI */ 290 ED_TC5299J_MII_CLK, /* MII_BIT_MDC */ 291 0, /* MII_BIT_DIR_HOST_PHY */ 292 ED_AX88X90_MII_DIRIN /* MII_BIT_DIR_PHY_HOST */ 293 } 294}; 295 296/* 297 * PC Card (PCMCIA) specific code. 298 */ 299static int ed_pccard_probe(device_t); 300static int ed_pccard_attach(device_t); 301static void ed_pccard_tick(struct ed_softc *); 302 303static int ed_pccard_dl100xx(device_t dev, const struct ed_product *); 304static void ed_pccard_dl100xx_mii_reset(struct ed_softc *sc); 305 306static int ed_pccard_ax88x90(device_t dev, const struct ed_product *); 307 308static int ed_miibus_readreg(device_t dev, int phy, int reg); 309static int ed_ifmedia_upd(struct ifnet *); 310static void ed_ifmedia_sts(struct ifnet *, struct ifmediareq *); 311 312static int ed_pccard_tc5299j(device_t dev, const struct ed_product *); 313 314static void 315ed_pccard_print_entry(const struct ed_product *pp) 316{ 317 int i; 318 319 printf("Product entry: "); 320 if (pp->prod.pp_name) 321 printf("name='%s',", pp->prod.pp_name); 322 printf("vendor=%#x,product=%#x", pp->prod.pp_vendor, 323 pp->prod.pp_product); 324 for (i = 0; i < 4; i++) 325 if (pp->prod.pp_cis[i]) 326 printf(",CIS%d='%s'", i, pp->prod.pp_cis[i]); 327 printf("\n"); 328} 329 330static int 331ed_pccard_probe(device_t dev) 332{ 333 const struct ed_product *pp, *pp2; 334 int error, first = 1; 335 uint32_t fcn = PCCARD_FUNCTION_UNSPEC; 336 337 /* Make sure we're a network function */ 338 error = pccard_get_function(dev, &fcn); 339 if (error != 0) 340 return (error); 341 342 if ((pp = (const struct ed_product *) pccard_product_lookup(dev, 343 (const struct pccard_product *) ed_pccard_products, 344 sizeof(ed_pccard_products[0]), NULL)) != NULL) { 345 if (pp->prod.pp_name != NULL) 346 device_set_desc(dev, pp->prod.pp_name); 347 /* 348 * Some devices don't ID themselves as network, but 349 * that's OK if the flags say so. 350 */ 351 if (!(pp->flags & NE2000DVF_ANYFUNC) && 352 fcn != PCCARD_FUNCTION_NETWORK) 353 return (ENXIO); 354 /* 355 * Some devices match multiple entries. Report that 356 * as a warning to help cull the table 357 */ 358 pp2 = pp; 359 while ((pp2 = (const struct ed_product *)pccard_product_lookup( 360 dev, (const struct pccard_product *)(pp2 + 1), 361 sizeof(ed_pccard_products[0]), NULL)) != NULL) { 362 if (first) { 363 device_printf(dev, 364 "Warning: card matches multiple entries. Report to imp@freebsd.org\n"); 365 ed_pccard_print_entry(pp); 366 first = 0; 367 } 368 ed_pccard_print_entry(pp2); 369 } 370 371 return (0); 372 } 373 return (ENXIO); 374} 375 376static int 377ed_pccard_rom_mac(device_t dev, uint8_t *enaddr) 378{ 379 struct ed_softc *sc = device_get_softc(dev); 380 uint8_t romdata[32], sum; 381 int i; 382 383 /* 384 * Read in the rom data at location 0. Since there are no 385 * NE-1000 based PC Card devices, we'll assume we're 16-bit. 386 * 387 * In researching what format this takes, I've found that the 388 * following appears to be true for multiple cards based on 389 * observation as well as datasheet digging. 390 * 391 * Data is stored in some ROM and is copied out 8 bits at a time 392 * into 16-bit wide locations. This means that the odd locations 393 * of the ROM are not used (and can be either 0 or ff). 394 * 395 * The contents appears to be as follows: 396 * PROM RAM 397 * Offset Offset What 398 * 0 0 ENETADDR 0 399 * 1 2 ENETADDR 1 400 * 2 4 ENETADDR 2 401 * 3 6 ENETADDR 3 402 * 4 8 ENETADDR 4 403 * 5 10 ENETADDR 5 404 * 6-13 12-26 Reserved (varies by manufacturer) 405 * 14 28 0x57 406 * 15 30 0x57 407 * 408 * Some manufacturers have another image of enetaddr from 409 * PROM offset 0x10 to 0x15 with 0x42 in 0x1e and 0x1f, but 410 * this doesn't appear to be universally documented in the 411 * datasheets. Some manufactuers have a card type, card config 412 * checksums, etc encoded into PROM offset 6-13, but deciphering it 413 * requires more knowledge about the exact underlying chipset than 414 * we possess (and maybe can possess). 415 */ 416 ed_pio_readmem(sc, 0, romdata, 32); 417 if (bootverbose) 418 device_printf(dev, "ROM DATA: %32D\n", romdata, " "); 419 if (romdata[28] != 0x57 || romdata[30] != 0x57) 420 return (0); 421 for (i = 0, sum = 0; i < ETHER_ADDR_LEN; i++) 422 sum |= romdata[i * 2]; 423 if (sum == 0) 424 return (0); 425 for (i = 0; i < ETHER_ADDR_LEN; i++) 426 enaddr[i] = romdata[i * 2]; 427 return (1); 428} 429 430static int 431ed_pccard_add_modem(device_t dev) 432{ 433 device_printf(dev, "Need to write this code\n"); 434 return 0; 435} 436 437static int 438ed_pccard_kick_phy(struct ed_softc *sc) 439{ 440 struct mii_softc *miisc; 441 struct mii_data *mii; 442 443 mii = device_get_softc(sc->miibus); 444 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 445 PHY_RESET(miisc); 446 return (mii_mediachg(mii)); 447} 448 449static int 450ed_pccard_media_ioctl(struct ed_softc *sc, struct ifreq *ifr, u_long command) 451{ 452 struct mii_data *mii; 453 454 if (sc->miibus == NULL) 455 return (EINVAL); 456 mii = device_get_softc(sc->miibus); 457 return (ifmedia_ioctl(sc->ifp, ifr, &mii->mii_media, command)); 458} 459 460 461static void 462ed_pccard_mediachg(struct ed_softc *sc) 463{ 464 struct mii_data *mii; 465 466 if (sc->miibus == NULL) 467 return; 468 mii = device_get_softc(sc->miibus); 469 mii_mediachg(mii); 470} 471 472static int 473ed_pccard_attach(device_t dev) 474{ 475 u_char sum; 476 u_char enaddr[ETHER_ADDR_LEN]; 477 const struct ed_product *pp; 478 int error, i, flags, port_rid, modem_rid; 479 struct ed_softc *sc = device_get_softc(dev); 480 u_long size; 481 static uint16_t *intr_vals[] = {NULL, NULL}; 482 483 sc->dev = dev; 484 if ((pp = (const struct ed_product *) pccard_product_lookup(dev, 485 (const struct pccard_product *) ed_pccard_products, 486 sizeof(ed_pccard_products[0]), NULL)) == NULL) { 487 printf("Can't find\n"); 488 return (ENXIO); 489 } 490 modem_rid = port_rid = -1; 491 if (pp->flags & NE2000DVF_MODEM) { 492 for (i = 0; i < 4; i++) { 493 size = bus_get_resource_count(dev, SYS_RES_IOPORT, i); 494 if (size == ED_NOVELL_IO_PORTS) 495 port_rid = i; 496 else if (size == 8) 497 modem_rid = i; 498 } 499 if (port_rid == -1) { 500 device_printf(dev, "Cannot locate my ports!\n"); 501 return (ENXIO); 502 } 503 } else { 504 port_rid = 0; 505 } 506 /* Allocate the port resource during setup. */ 507 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS); 508 if (error) { 509 printf("alloc_port failed\n"); 510 return (error); 511 } 512 if (rman_get_size(sc->port_res) == ED_NOVELL_IO_PORTS / 2) { 513 port_rid++; 514 sc->port_res2 = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 515 &port_rid, RF_ACTIVE); 516 if (sc->port_res2 == NULL || 517 rman_get_size(sc->port_res2) != ED_NOVELL_IO_PORTS / 2) { 518 error = ENXIO; 519 goto bad; 520 } 521 } 522 error = ed_alloc_irq(dev, 0, 0); 523 if (error) 524 goto bad; 525 526 /* 527 * Determine which chipset we are. Almost all the PC Card chipsets 528 * have the Novel ASIC and NIC offsets. There's 2 known cards that 529 * follow the WD80x3 conventions, which are handled as a special case. 530 */ 531 sc->asic_offset = ED_NOVELL_ASIC_OFFSET; 532 sc->nic_offset = ED_NOVELL_NIC_OFFSET; 533 error = ENXIO; 534 flags = device_get_flags(dev); 535 if (error != 0) 536 error = ed_pccard_dl100xx(dev, pp); 537 if (error != 0) 538 error = ed_pccard_ax88x90(dev, pp); 539 if (error != 0) 540 error = ed_pccard_tc5299j(dev, pp); 541 if (error != 0) { 542 error = ed_probe_Novell_generic(dev, flags); 543 printf("Novell generic probe failed: %d\n", error); 544 } 545 if (error != 0 && (pp->flags & NE2000DVF_TOSHIBA)) { 546 flags |= ED_FLAGS_TOSH_ETHER; 547 flags |= ED_FLAGS_PCCARD; 548 sc->asic_offset = ED_WD_ASIC_OFFSET; 549 sc->nic_offset = ED_WD_NIC_OFFSET; 550 error = ed_probe_WD80x3_generic(dev, flags, intr_vals); 551 } 552 if (error) 553 goto bad; 554 555 /* 556 * There are several ways to get the MAC address for the card. 557 * Some of the above probe routines can fill in the enaddr. If 558 * not, we run through a number of 'well known' locations: 559 * (1) From the PC Card FUNCE 560 * (2) From offset 0 in the shared memory 561 * (3) From a hinted offset in attribute memory 562 * (4) From 0xff0 in attribute memory 563 * If we can't get a non-zero MAC address from this list, we fail. 564 */ 565 for (i = 0, sum = 0; i < ETHER_ADDR_LEN; i++) 566 sum |= sc->enaddr[i]; 567 if (sum == 0) { 568 pccard_get_ether(dev, enaddr); 569 if (bootverbose) 570 device_printf(dev, "CIS MAC %6D\n", enaddr, ":"); 571 for (i = 0, sum = 0; i < ETHER_ADDR_LEN; i++) 572 sum |= enaddr[i]; 573 if (sum == 0 && ed_pccard_rom_mac(dev, enaddr)) { 574 if (bootverbose) 575 device_printf(dev, "ROM mac %6D\n", enaddr, 576 ":"); 577 sum++; 578 } 579 if (sum == 0 && pp->flags & NE2000DVF_ENADDR) { 580 for (i = 0; i < ETHER_ADDR_LEN; i++) { 581 pccard_attr_read_1(dev, pp->enoff + i * 2, 582 enaddr + i); 583 sum |= enaddr[i]; 584 } 585 if (bootverbose) 586 device_printf(dev, "Hint %x MAC %6D\n", 587 pp->enoff, enaddr, ":"); 588 } 589 if (sum == 0) { 590 for (i = 0; i < ETHER_ADDR_LEN; i++) { 591 pccard_attr_read_1(dev, ED_DEFAULT_MAC_OFFSET + 592 i * 2, enaddr + i); 593 sum |= enaddr[i]; 594 } 595 if (bootverbose) 596 device_printf(dev, "Fallback MAC %6D\n", 597 enaddr, ":"); 598 } 599 if (sum == 0) { 600 device_printf(dev, "Cannot extract MAC address.\n"); 601 ed_release_resources(dev); 602 return (ENXIO); 603 } 604 bcopy(enaddr, sc->enaddr, ETHER_ADDR_LEN); 605 } 606 607 error = ed_attach(dev); 608 if (error) 609 goto bad; 610 if (sc->chip_type == ED_CHIP_TYPE_DL10019 || 611 sc->chip_type == ED_CHIP_TYPE_DL10022) { 612 /* Try to attach an MII bus, but ignore errors. */ 613 ed_pccard_dl100xx_mii_reset(sc); 614 (void)mii_attach(dev, &sc->miibus, sc->ifp, ed_ifmedia_upd, 615 ed_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, 616 MII_OFFSET_ANY, MIIF_FORCEANEG); 617 } else if (sc->chip_type == ED_CHIP_TYPE_AX88190 || 618 sc->chip_type == ED_CHIP_TYPE_AX88790 || 619 sc->chip_type == ED_CHIP_TYPE_TC5299J) { 620 error = mii_attach(dev, &sc->miibus, sc->ifp, ed_ifmedia_upd, 621 ed_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, 622 MII_OFFSET_ANY, MIIF_FORCEANEG); 623 if (error != 0) { 624 device_printf(dev, "attaching PHYs failed\n"); 625 goto bad; 626 } 627 } 628 if (sc->miibus != NULL) { 629 sc->sc_tick = ed_pccard_tick; 630 sc->sc_mediachg = ed_pccard_mediachg; 631 sc->sc_media_ioctl = ed_pccard_media_ioctl; 632 ed_pccard_kick_phy(sc); 633 } else { 634 ed_gen_ifmedia_init(sc); 635 } 636 if (modem_rid != -1) 637 ed_pccard_add_modem(dev); 638 639 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 640 NULL, edintr, sc, &sc->irq_handle); 641 if (error) { 642 device_printf(dev, "setup intr failed %d \n", error); 643 goto bad; 644 } 645 646 return (0); 647bad: 648 ed_detach(dev); 649 return (error); 650} 651 652/* 653 * Probe the Ethernet MAC addrees for PCMCIA Linksys EtherFast 10/100 654 * and compatible cards (DL10019C Ethernet controller). 655 */ 656static int 657ed_pccard_dl100xx(device_t dev, const struct ed_product *pp) 658{ 659 struct ed_softc *sc = device_get_softc(dev); 660 u_char sum; 661 uint8_t id; 662 u_int memsize; 663 int i, error; 664 665 if (!(pp->flags & NE2000DVF_DL100XX)) 666 return (ENXIO); 667 if (bootverbose) 668 device_printf(dev, "Trying DL100xx\n"); 669 error = ed_probe_Novell_generic(dev, device_get_flags(dev)); 670 if (bootverbose && error) 671 device_printf(dev, "Novell generic probe failed: %d\n", error); 672 if (error != 0) 673 return (error); 674 675 /* 676 * Linksys registers(offset from ASIC base) 677 * 678 * 0x04-0x09 : Physical Address Register 0-5 (PAR0-PAR5) 679 * 0x0A : Card ID Register (CIR) 680 * 0x0B : Check Sum Register (SR) 681 */ 682 for (sum = 0, i = 0x04; i < 0x0c; i++) 683 sum += ed_asic_inb(sc, i); 684 if (sum != 0xff) { 685 if (bootverbose) 686 device_printf(dev, "Bad checksum %#x\n", sum); 687 return (ENXIO); /* invalid DL10019C */ 688 } 689 if (bootverbose) 690 device_printf(dev, "CIR is %d\n", ed_asic_inb(sc, 0xa)); 691 for (i = 0; i < ETHER_ADDR_LEN; i++) 692 sc->enaddr[i] = ed_asic_inb(sc, 0x04 + i); 693 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 694 id = ed_asic_inb(sc, 0xf); 695 sc->isa16bit = 1; 696 /* 697 * Hard code values based on the datasheet. We're NE-2000 compatible 698 * NIC with 24kb of packet memory starting at 24k offset. These 699 * cards also work with 16k at 16k, but don't work with 24k at 16k 700 * or 32k at 16k. 701 */ 702 sc->type = ED_TYPE_NE2000; 703 sc->mem_start = 24 * 1024; 704 memsize = sc->mem_size = 24 * 1024; 705 sc->mem_end = sc->mem_start + memsize; 706 sc->tx_page_start = memsize / ED_PAGE_SIZE; 707 sc->txb_cnt = 3; 708 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 709 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 710 711 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 712 713 ed_nic_outb(sc, ED_P0_PSTART, sc->mem_start / ED_PAGE_SIZE); 714 ed_nic_outb(sc, ED_P0_PSTOP, sc->mem_end / ED_PAGE_SIZE); 715 sc->vendor = ED_VENDOR_NOVELL; 716 sc->chip_type = (id & 0x90) == 0x90 ? 717 ED_CHIP_TYPE_DL10022 : ED_CHIP_TYPE_DL10019; 718 sc->type_str = ((id & 0x90) == 0x90) ? "DL10022" : "DL10019"; 719 sc->mii_bitbang_ops = &ed_pccard_dl100xx_mii_bitbang_ops; 720 return (0); 721} 722 723/* MII bit-twiddling routines for cards using Dlink chipset */ 724 725static void 726ed_pccard_dl100xx_mii_reset(struct ed_softc *sc) 727{ 728 if (sc->chip_type != ED_CHIP_TYPE_DL10022) 729 return; 730 731 ed_asic_outb(sc, ED_DL100XX_MIIBUS, ED_DL10022_MII_RESET2); 732 DELAY(10); 733 ed_asic_outb(sc, ED_DL100XX_MIIBUS, 734 ED_DL10022_MII_RESET2 | ED_DL10022_MII_RESET1); 735 DELAY(10); 736 ed_asic_outb(sc, ED_DL100XX_MIIBUS, ED_DL10022_MII_RESET2); 737 DELAY(10); 738 ed_asic_outb(sc, ED_DL100XX_MIIBUS, 739 ED_DL10022_MII_RESET2 | ED_DL10022_MII_RESET1); 740 DELAY(10); 741 ed_asic_outb(sc, ED_DL100XX_MIIBUS, 0); 742} 743 744static void 745ed_pccard_dl100xx_mii_bitbang_write(device_t dev, uint32_t val) 746{ 747 struct ed_softc *sc; 748 749 sc = device_get_softc(dev); 750 751 ed_asic_outb(sc, ED_DL100XX_MIIBUS, val); 752 ed_asic_barrier(sc, ED_DL100XX_MIIBUS, 1, 753 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 754} 755 756static uint32_t 757ed_pccard_dl100xx_mii_bitbang_read(device_t dev) 758{ 759 struct ed_softc *sc; 760 uint32_t val; 761 762 sc = device_get_softc(dev); 763 764 val = ed_asic_inb(sc, ED_DL100XX_MIIBUS); 765 ed_asic_barrier(sc, ED_DL100XX_MIIBUS, 1, 766 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 767 return (val); 768} 769 770static void 771ed_pccard_ax88x90_reset(struct ed_softc *sc) 772{ 773 int i; 774 775 /* Reset Card */ 776 ed_nic_barrier(sc, ED_P0_CR, 1, 777 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 778 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP | ED_CR_PAGE_0); 779 ed_nic_barrier(sc, ED_P0_CR, 1, 780 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 781 ed_asic_outb(sc, ED_NOVELL_RESET, ed_asic_inb(sc, ED_NOVELL_RESET)); 782 783 /* Wait for the RST bit to assert, but cap it at 10ms */ 784 for (i = 10000; !(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) && i > 0; 785 i--) 786 continue; 787 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RST); /* ACK INTR */ 788 if (i == 0) 789 device_printf(sc->dev, "Reset didn't finish\n"); 790} 791 792/* 793 * Probe and vendor-specific initialization routine for ax88x90 boards 794 */ 795static int 796ed_probe_ax88x90_generic(device_t dev, int flags) 797{ 798 struct ed_softc *sc = device_get_softc(dev); 799 u_int memsize; 800 static char test_pattern[32] = "THIS is A memory TEST pattern"; 801 char test_buffer[32]; 802 803 ed_pccard_ax88x90_reset(sc); 804 DELAY(10*1000); 805 806 /* Make sure that we really have an 8390 based board */ 807 if (!ed_probe_generic8390(sc)) 808 return (ENXIO); 809 810 sc->vendor = ED_VENDOR_NOVELL; 811 sc->mem_shared = 0; 812 sc->cr_proto = ED_CR_RD2; 813 814 /* 815 * This prevents packets from being stored in the NIC memory when the 816 * readmem routine turns on the start bit in the CR. We write some 817 * bytes in word mode and verify we can read them back. If we can't 818 * then we don't have an AX88x90 chip here. 819 */ 820 sc->isa16bit = 1; 821 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON); 822 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 823 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); 824 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); 825 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) != 0) 826 return (ENXIO); 827 828 /* 829 * Hard code values based on the datasheet. We're NE-2000 compatible 830 * NIC with 16kb of packet memory starting at 16k offset. 831 */ 832 sc->type = ED_TYPE_NE2000; 833 memsize = sc->mem_size = 16*1024; 834 sc->mem_start = 16 * 1024; 835 if (ed_asic_inb(sc, ED_AX88X90_TEST) != 0) 836 sc->chip_type = ED_CHIP_TYPE_AX88790; 837 else { 838 sc->chip_type = ED_CHIP_TYPE_AX88190; 839 /* 840 * The AX88190 (not A) has external 64k SRAM. Probe for this 841 * here. Most of the cards I have either use the AX88190A 842 * part, or have only 32k SRAM for some reason, so I don't 843 * know if this works or not. 844 */ 845 ed_pio_writemem(sc, test_pattern, 32768, sizeof(test_pattern)); 846 ed_pio_readmem(sc, 32768, test_buffer, sizeof(test_pattern)); 847 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) { 848 sc->mem_start = 2*1024; 849 memsize = sc->mem_size = 62 * 1024; 850 } 851 } 852 sc->mem_end = sc->mem_start + memsize; 853 sc->tx_page_start = memsize / ED_PAGE_SIZE; 854 if (sc->mem_size > 16 * 1024) 855 sc->txb_cnt = 3; 856 else 857 sc->txb_cnt = 2; 858 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 859 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 860 861 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 862 863 ed_nic_outb(sc, ED_P0_PSTART, sc->mem_start / ED_PAGE_SIZE); 864 ed_nic_outb(sc, ED_P0_PSTOP, sc->mem_end / ED_PAGE_SIZE); 865 866 /* Get the mac before we go -- It's just at 0x400 in "SRAM" */ 867 ed_pio_readmem(sc, 0x400, sc->enaddr, ETHER_ADDR_LEN); 868 869 /* clear any pending interrupts that might have occurred above */ 870 ed_nic_outb(sc, ED_P0_ISR, 0xff); 871 sc->sc_write_mbufs = ed_pio_write_mbufs; 872 return (0); 873} 874 875static int 876ed_pccard_ax88x90_check_mii(device_t dev, struct ed_softc *sc) 877{ 878 int i, id; 879 880 /* 881 * All AX88x90 devices have MII and a PHY, so we use this to weed out 882 * chips that would otherwise make it through the tests we have after 883 * this point. 884 */ 885 for (i = 0; i < 32; i++) { 886 id = ed_miibus_readreg(dev, i, MII_BMSR); 887 if (id != 0 && id != 0xffff) 888 break; 889 } 890 /* 891 * Found one, we're good. 892 */ 893 if (i != 32) 894 return (0); 895 /* 896 * Didn't find anything, so try to power up and try again. The PHY 897 * may be not responding because we're in power down mode. 898 */ 899 if (sc->chip_type == ED_CHIP_TYPE_AX88190) 900 return (ENXIO); 901 pccard_ccr_write_1(dev, PCCARD_CCR_STATUS, PCCARD_CCR_STATUS_PWRDWN); 902 for (i = 0; i < 32; i++) { 903 id = ed_miibus_readreg(dev, i, MII_BMSR); 904 if (id != 0 && id != 0xffff) 905 break; 906 } 907 /* 908 * Still no joy? We're AFU, punt. 909 */ 910 if (i == 32) 911 return (ENXIO); 912 return (0); 913} 914 915/* 916 * Special setup for AX88[17]90 917 */ 918static int 919ed_pccard_ax88x90(device_t dev, const struct ed_product *pp) 920{ 921 int error; 922 int iobase; 923 struct ed_softc *sc = device_get_softc(dev); 924 925 if (!(pp->flags & NE2000DVF_AX88X90)) 926 return (ENXIO); 927 928 if (bootverbose) 929 device_printf(dev, "Checking AX88x90\n"); 930 931 /* 932 * Set the IOBASE Register. The AX88x90 cards are potentially 933 * multifunction cards, and thus requires a slight workaround. 934 * We write the address the card is at, on the off chance that this 935 * card is not MFC. 936 * XXX I'm not sure that this is still needed... 937 */ 938 iobase = rman_get_start(sc->port_res); 939 pccard_ccr_write_1(dev, PCCARD_CCR_IOBASE0, iobase & 0xff); 940 pccard_ccr_write_1(dev, PCCARD_CCR_IOBASE1, (iobase >> 8) & 0xff); 941 942 error = ed_probe_ax88x90_generic(dev, device_get_flags(dev)); 943 if (error) { 944 if (bootverbose) 945 device_printf(dev, "probe ax88x90 failed %d\n", 946 error); 947 return (error); 948 } 949 sc->mii_bitbang_ops = &ed_pccard_ax88x90_mii_bitbang_ops; 950 error = ed_pccard_ax88x90_check_mii(dev, sc); 951 if (error) 952 return (error); 953 sc->vendor = ED_VENDOR_NOVELL; 954 sc->type = ED_TYPE_NE2000; 955 if (sc->chip_type == ED_CHIP_TYPE_AX88190) 956 sc->type_str = "AX88190"; 957 else 958 sc->type_str = "AX88790"; 959 return (0); 960} 961 962static void 963ed_pccard_ax88x90_mii_bitbang_write(device_t dev, uint32_t val) 964{ 965 struct ed_softc *sc; 966 967 sc = device_get_softc(dev); 968 969 ed_asic_outb(sc, ED_AX88X90_MIIBUS, val); 970 ed_asic_barrier(sc, ED_AX88X90_MIIBUS, 1, 971 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 972} 973 974static uint32_t 975ed_pccard_ax88x90_mii_bitbang_read(device_t dev) 976{ 977 struct ed_softc *sc; 978 uint32_t val; 979 980 sc = device_get_softc(dev); 981 982 val = ed_asic_inb(sc, ED_AX88X90_MIIBUS); 983 ed_asic_barrier(sc, ED_AX88X90_MIIBUS, 1, 984 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 985 return (val); 986} 987 988/* 989 * Special setup for TC5299J 990 */ 991static int 992ed_pccard_tc5299j(device_t dev, const struct ed_product *pp) 993{ 994 int error, i, id; 995 char *ts; 996 struct ed_softc *sc = device_get_softc(dev); 997 998 if (!(pp->flags & NE2000DVF_TC5299J)) 999 return (ENXIO); 1000 1001 if (bootverbose) 1002 device_printf(dev, "Checking Tc5299j\n"); 1003 1004 error = ed_probe_Novell_generic(dev, device_get_flags(dev)); 1005 if (bootverbose) 1006 device_printf(dev, "Novell generic probe failed: %d\n", error); 1007 if (error != 0) 1008 return (error); 1009 1010 /* 1011 * Check to see if we have a MII PHY ID at any address. All TC5299J 1012 * devices have MII and a PHY, so we use this to weed out chips that 1013 * would otherwise make it through the tests we have after this point. 1014 */ 1015 sc->mii_bitbang_ops = &ed_pccard_tc5299j_mii_bitbang_ops; 1016 for (i = 0; i < 32; i++) { 1017 id = ed_miibus_readreg(dev, i, MII_PHYIDR1); 1018 if (id != 0 && id != 0xffff) 1019 break; 1020 } 1021 if (i == 32) 1022 return (ENXIO); 1023 ts = "TC5299J"; 1024 if (ed_pccard_rom_mac(dev, sc->enaddr) == 0) 1025 return (ENXIO); 1026 sc->vendor = ED_VENDOR_NOVELL; 1027 sc->type = ED_TYPE_NE2000; 1028 sc->chip_type = ED_CHIP_TYPE_TC5299J; 1029 sc->type_str = ts; 1030 return (0); 1031} 1032 1033static void 1034ed_pccard_tc5299j_mii_bitbang_write(device_t dev, uint32_t val) 1035{ 1036 struct ed_softc *sc; 1037 1038 sc = device_get_softc(dev); 1039 1040 /* We are already on page 3. */ 1041 ed_nic_outb(sc, ED_TC5299J_MIIBUS, val); 1042 ed_nic_barrier(sc, ED_TC5299J_MIIBUS, 1, 1043 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1044} 1045 1046static uint32_t 1047ed_pccard_tc5299j_mii_bitbang_read(device_t dev) 1048{ 1049 struct ed_softc *sc; 1050 uint32_t val; 1051 1052 sc = device_get_softc(dev); 1053 1054 /* We are already on page 3. */ 1055 val = ed_asic_inb(sc, ED_TC5299J_MIIBUS); 1056 ed_nic_barrier(sc, ED_TC5299J_MIIBUS, 1, 1057 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1058 return (val); 1059} 1060 1061/* 1062 * MII bus support routines. 1063 */ 1064static int 1065ed_miibus_readreg(device_t dev, int phy, int reg) 1066{ 1067 struct ed_softc *sc; 1068 int val; 1069 uint8_t cr = 0; 1070 1071 sc = device_get_softc(dev); 1072 /* 1073 * The AX88790 has an interesting quirk. It has an internal phy that 1074 * needs a special bit set to access, but can also have additional 1075 * external PHYs set for things like HomeNET media. When accessing 1076 * the internal PHY, a bit has to be set, when accessing the external 1077 * PHYs, it must be clear. See Errata 1, page 51, in the AX88790 1078 * datasheet for more details. 1079 * 1080 * Also, PHYs above 16 appear to be phantoms on some cards, but not 1081 * others. Registers read for this are often the same as prior values 1082 * read. Filter all register requests to 17-31. 1083 */ 1084 if (sc->chip_type == ED_CHIP_TYPE_AX88790) { 1085 if (phy > 0x10) 1086 return (0); 1087 if (phy == 0x10) 1088 ed_asic_outb(sc, ED_AX88X90_GPIO, 1089 ED_AX88X90_GPIO_INT_PHY); 1090 else 1091 ed_asic_outb(sc, ED_AX88X90_GPIO, 0); 1092 ed_asic_barrier(sc, ED_AX88X90_GPIO, 1, 1093 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1094 } else if (sc->chip_type == ED_CHIP_TYPE_TC5299J) { 1095 /* Select page 3. */ 1096 ed_nic_barrier(sc, ED_P0_CR, 1, 1097 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1098 cr = ed_nic_inb(sc, ED_P0_CR); 1099 ed_nic_outb(sc, ED_P0_CR, cr | ED_CR_PAGE_3); 1100 ed_nic_barrier(sc, ED_P0_CR, 1, 1101 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1102 } 1103 val = mii_bitbang_readreg(dev, sc->mii_bitbang_ops, phy, reg); 1104 if (sc->chip_type == ED_CHIP_TYPE_TC5299J) { 1105 /* Restore prior page. */ 1106 ed_nic_outb(sc, ED_P0_CR, cr); 1107 ed_nic_barrier(sc, ED_P0_CR, 1, 1108 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1109 } 1110 return (val); 1111} 1112 1113static int 1114ed_miibus_writereg(device_t dev, int phy, int reg, int data) 1115{ 1116 struct ed_softc *sc; 1117 uint8_t cr = 0; 1118 1119 sc = device_get_softc(dev); 1120 /* See ed_miibus_readreg for details */ 1121 if (sc->chip_type == ED_CHIP_TYPE_AX88790) { 1122 if (phy > 0x10) 1123 return (0); 1124 if (phy == 0x10) 1125 ed_asic_outb(sc, ED_AX88X90_GPIO, 1126 ED_AX88X90_GPIO_INT_PHY); 1127 else 1128 ed_asic_outb(sc, ED_AX88X90_GPIO, 0); 1129 ed_asic_barrier(sc, ED_AX88X90_GPIO, 1, 1130 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1131 } else if (sc->chip_type == ED_CHIP_TYPE_TC5299J) { 1132 /* Select page 3. */ 1133 ed_nic_barrier(sc, ED_P0_CR, 1, 1134 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1135 cr = ed_nic_inb(sc, ED_P0_CR); 1136 ed_nic_outb(sc, ED_P0_CR, cr | ED_CR_PAGE_3); 1137 ed_nic_barrier(sc, ED_P0_CR, 1, 1138 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1139 } 1140 mii_bitbang_writereg(dev, sc->mii_bitbang_ops, phy, reg, data); 1141 if (sc->chip_type == ED_CHIP_TYPE_TC5299J) { 1142 /* Restore prior page. */ 1143 ed_nic_outb(sc, ED_P0_CR, cr); 1144 ed_nic_barrier(sc, ED_P0_CR, 1, 1145 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1146 } 1147 return (0); 1148} 1149 1150static int 1151ed_ifmedia_upd(struct ifnet *ifp) 1152{ 1153 struct ed_softc *sc; 1154 int error; 1155 1156 sc = ifp->if_softc; 1157 ED_LOCK(sc); 1158 if (sc->miibus == NULL) { 1159 ED_UNLOCK(sc); 1160 return (ENXIO); 1161 } 1162 1163 error = ed_pccard_kick_phy(sc); 1164 ED_UNLOCK(sc); 1165 return (error); 1166} 1167 1168static void 1169ed_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1170{ 1171 struct ed_softc *sc; 1172 struct mii_data *mii; 1173 1174 sc = ifp->if_softc; 1175 ED_LOCK(sc); 1176 if (sc->miibus == NULL) { 1177 ED_UNLOCK(sc); 1178 return; 1179 } 1180 1181 mii = device_get_softc(sc->miibus); 1182 mii_pollstat(mii); 1183 ifmr->ifm_active = mii->mii_media_active; 1184 ifmr->ifm_status = mii->mii_media_status; 1185 ED_UNLOCK(sc); 1186} 1187 1188static void 1189ed_child_detached(device_t dev, device_t child) 1190{ 1191 struct ed_softc *sc; 1192 1193 sc = device_get_softc(dev); 1194 if (child == sc->miibus) 1195 sc->miibus = NULL; 1196} 1197 1198static void 1199ed_pccard_tick(struct ed_softc *sc) 1200{ 1201 struct mii_data *mii; 1202 int media = 0; 1203 1204 ED_ASSERT_LOCKED(sc); 1205 if (sc->miibus != NULL) { 1206 mii = device_get_softc(sc->miibus); 1207 media = mii->mii_media_status; 1208 mii_tick(mii); 1209 if (mii->mii_media_status & IFM_ACTIVE && 1210 media != mii->mii_media_status) { 1211 if (sc->chip_type == ED_CHIP_TYPE_DL10022) { 1212 ed_asic_outb(sc, ED_DL10022_DIAG, 1213 (mii->mii_media_active & IFM_FDX) ? 1214 ED_DL10022_COLLISON_DIS : 0); 1215#ifdef notyet 1216 } else if (sc->chip_type == ED_CHIP_TYPE_DL10019) { 1217 write_asic(sc, ED_DL10019_MAGIC, 1218 (mii->mii_media_active & IFM_FDX) ? 1219 DL19FDUPLX : 0); 1220#endif 1221 } 1222 } 1223 1224 } 1225} 1226 1227static device_method_t ed_pccard_methods[] = { 1228 /* Device interface */ 1229 DEVMETHOD(device_probe, ed_pccard_probe), 1230 DEVMETHOD(device_attach, ed_pccard_attach), 1231 DEVMETHOD(device_detach, ed_detach), 1232 1233 /* Bus interface */ 1234 DEVMETHOD(bus_child_detached, ed_child_detached), 1235 1236 /* MII interface */ 1237 DEVMETHOD(miibus_readreg, ed_miibus_readreg), 1238 DEVMETHOD(miibus_writereg, ed_miibus_writereg), 1239 1240 DEVMETHOD_END 1241}; 1242 1243static driver_t ed_pccard_driver = { 1244 "ed", 1245 ed_pccard_methods, 1246 sizeof(struct ed_softc) 1247}; 1248 1249DRIVER_MODULE(ed, pccard, ed_pccard_driver, ed_devclass, 0, NULL); 1250DRIVER_MODULE(miibus, ed, miibus_driver, miibus_devclass, 0, NULL); 1251MODULE_DEPEND(ed, miibus, 1, 1, 1); 1252MODULE_DEPEND(ed, ether, 1, 1, 1); 1253PCCARD_PNP_INFO(ed_pccard_products); 1254