1/* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 * 25 * $FreeBSD$ 26 */ 27#ifndef __INTEL_DRV_H__ 28#define __INTEL_DRV_H__ 29 30#include <dev/drm2/i915/i915_drm.h> 31#include <dev/drm2/i915/i915_drv.h> 32#include <dev/drm2/drm_crtc.h> 33#include <dev/drm2/drm_crtc_helper.h> 34#include <dev/drm2/drm_fb_helper.h> 35#include <dev/drm2/drm_dp_helper.h> 36 37#define _intel_wait_for(DEV, COND, MS, W, WMSG) \ 38({ \ 39 int end, ret; \ 40 \ 41 end = ticks + (MS) * hz / 1000; \ 42 ret = 0; \ 43 \ 44 while (!(COND)) { \ 45 if (time_after(ticks, end)) { \ 46 ret = -ETIMEDOUT; \ 47 break; \ 48 } \ 49 if (W) \ 50 pause((WMSG), 1); \ 51 else \ 52 DELAY(1000); \ 53 if (cold) \ 54 end -= howmany(hz, 1000); \ 55 } \ 56 \ 57 ret; \ 58}) 59 60#define _wait_for(COND, MS, W, WMSG) ({ \ 61 int timeout__ = ticks + (MS) * hz / 1000; \ 62 int ret__ = 0; \ 63 while (!(COND)) { \ 64 if (time_after(ticks, timeout__)) { \ 65 ret__ = -ETIMEDOUT; \ 66 break; \ 67 } \ 68 if (W) { \ 69 pause((WMSG), 1); \ 70 } else { \ 71 DELAY(1000); \ 72 } \ 73 if (cold) \ 74 timeout__ -= howmany(hz, 1000); \ 75 } \ 76 ret__; \ 77}) 78 79#define wait_for_atomic_us(COND, US) ({ \ 80 int i, ret__ = -ETIMEDOUT; \ 81 for (i = 0; i < (US); i++) { \ 82 if ((COND)) { \ 83 ret__ = 0; \ 84 break; \ 85 } \ 86 DELAY(1); \ 87 } \ 88 ret__; \ 89}) 90 91#define wait_for(COND, MS) _intel_wait_for(NULL, COND, MS, 1, "915wfi") 92#define wait_for_atomic(COND, MS) _intel_wait_for(NULL, COND, MS, 0, "915wfa") 93 94#define KHz(x) (1000*x) 95#define MHz(x) KHz(1000*x) 96 97/* 98 * Display related stuff 99 */ 100 101/* store information about an Ixxx DVO */ 102/* The i830->i865 use multiple DVOs with multiple i2cs */ 103/* the i915, i945 have a single sDVO i2c bus - which is different */ 104#define MAX_OUTPUTS 6 105/* maximum connectors per crtcs in the mode set */ 106#define INTELFB_CONN_LIMIT 4 107 108#define INTEL_I2C_BUS_DVO 1 109#define INTEL_I2C_BUS_SDVO 2 110 111/* these are outputs from the chip - integrated only 112 external chips are via DVO or SDVO output */ 113#define INTEL_OUTPUT_UNUSED 0 114#define INTEL_OUTPUT_ANALOG 1 115#define INTEL_OUTPUT_DVO 2 116#define INTEL_OUTPUT_SDVO 3 117#define INTEL_OUTPUT_LVDS 4 118#define INTEL_OUTPUT_TVOUT 5 119#define INTEL_OUTPUT_HDMI 6 120#define INTEL_OUTPUT_DISPLAYPORT 7 121#define INTEL_OUTPUT_EDP 8 122#define INTEL_OUTPUT_UNKNOWN 9 123 124#define INTEL_DVO_CHIP_NONE 0 125#define INTEL_DVO_CHIP_LVDS 1 126#define INTEL_DVO_CHIP_TMDS 2 127#define INTEL_DVO_CHIP_TVOUT 4 128 129/* drm_display_mode->private_flags */ 130#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0) 131#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT) 132#define INTEL_MODE_DP_FORCE_6BPC (0x10) 133/* This flag must be set by the encoder's mode_fixup if it changes the crtc 134 * timings in the mode to prevent the crtc fixup from overwriting them. 135 * Currently only lvds needs that. */ 136#define INTEL_MODE_CRTC_TIMINGS_SET (0x20) 137 138static inline void 139intel_mode_set_pixel_multiplier(struct drm_display_mode *mode, 140 int multiplier) 141{ 142 mode->clock *= multiplier; 143 mode->private_flags |= multiplier; 144} 145 146static inline int 147intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode) 148{ 149 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT; 150} 151 152struct intel_framebuffer { 153 struct drm_framebuffer base; 154 struct drm_i915_gem_object *obj; 155}; 156 157struct intel_fbdev { 158 struct drm_fb_helper helper; 159 struct intel_framebuffer ifb; 160 struct list_head fbdev_list; 161 struct drm_display_mode *our_mode; 162}; 163 164struct intel_encoder { 165 struct drm_encoder base; 166 /* 167 * The new crtc this encoder will be driven from. Only differs from 168 * base->crtc while a modeset is in progress. 169 */ 170 struct intel_crtc *new_crtc; 171 172 int type; 173 bool needs_tv_clock; 174 /* 175 * Intel hw has only one MUX where encoders could be clone, hence a 176 * simple flag is enough to compute the possible_clones mask. 177 */ 178 bool cloneable; 179 bool connectors_active; 180 void (*hot_plug)(struct intel_encoder *); 181 void (*pre_enable)(struct intel_encoder *); 182 void (*enable)(struct intel_encoder *); 183 void (*disable)(struct intel_encoder *); 184 void (*post_disable)(struct intel_encoder *); 185 /* Read out the current hw state of this connector, returning true if 186 * the encoder is active. If the encoder is enabled it also set the pipe 187 * it is connected to in the pipe parameter. */ 188 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); 189 int crtc_mask; 190}; 191 192struct intel_panel { 193 struct drm_display_mode *fixed_mode; 194 int fitting_mode; 195}; 196 197struct intel_connector { 198 struct drm_connector base; 199 /* 200 * The fixed encoder this connector is connected to. 201 */ 202 struct intel_encoder *encoder; 203 204 /* 205 * The new encoder this connector will be driven. Only differs from 206 * encoder while a modeset is in progress. 207 */ 208 struct intel_encoder *new_encoder; 209 210 /* Reads out the current hw, returning true if the connector is enabled 211 * and active (i.e. dpms ON state). */ 212 bool (*get_hw_state)(struct intel_connector *); 213 214 /* Panel info for eDP and LVDS */ 215 struct intel_panel panel; 216 217 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ 218 struct edid *edid; 219 int edid_err; 220}; 221 222struct intel_crtc { 223 struct drm_crtc base; 224 enum pipe pipe; 225 enum plane plane; 226 enum transcoder cpu_transcoder; 227 u8 lut_r[256], lut_g[256], lut_b[256]; 228 /* 229 * Whether the crtc and the connected output pipeline is active. Implies 230 * that crtc->enabled is set, i.e. the current mode configuration has 231 * some outputs connected to this crtc. 232 */ 233 bool active; 234 bool primary_disabled; /* is the crtc obscured by a plane? */ 235 bool lowfreq_avail; 236 struct intel_overlay *overlay; 237 struct intel_unpin_work *unpin_work; 238 int fdi_lanes; 239 240 atomic_t unpin_work_count; 241 242 /* Display surface base address adjustement for pageflips. Note that on 243 * gen4+ this only adjusts up to a tile, offsets within a tile are 244 * handled in the hw itself (with the TILEOFF register). */ 245 unsigned long dspaddr_offset; 246 247 struct drm_i915_gem_object *cursor_bo; 248 uint32_t cursor_addr; 249 int16_t cursor_x, cursor_y; 250 int16_t cursor_width, cursor_height; 251 bool cursor_visible; 252 unsigned int bpp; 253 254 /* We can share PLLs across outputs if the timings match */ 255 struct intel_pch_pll *pch_pll; 256 uint32_t ddi_pll_sel; 257}; 258 259struct intel_plane { 260 struct drm_plane base; 261 enum pipe pipe; 262 struct drm_i915_gem_object *obj; 263 bool can_scale; 264 int max_downscale; 265 u32 lut_r[1024], lut_g[1024], lut_b[1024]; 266 void (*update_plane)(struct drm_plane *plane, 267 struct drm_framebuffer *fb, 268 struct drm_i915_gem_object *obj, 269 int crtc_x, int crtc_y, 270 unsigned int crtc_w, unsigned int crtc_h, 271 uint32_t x, uint32_t y, 272 uint32_t src_w, uint32_t src_h); 273 void (*disable_plane)(struct drm_plane *plane); 274 int (*update_colorkey)(struct drm_plane *plane, 275 struct drm_intel_sprite_colorkey *key); 276 void (*get_colorkey)(struct drm_plane *plane, 277 struct drm_intel_sprite_colorkey *key); 278}; 279 280struct intel_watermark_params { 281 unsigned long fifo_size; 282 unsigned long max_wm; 283 unsigned long default_wm; 284 unsigned long guard_size; 285 unsigned long cacheline_size; 286}; 287 288struct cxsr_latency { 289 int is_desktop; 290 int is_ddr3; 291 unsigned long fsb_freq; 292 unsigned long mem_freq; 293 unsigned long display_sr; 294 unsigned long display_hpll_disable; 295 unsigned long cursor_sr; 296 unsigned long cursor_hpll_disable; 297}; 298 299#define to_intel_crtc(x) container_of(x, struct intel_crtc, base) 300#define to_intel_connector(x) container_of(x, struct intel_connector, base) 301#define to_intel_encoder(x) container_of(x, struct intel_encoder, base) 302#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) 303#define to_intel_plane(x) container_of(x, struct intel_plane, base) 304 305#define DIP_HEADER_SIZE 5 306 307#define DIP_TYPE_AVI 0x82 308#define DIP_VERSION_AVI 0x2 309#define DIP_LEN_AVI 13 310#define DIP_AVI_PR_1 0 311#define DIP_AVI_PR_2 1 312 313#define DIP_TYPE_SPD 0x83 314#define DIP_VERSION_SPD 0x1 315#define DIP_LEN_SPD 25 316#define DIP_SPD_UNKNOWN 0 317#define DIP_SPD_DSTB 0x1 318#define DIP_SPD_DVDP 0x2 319#define DIP_SPD_DVHS 0x3 320#define DIP_SPD_HDDVR 0x4 321#define DIP_SPD_DVC 0x5 322#define DIP_SPD_DSC 0x6 323#define DIP_SPD_VCD 0x7 324#define DIP_SPD_GAME 0x8 325#define DIP_SPD_PC 0x9 326#define DIP_SPD_BD 0xa 327#define DIP_SPD_SCD 0xb 328 329struct dip_infoframe { 330 uint8_t type; /* HB0 */ 331 uint8_t ver; /* HB1 */ 332 uint8_t len; /* HB2 - body len, not including checksum */ 333 uint8_t ecc; /* Header ECC */ 334 uint8_t checksum; /* PB0 */ 335 union { 336 struct { 337 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */ 338 uint8_t Y_A_B_S; 339 /* PB2 - C 7:6, M 5:4, R 3:0 */ 340 uint8_t C_M_R; 341 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */ 342 uint8_t ITC_EC_Q_SC; 343 /* PB4 - VIC 6:0 */ 344 uint8_t VIC; 345 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */ 346 uint8_t YQ_CN_PR; 347 /* PB6 to PB13 */ 348 uint16_t top_bar_end; 349 uint16_t bottom_bar_start; 350 uint16_t left_bar_end; 351 uint16_t right_bar_start; 352 } __attribute__ ((packed)) avi; 353 struct { 354 uint8_t vn[8]; 355 uint8_t pd[16]; 356 uint8_t sdi; 357 } __attribute__ ((packed)) spd; 358 uint8_t payload[27]; 359 } __attribute__ ((packed)) body; 360} __attribute__((packed)); 361 362struct intel_hdmi { 363 u32 sdvox_reg; 364 int ddc_bus; 365 uint32_t color_range; 366 bool has_hdmi_sink; 367 bool has_audio; 368 enum hdmi_force_audio force_audio; 369 void (*write_infoframe)(struct drm_encoder *encoder, 370 struct dip_infoframe *frame); 371 void (*set_infoframes)(struct drm_encoder *encoder, 372 struct drm_display_mode *adjusted_mode); 373}; 374 375#define DP_MAX_DOWNSTREAM_PORTS 0x10 376#define DP_LINK_CONFIGURATION_SIZE 9 377 378struct intel_dp { 379 uint32_t output_reg; 380 uint32_t DP; 381 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; 382 bool has_audio; 383 enum hdmi_force_audio force_audio; 384 uint32_t color_range; 385 uint8_t link_bw; 386 uint8_t lane_count; 387 uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; 388 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 389 device_t dp_iic_bus; 390 device_t adapter; 391 bool is_pch_edp; 392 uint8_t train_set[4]; 393 int panel_power_up_delay; 394 int panel_power_down_delay; 395 int panel_power_cycle_delay; 396 int backlight_on_delay; 397 int backlight_off_delay; 398 struct timeout_task panel_vdd_work; 399 bool want_panel_vdd; 400 struct intel_connector *attached_connector; 401}; 402 403struct intel_digital_port { 404 struct intel_encoder base; 405 enum port port; 406 u32 port_reversal; 407 struct intel_dp dp; 408 struct intel_hdmi hdmi; 409}; 410 411static inline struct drm_crtc * 412intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) 413{ 414 struct drm_i915_private *dev_priv = dev->dev_private; 415 return dev_priv->pipe_to_crtc_mapping[pipe]; 416} 417 418static inline struct drm_crtc * 419intel_get_crtc_for_plane(struct drm_device *dev, int plane) 420{ 421 struct drm_i915_private *dev_priv = dev->dev_private; 422 return dev_priv->plane_to_crtc_mapping[plane]; 423} 424 425struct intel_unpin_work { 426 struct task work; 427 struct drm_crtc *crtc; 428 struct drm_i915_gem_object *old_fb_obj; 429 struct drm_i915_gem_object *pending_flip_obj; 430 struct drm_pending_vblank_event *event; 431 atomic_t pending; 432#define INTEL_FLIP_INACTIVE 0 433#define INTEL_FLIP_PENDING 1 434#define INTEL_FLIP_COMPLETE 2 435 bool enable_stall_check; 436}; 437 438struct intel_fbc_work { 439 struct timeout_task work; 440 struct drm_crtc *crtc; 441 struct drm_framebuffer *fb; 442 int interval; 443}; 444 445int intel_pch_rawclk(struct drm_device *dev); 446 447int intel_connector_update_modes(struct drm_connector *connector, 448 struct edid *edid); 449int intel_ddc_get_modes(struct drm_connector *c, device_t adapter); 450 451extern void intel_attach_force_audio_property(struct drm_connector *connector); 452extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector); 453 454extern void intel_crt_init(struct drm_device *dev); 455extern void intel_hdmi_init(struct drm_device *dev, 456 int sdvox_reg, enum port port); 457extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 458 struct intel_connector *intel_connector); 459extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); 460extern bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, 461 const struct drm_display_mode *mode, 462 struct drm_display_mode *adjusted_mode); 463extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if); 464extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, 465 bool is_sdvob); 466extern void intel_dvo_init(struct drm_device *dev); 467extern void intel_tv_init(struct drm_device *dev); 468extern void intel_mark_busy(struct drm_device *dev); 469extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj); 470extern void intel_mark_idle(struct drm_device *dev); 471extern bool intel_lvds_init(struct drm_device *dev); 472extern void intel_dp_init(struct drm_device *dev, int output_reg, 473 enum port port); 474extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 475 struct intel_connector *intel_connector); 476void 477intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 478 struct drm_display_mode *adjusted_mode); 479extern void intel_dp_init_link_config(struct intel_dp *intel_dp); 480extern void intel_dp_start_link_train(struct intel_dp *intel_dp); 481extern void intel_dp_complete_link_train(struct intel_dp *intel_dp); 482extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); 483extern void intel_dp_encoder_destroy(struct drm_encoder *encoder); 484extern void intel_dp_check_link_status(struct intel_dp *intel_dp); 485extern bool intel_dp_mode_fixup(struct drm_encoder *encoder, 486 const struct drm_display_mode *mode, 487 struct drm_display_mode *adjusted_mode); 488extern bool intel_dpd_is_edp(struct drm_device *dev); 489extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp); 490extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp); 491extern void ironlake_edp_panel_on(struct intel_dp *intel_dp); 492extern void ironlake_edp_panel_off(struct intel_dp *intel_dp); 493extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); 494extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 495extern void intel_edp_link_config(struct intel_encoder *, int *, int *); 496extern int intel_edp_target_clock(struct intel_encoder *, 497 struct drm_display_mode *mode); 498extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder); 499extern int intel_plane_init(struct drm_device *dev, enum pipe pipe); 500extern void intel_flush_display_plane(struct drm_i915_private *dev_priv, 501 enum plane plane); 502 503/* intel_panel.c */ 504extern int intel_panel_init(struct intel_panel *panel, 505 struct drm_display_mode *fixed_mode); 506extern void intel_panel_fini(struct intel_panel *panel); 507 508extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, 509 struct drm_display_mode *adjusted_mode); 510extern void intel_pch_panel_fitting(struct drm_device *dev, 511 int fitting_mode, 512 const struct drm_display_mode *mode, 513 struct drm_display_mode *adjusted_mode); 514extern u32 intel_panel_get_max_backlight(struct drm_device *dev); 515extern void intel_panel_set_backlight(struct drm_device *dev, u32 level); 516extern int intel_panel_setup_backlight(struct drm_connector *connector); 517extern void intel_panel_enable_backlight(struct drm_device *dev, 518 enum pipe pipe); 519extern void intel_panel_disable_backlight(struct drm_device *dev); 520extern void intel_panel_destroy_backlight(struct drm_device *dev); 521extern enum drm_connector_status intel_panel_detect(struct drm_device *dev); 522 523struct intel_set_config { 524 struct drm_encoder **save_connector_encoders; 525 struct drm_crtc **save_encoder_crtcs; 526 527 bool fb_changed; 528 bool mode_changed; 529}; 530 531extern bool intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, 532 int x, int y, struct drm_framebuffer *old_fb); 533extern void intel_modeset_disable(struct drm_device *dev); 534extern void intel_crtc_load_lut(struct drm_crtc *crtc); 535extern void intel_crtc_update_dpms(struct drm_crtc *crtc); 536extern void intel_encoder_noop(struct drm_encoder *encoder); 537extern void intel_encoder_destroy(struct drm_encoder *encoder); 538extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode); 539extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder); 540extern void intel_connector_dpms(struct drm_connector *, int mode); 541extern bool intel_connector_get_hw_state(struct intel_connector *connector); 542extern void intel_modeset_check_state(struct drm_device *dev); 543 544 545static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) 546{ 547 return to_intel_connector(connector)->encoder; 548} 549 550static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) 551{ 552 struct intel_digital_port *intel_dig_port = 553 container_of(encoder, struct intel_digital_port, base.base); 554 return &intel_dig_port->dp; 555} 556 557static inline struct intel_digital_port * 558enc_to_dig_port(struct drm_encoder *encoder) 559{ 560 return container_of(encoder, struct intel_digital_port, base.base); 561} 562 563static inline struct intel_digital_port * 564dp_to_dig_port(struct intel_dp *intel_dp) 565{ 566 return container_of(intel_dp, struct intel_digital_port, dp); 567} 568 569static inline struct intel_digital_port * 570hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) 571{ 572 return container_of(intel_hdmi, struct intel_digital_port, hdmi); 573} 574 575extern void intel_connector_attach_encoder(struct intel_connector *connector, 576 struct intel_encoder *encoder); 577extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector); 578 579extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, 580 struct drm_crtc *crtc); 581int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 582 struct drm_file *file_priv); 583extern enum transcoder 584intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 585 enum pipe pipe); 586extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); 587extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); 588extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); 589 590struct intel_load_detect_pipe { 591 struct drm_framebuffer *release_fb; 592 bool load_detect_temp; 593 int dpms_mode; 594}; 595extern bool intel_get_load_detect_pipe(struct drm_connector *connector, 596 struct drm_display_mode *mode, 597 struct intel_load_detect_pipe *old); 598extern void intel_release_load_detect_pipe(struct drm_connector *connector, 599 struct intel_load_detect_pipe *old); 600 601extern void intelfb_restore(void); 602extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 603 u16 blue, int regno); 604extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 605 u16 *blue, int regno); 606extern void intel_enable_clock_gating(struct drm_device *dev); 607 608extern int intel_pin_and_fence_fb_obj(struct drm_device *dev, 609 struct drm_i915_gem_object *obj, 610 struct intel_ring_buffer *pipelined); 611extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); 612 613extern int intel_framebuffer_init(struct drm_device *dev, 614 struct intel_framebuffer *ifb, 615 struct drm_mode_fb_cmd2 *mode_cmd, 616 struct drm_i915_gem_object *obj); 617extern int intel_fbdev_init(struct drm_device *dev); 618extern void intel_fbdev_fini(struct drm_device *dev); 619extern void intel_fbdev_set_suspend(struct drm_device *dev, int state); 620extern void intel_prepare_page_flip(struct drm_device *dev, int plane); 621extern void intel_finish_page_flip(struct drm_device *dev, int pipe); 622extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane); 623 624extern void intel_setup_overlay(struct drm_device *dev); 625extern void intel_cleanup_overlay(struct drm_device *dev); 626extern int intel_overlay_switch_off(struct intel_overlay *overlay); 627extern int intel_overlay_put_image(struct drm_device *dev, void *data, 628 struct drm_file *file_priv); 629extern int intel_overlay_attrs(struct drm_device *dev, void *data, 630 struct drm_file *file_priv); 631 632extern void intel_fb_output_poll_changed(struct drm_device *dev); 633extern void intel_fb_restore_mode(struct drm_device *dev); 634 635extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, 636 bool state); 637#define assert_pipe_enabled(d, p) assert_pipe(d, p, true) 638#define assert_pipe_disabled(d, p) assert_pipe(d, p, false) 639 640extern void intel_init_clock_gating(struct drm_device *dev); 641extern void intel_write_eld(struct drm_encoder *encoder, 642 struct drm_display_mode *mode); 643extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); 644extern void intel_prepare_ddi(struct drm_device *dev); 645extern void hsw_fdi_link_train(struct drm_crtc *crtc); 646extern void intel_ddi_init(struct drm_device *dev, enum port port); 647 648/* For use by IVB LP watermark workaround in intel_sprite.c */ 649extern void intel_update_watermarks(struct drm_device *dev); 650extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, 651 uint32_t sprite_width, 652 int pixel_size); 653extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe, 654 struct drm_display_mode *mode); 655 656extern unsigned long intel_gen4_compute_page_offset(int *x, int *y, 657 unsigned int tiling_mode, 658 unsigned int bpp, 659 unsigned int pitch); 660 661extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, 662 struct drm_file *file_priv); 663extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data, 664 struct drm_file *file_priv); 665 666extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg); 667 668/* Power-related functions, located in intel_pm.c */ 669extern void intel_init_pm(struct drm_device *dev); 670/* FBC */ 671extern bool intel_fbc_enabled(struct drm_device *dev); 672extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); 673extern void intel_update_fbc(struct drm_device *dev); 674/* IPS */ 675extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv); 676extern void intel_gpu_ips_teardown(void); 677 678extern void intel_init_power_wells(struct drm_device *dev); 679extern void intel_enable_gt_powersave(struct drm_device *dev); 680extern void intel_disable_gt_powersave(struct drm_device *dev); 681extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv); 682extern void ironlake_teardown_rc6(struct drm_device *dev); 683 684extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 685 enum pipe *pipe); 686extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); 687extern void intel_ddi_pll_init(struct drm_device *dev); 688extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc); 689extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 690 enum transcoder cpu_transcoder); 691extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); 692extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); 693extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev); 694extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock); 695extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); 696extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); 697extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); 698extern bool 699intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); 700extern void intel_ddi_fdi_disable(struct drm_crtc *crtc); 701 702#endif /* __INTEL_DRV_H__ */ 703