1/* 2 * Copyright �� 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD$"); 30 31#include <dev/drm2/drmP.h> 32#include <dev/drm2/i915/i915_drv.h> 33#include <dev/drm2/i915/intel_drv.h> 34 35/* HDMI/DVI modes ignore everything but the last 2 items. So we share 36 * them for both DP and FDI transports, allowing those ports to 37 * automatically adapt to HDMI connections as well 38 */ 39static const u32 hsw_ddi_translations_dp[] = { 40 0x00FFFFFF, 0x0006000E, /* DP parameters */ 41 0x00D75FFF, 0x0005000A, 42 0x00C30FFF, 0x00040006, 43 0x80AAAFFF, 0x000B0000, 44 0x00FFFFFF, 0x0005000A, 45 0x00D75FFF, 0x000C0004, 46 0x80C30FFF, 0x000B0000, 47 0x00FFFFFF, 0x00040006, 48 0x80D75FFF, 0x000B0000, 49 0x00FFFFFF, 0x00040006 /* HDMI parameters */ 50}; 51 52static const u32 hsw_ddi_translations_fdi[] = { 53 0x00FFFFFF, 0x0007000E, /* FDI parameters */ 54 0x00D75FFF, 0x000F000A, 55 0x00C30FFF, 0x00060006, 56 0x00AAAFFF, 0x001E0000, 57 0x00FFFFFF, 0x000F000A, 58 0x00D75FFF, 0x00160004, 59 0x00C30FFF, 0x001E0000, 60 0x00FFFFFF, 0x00060006, 61 0x00D75FFF, 0x001E0000, 62 0x00FFFFFF, 0x00040006 /* HDMI parameters */ 63}; 64 65static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) 66{ 67 struct drm_encoder *encoder = &intel_encoder->base; 68 int type = intel_encoder->type; 69 70 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || 71 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { 72 struct intel_digital_port *intel_dig_port = 73 enc_to_dig_port(encoder); 74 return intel_dig_port->port; 75 76 } else if (type == INTEL_OUTPUT_ANALOG) { 77 return PORT_E; 78 79 } else { 80 DRM_ERROR("Invalid DDI encoder type %d\n", type); 81 BUG(); 82 } 83} 84 85/* On Haswell, DDI port buffers must be programmed with correct values 86 * in advance. The buffer values are different for FDI and DP modes, 87 * but the HDMI/DVI fields are shared among those. So we program the DDI 88 * in either FDI or DP modes only, as HDMI connections will work with both 89 * of those 90 */ 91static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, bool use_fdi_mode) 92{ 93 struct drm_i915_private *dev_priv = dev->dev_private; 94 u32 reg; 95 int i; 96 const u32 *ddi_translations = ((use_fdi_mode) ? 97 hsw_ddi_translations_fdi : 98 hsw_ddi_translations_dp); 99 100 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n", 101 port_name(port), 102 use_fdi_mode ? "FDI" : "DP"); 103 104 WARN((use_fdi_mode && (port != PORT_E)), 105 "Programming port %c in FDI mode, this probably will not work.\n", 106 port_name(port)); 107 108 for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { 109 I915_WRITE(reg, ddi_translations[i]); 110 reg += 4; 111 } 112} 113 114/* Program DDI buffers translations for DP. By default, program ports A-D in DP 115 * mode and port E for FDI. 116 */ 117void intel_prepare_ddi(struct drm_device *dev) 118{ 119 int port; 120 121 if (IS_HASWELL(dev)) { 122 for (port = PORT_A; port < PORT_E; port++) 123 intel_prepare_ddi_buffers(dev, port, false); 124 125 /* DDI E is the suggested one to work in FDI mode, so program is as such by 126 * default. It will have to be re-programmed in case a digital DP output 127 * will be detected on it 128 */ 129 intel_prepare_ddi_buffers(dev, PORT_E, true); 130 } 131} 132 133static const long hsw_ddi_buf_ctl_values[] = { 134 DDI_BUF_EMP_400MV_0DB_HSW, 135 DDI_BUF_EMP_400MV_3_5DB_HSW, 136 DDI_BUF_EMP_400MV_6DB_HSW, 137 DDI_BUF_EMP_400MV_9_5DB_HSW, 138 DDI_BUF_EMP_600MV_0DB_HSW, 139 DDI_BUF_EMP_600MV_3_5DB_HSW, 140 DDI_BUF_EMP_600MV_6DB_HSW, 141 DDI_BUF_EMP_800MV_0DB_HSW, 142 DDI_BUF_EMP_800MV_3_5DB_HSW 143}; 144 145static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 146 enum port port) 147{ 148 uint32_t reg = DDI_BUF_CTL(port); 149 int i; 150 151 for (i = 0; i < 8; i++) { 152 udelay(1); 153 if (I915_READ(reg) & DDI_BUF_IS_IDLE) 154 return; 155 } 156 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); 157} 158 159/* Starting with Haswell, different DDI ports can work in FDI mode for 160 * connection to the PCH-located connectors. For this, it is necessary to train 161 * both the DDI port and PCH receiver for the desired DDI buffer settings. 162 * 163 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 164 * please note that when FDI mode is active on DDI E, it shares 2 lines with 165 * DDI A (which is used for eDP) 166 */ 167 168void hsw_fdi_link_train(struct drm_crtc *crtc) 169{ 170 struct drm_device *dev = crtc->dev; 171 struct drm_i915_private *dev_priv = dev->dev_private; 172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 173 u32 temp, i, rx_ctl_val; 174 175 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 176 * mode set "sequence for CRT port" document: 177 * - TP1 to TP2 time with the default value 178 * - FDI delay to 90h 179 */ 180 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | 181 FDI_RX_PWRDN_LANE0_VAL(2) | 182 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 183 184 /* Enable the PCH Receiver FDI PLL */ 185 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 186 FDI_RX_PLL_ENABLE | ((intel_crtc->fdi_lanes - 1) << 19); 187 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 188 POSTING_READ(_FDI_RXA_CTL); 189 udelay(220); 190 191 /* Switch from Rawclk to PCDclk */ 192 rx_ctl_val |= FDI_PCDCLK; 193 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 194 195 /* Configure Port Clock Select */ 196 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel); 197 198 /* Start the training iterating through available voltages and emphasis, 199 * testing each value twice. */ 200 for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) { 201 /* Configure DP_TP_CTL with auto-training */ 202 I915_WRITE(DP_TP_CTL(PORT_E), 203 DP_TP_CTL_FDI_AUTOTRAIN | 204 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 205 DP_TP_CTL_LINK_TRAIN_PAT1 | 206 DP_TP_CTL_ENABLE); 207 208 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 209 * DDI E does not support port reversal, the functionality is 210 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 211 * port reversal bit */ 212 I915_WRITE(DDI_BUF_CTL(PORT_E), 213 DDI_BUF_CTL_ENABLE | 214 ((intel_crtc->fdi_lanes - 1) << 1) | 215 hsw_ddi_buf_ctl_values[i / 2]); 216 POSTING_READ(DDI_BUF_CTL(PORT_E)); 217 218 udelay(600); 219 220 /* Program PCH FDI Receiver TU */ 221 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); 222 223 /* Enable PCH FDI Receiver with auto-training */ 224 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 225 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 226 POSTING_READ(_FDI_RXA_CTL); 227 228 /* Wait for FDI receiver lane calibration */ 229 udelay(30); 230 231 /* Unset FDI_RX_MISC pwrdn lanes */ 232 temp = I915_READ(_FDI_RXA_MISC); 233 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 234 I915_WRITE(_FDI_RXA_MISC, temp); 235 POSTING_READ(_FDI_RXA_MISC); 236 237 /* Wait for FDI auto training time */ 238 udelay(5); 239 240 temp = I915_READ(DP_TP_STATUS(PORT_E)); 241 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 242 DRM_DEBUG_KMS("FDI link training done on step %d\n", i); 243 244 /* Enable normal pixel sending for FDI */ 245 I915_WRITE(DP_TP_CTL(PORT_E), 246 DP_TP_CTL_FDI_AUTOTRAIN | 247 DP_TP_CTL_LINK_TRAIN_NORMAL | 248 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 249 DP_TP_CTL_ENABLE); 250 251 return; 252 } 253 254 temp = I915_READ(DDI_BUF_CTL(PORT_E)); 255 temp &= ~DDI_BUF_CTL_ENABLE; 256 I915_WRITE(DDI_BUF_CTL(PORT_E), temp); 257 POSTING_READ(DDI_BUF_CTL(PORT_E)); 258 259 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 260 temp = I915_READ(DP_TP_CTL(PORT_E)); 261 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 262 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 263 I915_WRITE(DP_TP_CTL(PORT_E), temp); 264 POSTING_READ(DP_TP_CTL(PORT_E)); 265 266 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 267 268 rx_ctl_val &= ~FDI_RX_ENABLE; 269 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 270 POSTING_READ(_FDI_RXA_CTL); 271 272 /* Reset FDI_RX_MISC pwrdn lanes */ 273 temp = I915_READ(_FDI_RXA_MISC); 274 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 275 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 276 I915_WRITE(_FDI_RXA_MISC, temp); 277 POSTING_READ(_FDI_RXA_MISC); 278 } 279 280 DRM_ERROR("FDI link training failed!\n"); 281} 282 283/* WRPLL clock dividers */ 284struct wrpll_tmds_clock { 285 u32 clock; 286 u16 p; /* Post divider */ 287 u16 n2; /* Feedback divider */ 288 u16 r2; /* Reference divider */ 289}; 290 291/* Table of matching values for WRPLL clocks programming for each frequency. 292 * The code assumes this table is sorted. */ 293static const struct wrpll_tmds_clock wrpll_tmds_clock_table[] = { 294 {19750, 38, 25, 18}, 295 {20000, 48, 32, 18}, 296 {21000, 36, 21, 15}, 297 {21912, 42, 29, 17}, 298 {22000, 36, 22, 15}, 299 {23000, 36, 23, 15}, 300 {23500, 40, 40, 23}, 301 {23750, 26, 16, 14}, 302 {24000, 36, 24, 15}, 303 {25000, 36, 25, 15}, 304 {25175, 26, 40, 33}, 305 {25200, 30, 21, 15}, 306 {26000, 36, 26, 15}, 307 {27000, 30, 21, 14}, 308 {27027, 18, 100, 111}, 309 {27500, 30, 29, 19}, 310 {28000, 34, 30, 17}, 311 {28320, 26, 30, 22}, 312 {28322, 32, 42, 25}, 313 {28750, 24, 23, 18}, 314 {29000, 30, 29, 18}, 315 {29750, 32, 30, 17}, 316 {30000, 30, 25, 15}, 317 {30750, 30, 41, 24}, 318 {31000, 30, 31, 18}, 319 {31500, 30, 28, 16}, 320 {32000, 30, 32, 18}, 321 {32500, 28, 32, 19}, 322 {33000, 24, 22, 15}, 323 {34000, 28, 30, 17}, 324 {35000, 26, 32, 19}, 325 {35500, 24, 30, 19}, 326 {36000, 26, 26, 15}, 327 {36750, 26, 46, 26}, 328 {37000, 24, 23, 14}, 329 {37762, 22, 40, 26}, 330 {37800, 20, 21, 15}, 331 {38000, 24, 27, 16}, 332 {38250, 24, 34, 20}, 333 {39000, 24, 26, 15}, 334 {40000, 24, 32, 18}, 335 {40500, 20, 21, 14}, 336 {40541, 22, 147, 89}, 337 {40750, 18, 19, 14}, 338 {41000, 16, 17, 14}, 339 {41500, 22, 44, 26}, 340 {41540, 22, 44, 26}, 341 {42000, 18, 21, 15}, 342 {42500, 22, 45, 26}, 343 {43000, 20, 43, 27}, 344 {43163, 20, 24, 15}, 345 {44000, 18, 22, 15}, 346 {44900, 20, 108, 65}, 347 {45000, 20, 25, 15}, 348 {45250, 20, 52, 31}, 349 {46000, 18, 23, 15}, 350 {46750, 20, 45, 26}, 351 {47000, 20, 40, 23}, 352 {48000, 18, 24, 15}, 353 {49000, 18, 49, 30}, 354 {49500, 16, 22, 15}, 355 {50000, 18, 25, 15}, 356 {50500, 18, 32, 19}, 357 {51000, 18, 34, 20}, 358 {52000, 18, 26, 15}, 359 {52406, 14, 34, 25}, 360 {53000, 16, 22, 14}, 361 {54000, 16, 24, 15}, 362 {54054, 16, 173, 108}, 363 {54500, 14, 24, 17}, 364 {55000, 12, 22, 18}, 365 {56000, 14, 45, 31}, 366 {56250, 16, 25, 15}, 367 {56750, 14, 25, 17}, 368 {57000, 16, 27, 16}, 369 {58000, 16, 43, 25}, 370 {58250, 16, 38, 22}, 371 {58750, 16, 40, 23}, 372 {59000, 14, 26, 17}, 373 {59341, 14, 40, 26}, 374 {59400, 16, 44, 25}, 375 {60000, 16, 32, 18}, 376 {60500, 12, 39, 29}, 377 {61000, 14, 49, 31}, 378 {62000, 14, 37, 23}, 379 {62250, 14, 42, 26}, 380 {63000, 12, 21, 15}, 381 {63500, 14, 28, 17}, 382 {64000, 12, 27, 19}, 383 {65000, 14, 32, 19}, 384 {65250, 12, 29, 20}, 385 {65500, 12, 32, 22}, 386 {66000, 12, 22, 15}, 387 {66667, 14, 38, 22}, 388 {66750, 10, 21, 17}, 389 {67000, 14, 33, 19}, 390 {67750, 14, 58, 33}, 391 {68000, 14, 30, 17}, 392 {68179, 14, 46, 26}, 393 {68250, 14, 46, 26}, 394 {69000, 12, 23, 15}, 395 {70000, 12, 28, 18}, 396 {71000, 12, 30, 19}, 397 {72000, 12, 24, 15}, 398 {73000, 10, 23, 17}, 399 {74000, 12, 23, 14}, 400 {74176, 8, 100, 91}, 401 {74250, 10, 22, 16}, 402 {74481, 12, 43, 26}, 403 {74500, 10, 29, 21}, 404 {75000, 12, 25, 15}, 405 {75250, 10, 39, 28}, 406 {76000, 12, 27, 16}, 407 {77000, 12, 53, 31}, 408 {78000, 12, 26, 15}, 409 {78750, 12, 28, 16}, 410 {79000, 10, 38, 26}, 411 {79500, 10, 28, 19}, 412 {80000, 12, 32, 18}, 413 {81000, 10, 21, 14}, 414 {81081, 6, 100, 111}, 415 {81624, 8, 29, 24}, 416 {82000, 8, 17, 14}, 417 {83000, 10, 40, 26}, 418 {83950, 10, 28, 18}, 419 {84000, 10, 28, 18}, 420 {84750, 6, 16, 17}, 421 {85000, 6, 17, 18}, 422 {85250, 10, 30, 19}, 423 {85750, 10, 27, 17}, 424 {86000, 10, 43, 27}, 425 {87000, 10, 29, 18}, 426 {88000, 10, 44, 27}, 427 {88500, 10, 41, 25}, 428 {89000, 10, 28, 17}, 429 {89012, 6, 90, 91}, 430 {89100, 10, 33, 20}, 431 {90000, 10, 25, 15}, 432 {91000, 10, 32, 19}, 433 {92000, 10, 46, 27}, 434 {93000, 10, 31, 18}, 435 {94000, 10, 40, 23}, 436 {94500, 10, 28, 16}, 437 {95000, 10, 44, 25}, 438 {95654, 10, 39, 22}, 439 {95750, 10, 39, 22}, 440 {96000, 10, 32, 18}, 441 {97000, 8, 23, 16}, 442 {97750, 8, 42, 29}, 443 {98000, 8, 45, 31}, 444 {99000, 8, 22, 15}, 445 {99750, 8, 34, 23}, 446 {100000, 6, 20, 18}, 447 {100500, 6, 19, 17}, 448 {101000, 6, 37, 33}, 449 {101250, 8, 21, 14}, 450 {102000, 6, 17, 15}, 451 {102250, 6, 25, 22}, 452 {103000, 8, 29, 19}, 453 {104000, 8, 37, 24}, 454 {105000, 8, 28, 18}, 455 {106000, 8, 22, 14}, 456 {107000, 8, 46, 29}, 457 {107214, 8, 27, 17}, 458 {108000, 8, 24, 15}, 459 {108108, 8, 173, 108}, 460 {109000, 6, 23, 19}, 461 {110000, 6, 22, 18}, 462 {110013, 6, 22, 18}, 463 {110250, 8, 49, 30}, 464 {110500, 8, 36, 22}, 465 {111000, 8, 23, 14}, 466 {111264, 8, 150, 91}, 467 {111375, 8, 33, 20}, 468 {112000, 8, 63, 38}, 469 {112500, 8, 25, 15}, 470 {113100, 8, 57, 34}, 471 {113309, 8, 42, 25}, 472 {114000, 8, 27, 16}, 473 {115000, 6, 23, 18}, 474 {116000, 8, 43, 25}, 475 {117000, 8, 26, 15}, 476 {117500, 8, 40, 23}, 477 {118000, 6, 38, 29}, 478 {119000, 8, 30, 17}, 479 {119500, 8, 46, 26}, 480 {119651, 8, 39, 22}, 481 {120000, 8, 32, 18}, 482 {121000, 6, 39, 29}, 483 {121250, 6, 31, 23}, 484 {121750, 6, 23, 17}, 485 {122000, 6, 42, 31}, 486 {122614, 6, 30, 22}, 487 {123000, 6, 41, 30}, 488 {123379, 6, 37, 27}, 489 {124000, 6, 51, 37}, 490 {125000, 6, 25, 18}, 491 {125250, 4, 13, 14}, 492 {125750, 4, 27, 29}, 493 {126000, 6, 21, 15}, 494 {127000, 6, 24, 17}, 495 {127250, 6, 41, 29}, 496 {128000, 6, 27, 19}, 497 {129000, 6, 43, 30}, 498 {129859, 4, 25, 26}, 499 {130000, 6, 26, 18}, 500 {130250, 6, 42, 29}, 501 {131000, 6, 32, 22}, 502 {131500, 6, 38, 26}, 503 {131850, 6, 41, 28}, 504 {132000, 6, 22, 15}, 505 {132750, 6, 28, 19}, 506 {133000, 6, 34, 23}, 507 {133330, 6, 37, 25}, 508 {134000, 6, 61, 41}, 509 {135000, 6, 21, 14}, 510 {135250, 6, 167, 111}, 511 {136000, 6, 62, 41}, 512 {137000, 6, 35, 23}, 513 {138000, 6, 23, 15}, 514 {138500, 6, 40, 26}, 515 {138750, 6, 37, 24}, 516 {139000, 6, 34, 22}, 517 {139050, 6, 34, 22}, 518 {139054, 6, 34, 22}, 519 {140000, 6, 28, 18}, 520 {141000, 6, 36, 23}, 521 {141500, 6, 22, 14}, 522 {142000, 6, 30, 19}, 523 {143000, 6, 27, 17}, 524 {143472, 4, 17, 16}, 525 {144000, 6, 24, 15}, 526 {145000, 6, 29, 18}, 527 {146000, 6, 47, 29}, 528 {146250, 6, 26, 16}, 529 {147000, 6, 49, 30}, 530 {147891, 6, 23, 14}, 531 {148000, 6, 23, 14}, 532 {148250, 6, 28, 17}, 533 {148352, 4, 100, 91}, 534 {148500, 6, 33, 20}, 535 {149000, 6, 48, 29}, 536 {150000, 6, 25, 15}, 537 {151000, 4, 19, 17}, 538 {152000, 6, 27, 16}, 539 {152280, 6, 44, 26}, 540 {153000, 6, 34, 20}, 541 {154000, 6, 53, 31}, 542 {155000, 6, 31, 18}, 543 {155250, 6, 50, 29}, 544 {155750, 6, 45, 26}, 545 {156000, 6, 26, 15}, 546 {157000, 6, 61, 35}, 547 {157500, 6, 28, 16}, 548 {158000, 6, 65, 37}, 549 {158250, 6, 44, 25}, 550 {159000, 6, 53, 30}, 551 {159500, 6, 39, 22}, 552 {160000, 6, 32, 18}, 553 {161000, 4, 31, 26}, 554 {162000, 4, 18, 15}, 555 {162162, 4, 131, 109}, 556 {162500, 4, 53, 44}, 557 {163000, 4, 29, 24}, 558 {164000, 4, 17, 14}, 559 {165000, 4, 22, 18}, 560 {166000, 4, 32, 26}, 561 {167000, 4, 26, 21}, 562 {168000, 4, 46, 37}, 563 {169000, 4, 104, 83}, 564 {169128, 4, 64, 51}, 565 {169500, 4, 39, 31}, 566 {170000, 4, 34, 27}, 567 {171000, 4, 19, 15}, 568 {172000, 4, 51, 40}, 569 {172750, 4, 32, 25}, 570 {172800, 4, 32, 25}, 571 {173000, 4, 41, 32}, 572 {174000, 4, 49, 38}, 573 {174787, 4, 22, 17}, 574 {175000, 4, 35, 27}, 575 {176000, 4, 30, 23}, 576 {177000, 4, 38, 29}, 577 {178000, 4, 29, 22}, 578 {178500, 4, 37, 28}, 579 {179000, 4, 53, 40}, 580 {179500, 4, 73, 55}, 581 {180000, 4, 20, 15}, 582 {181000, 4, 55, 41}, 583 {182000, 4, 31, 23}, 584 {183000, 4, 42, 31}, 585 {184000, 4, 30, 22}, 586 {184750, 4, 26, 19}, 587 {185000, 4, 37, 27}, 588 {186000, 4, 51, 37}, 589 {187000, 4, 36, 26}, 590 {188000, 4, 32, 23}, 591 {189000, 4, 21, 15}, 592 {190000, 4, 38, 27}, 593 {190960, 4, 41, 29}, 594 {191000, 4, 41, 29}, 595 {192000, 4, 27, 19}, 596 {192250, 4, 37, 26}, 597 {193000, 4, 20, 14}, 598 {193250, 4, 53, 37}, 599 {194000, 4, 23, 16}, 600 {194208, 4, 23, 16}, 601 {195000, 4, 26, 18}, 602 {196000, 4, 45, 31}, 603 {197000, 4, 35, 24}, 604 {197750, 4, 41, 28}, 605 {198000, 4, 22, 15}, 606 {198500, 4, 25, 17}, 607 {199000, 4, 28, 19}, 608 {200000, 4, 37, 25}, 609 {201000, 4, 61, 41}, 610 {202000, 4, 112, 75}, 611 {202500, 4, 21, 14}, 612 {203000, 4, 146, 97}, 613 {204000, 4, 62, 41}, 614 {204750, 4, 44, 29}, 615 {205000, 4, 38, 25}, 616 {206000, 4, 29, 19}, 617 {207000, 4, 23, 15}, 618 {207500, 4, 40, 26}, 619 {208000, 4, 37, 24}, 620 {208900, 4, 48, 31}, 621 {209000, 4, 48, 31}, 622 {209250, 4, 31, 20}, 623 {210000, 4, 28, 18}, 624 {211000, 4, 25, 16}, 625 {212000, 4, 22, 14}, 626 {213000, 4, 30, 19}, 627 {213750, 4, 38, 24}, 628 {214000, 4, 46, 29}, 629 {214750, 4, 35, 22}, 630 {215000, 4, 43, 27}, 631 {216000, 4, 24, 15}, 632 {217000, 4, 37, 23}, 633 {218000, 4, 42, 26}, 634 {218250, 4, 42, 26}, 635 {218750, 4, 34, 21}, 636 {219000, 4, 47, 29}, 637 {220000, 4, 44, 27}, 638 {220640, 4, 49, 30}, 639 {220750, 4, 36, 22}, 640 {221000, 4, 36, 22}, 641 {222000, 4, 23, 14}, 642 {222525, 4, 28, 17}, 643 {222750, 4, 33, 20}, 644 {227000, 4, 37, 22}, 645 {230250, 4, 29, 17}, 646 {233500, 4, 38, 22}, 647 {235000, 4, 40, 23}, 648 {238000, 4, 30, 17}, 649 {241500, 2, 17, 19}, 650 {245250, 2, 20, 22}, 651 {247750, 2, 22, 24}, 652 {253250, 2, 15, 16}, 653 {256250, 2, 18, 19}, 654 {262500, 2, 31, 32}, 655 {267250, 2, 66, 67}, 656 {268500, 2, 94, 95}, 657 {270000, 2, 14, 14}, 658 {272500, 2, 77, 76}, 659 {273750, 2, 57, 56}, 660 {280750, 2, 24, 23}, 661 {281250, 2, 23, 22}, 662 {286000, 2, 17, 16}, 663 {291750, 2, 26, 24}, 664 {296703, 2, 56, 51}, 665 {297000, 2, 22, 20}, 666 {298000, 2, 21, 19}, 667}; 668 669static void intel_ddi_mode_set(struct drm_encoder *encoder, 670 struct drm_display_mode *mode, 671 struct drm_display_mode *adjusted_mode) 672{ 673 struct drm_crtc *crtc = encoder->crtc; 674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 675 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 676 int port = intel_ddi_get_encoder_port(intel_encoder); 677 int pipe = intel_crtc->pipe; 678 int type = intel_encoder->type; 679 680 DRM_DEBUG_KMS("Preparing DDI mode for Haswell on port %c, pipe %c\n", 681 port_name(port), pipe_name(pipe)); 682 683 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 684 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 685 struct intel_digital_port *intel_dig_port = 686 enc_to_dig_port(encoder); 687 688 intel_dp->DP = intel_dig_port->port_reversal | 689 DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW; 690 switch (intel_dp->lane_count) { 691 case 1: 692 intel_dp->DP |= DDI_PORT_WIDTH_X1; 693 break; 694 case 2: 695 intel_dp->DP |= DDI_PORT_WIDTH_X2; 696 break; 697 case 4: 698 intel_dp->DP |= DDI_PORT_WIDTH_X4; 699 break; 700 default: 701 intel_dp->DP |= DDI_PORT_WIDTH_X4; 702 WARN(1, "Unexpected DP lane count %d\n", 703 intel_dp->lane_count); 704 break; 705 } 706 707 if (intel_dp->has_audio) { 708 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n", 709 pipe_name(intel_crtc->pipe)); 710 711 /* write eld */ 712 DRM_DEBUG_DRIVER("DP audio: write eld information\n"); 713 intel_write_eld(encoder, adjusted_mode); 714 } 715 716 intel_dp_init_link_config(intel_dp); 717 718 } else if (type == INTEL_OUTPUT_HDMI) { 719 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 720 721 if (intel_hdmi->has_audio) { 722 /* Proper support for digital audio needs a new logic 723 * and a new set of registers, so we leave it for future 724 * patch bombing. 725 */ 726 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n", 727 pipe_name(intel_crtc->pipe)); 728 729 /* write eld */ 730 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n"); 731 intel_write_eld(encoder, adjusted_mode); 732 } 733 734 intel_hdmi->set_infoframes(encoder, adjusted_mode); 735 } 736} 737 738static struct intel_encoder * 739intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) 740{ 741 struct drm_device *dev = crtc->dev; 742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 743 struct intel_encoder *intel_encoder, *ret = NULL; 744 int num_encoders = 0; 745 746 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 747 ret = intel_encoder; 748 num_encoders++; 749 } 750 751 if (num_encoders != 1) 752 WARN(1, "%d encoders on crtc for pipe %d\n", num_encoders, 753 intel_crtc->pipe); 754 755 BUG_ON(ret == NULL); 756 return ret; 757} 758 759void intel_ddi_put_crtc_pll(struct drm_crtc *crtc) 760{ 761 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 762 struct intel_ddi_plls *plls = &dev_priv->ddi_plls; 763 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 764 uint32_t val; 765 766 switch (intel_crtc->ddi_pll_sel) { 767 case PORT_CLK_SEL_SPLL: 768 plls->spll_refcount--; 769 if (plls->spll_refcount == 0) { 770 DRM_DEBUG_KMS("Disabling SPLL\n"); 771 val = I915_READ(SPLL_CTL); 772 WARN_ON(!(val & SPLL_PLL_ENABLE)); 773 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); 774 POSTING_READ(SPLL_CTL); 775 } 776 break; 777 case PORT_CLK_SEL_WRPLL1: 778 plls->wrpll1_refcount--; 779 if (plls->wrpll1_refcount == 0) { 780 DRM_DEBUG_KMS("Disabling WRPLL 1\n"); 781 val = I915_READ(WRPLL_CTL1); 782 WARN_ON(!(val & WRPLL_PLL_ENABLE)); 783 I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE); 784 POSTING_READ(WRPLL_CTL1); 785 } 786 break; 787 case PORT_CLK_SEL_WRPLL2: 788 plls->wrpll2_refcount--; 789 if (plls->wrpll2_refcount == 0) { 790 DRM_DEBUG_KMS("Disabling WRPLL 2\n"); 791 val = I915_READ(WRPLL_CTL2); 792 WARN_ON(!(val & WRPLL_PLL_ENABLE)); 793 I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE); 794 POSTING_READ(WRPLL_CTL2); 795 } 796 break; 797 } 798 799 WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n"); 800 WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n"); 801 WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n"); 802 803 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE; 804} 805 806static void intel_ddi_calculate_wrpll(int clock, int *p, int *n2, int *r2) 807{ 808 u32 i; 809 810 for (i = 0; i < ARRAY_SIZE(wrpll_tmds_clock_table); i++) 811 if (clock <= wrpll_tmds_clock_table[i].clock) 812 break; 813 814 if (i == ARRAY_SIZE(wrpll_tmds_clock_table)) 815 i--; 816 817 *p = wrpll_tmds_clock_table[i].p; 818 *n2 = wrpll_tmds_clock_table[i].n2; 819 *r2 = wrpll_tmds_clock_table[i].r2; 820 821 if (wrpll_tmds_clock_table[i].clock != clock) 822 DRM_INFO("WRPLL: using settings for %dKHz on %dKHz mode\n", 823 wrpll_tmds_clock_table[i].clock, clock); 824 825 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n", 826 clock, *p, *n2, *r2); 827} 828 829bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock) 830{ 831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 832 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 833 struct drm_encoder *encoder = &intel_encoder->base; 834 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 835 struct intel_ddi_plls *plls = &dev_priv->ddi_plls; 836 int type = intel_encoder->type; 837 enum pipe pipe = intel_crtc->pipe; 838 uint32_t reg, val; 839 840 /* TODO: reuse PLLs when possible (compare values) */ 841 842 intel_ddi_put_crtc_pll(crtc); 843 844 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 845 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 846 847 switch (intel_dp->link_bw) { 848 case DP_LINK_BW_1_62: 849 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; 850 break; 851 case DP_LINK_BW_2_7: 852 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; 853 break; 854 case DP_LINK_BW_5_4: 855 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; 856 break; 857 default: 858 DRM_ERROR("Link bandwidth %d unsupported\n", 859 intel_dp->link_bw); 860 return false; 861 } 862 863 /* We don't need to turn any PLL on because we'll use LCPLL. */ 864 return true; 865 866 } else if (type == INTEL_OUTPUT_HDMI) { 867 int p, n2, r2; 868 869 if (plls->wrpll1_refcount == 0) { 870 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n", 871 pipe_name(pipe)); 872 plls->wrpll1_refcount++; 873 reg = WRPLL_CTL1; 874 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1; 875 } else if (plls->wrpll2_refcount == 0) { 876 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n", 877 pipe_name(pipe)); 878 plls->wrpll2_refcount++; 879 reg = WRPLL_CTL2; 880 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2; 881 } else { 882 DRM_ERROR("No WRPLLs available!\n"); 883 return false; 884 } 885 886 WARN(I915_READ(reg) & WRPLL_PLL_ENABLE, 887 "WRPLL already enabled\n"); 888 889 intel_ddi_calculate_wrpll(clock, &p, &n2, &r2); 890 891 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 | 892 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | 893 WRPLL_DIVIDER_POST(p); 894 895 } else if (type == INTEL_OUTPUT_ANALOG) { 896 if (plls->spll_refcount == 0) { 897 DRM_DEBUG_KMS("Using SPLL on pipe %c\n", 898 pipe_name(pipe)); 899 plls->spll_refcount++; 900 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL; 901 } 902 reg = SPLL_CTL; 903 904 WARN(I915_READ(reg) & SPLL_PLL_ENABLE, 905 "SPLL already enabled\n"); 906 907 val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC; 908 909 } else { 910 WARN(1, "Invalid DDI encoder type %d\n", type); 911 return false; 912 } 913 914 I915_WRITE(reg, val); 915 udelay(20); 916 917 return true; 918} 919 920void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) 921{ 922 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 924 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 925 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; 926 int type = intel_encoder->type; 927 uint32_t temp; 928 929 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 930 931 temp = TRANS_MSA_SYNC_CLK; 932 switch (intel_crtc->bpp) { 933 case 18: 934 temp |= TRANS_MSA_6_BPC; 935 break; 936 case 24: 937 temp |= TRANS_MSA_8_BPC; 938 break; 939 case 30: 940 temp |= TRANS_MSA_10_BPC; 941 break; 942 case 36: 943 temp |= TRANS_MSA_12_BPC; 944 break; 945 default: 946 temp |= TRANS_MSA_8_BPC; 947 WARN(1, "%d bpp unsupported by DDI function\n", 948 intel_crtc->bpp); 949 } 950 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); 951 } 952} 953 954void intel_ddi_enable_pipe_func(struct drm_crtc *crtc) 955{ 956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 957 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 958 struct drm_encoder *encoder = &intel_encoder->base; 959 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 960 enum pipe pipe = intel_crtc->pipe; 961 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; 962 enum port port = intel_ddi_get_encoder_port(intel_encoder); 963 int type = intel_encoder->type; 964 uint32_t temp; 965 966 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 967 temp = TRANS_DDI_FUNC_ENABLE; 968 temp |= TRANS_DDI_SELECT_PORT(port); 969 970 switch (intel_crtc->bpp) { 971 case 18: 972 temp |= TRANS_DDI_BPC_6; 973 break; 974 case 24: 975 temp |= TRANS_DDI_BPC_8; 976 break; 977 case 30: 978 temp |= TRANS_DDI_BPC_10; 979 break; 980 case 36: 981 temp |= TRANS_DDI_BPC_12; 982 break; 983 default: 984 WARN(1, "%d bpp unsupported by transcoder DDI function\n", 985 intel_crtc->bpp); 986 } 987 988 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) 989 temp |= TRANS_DDI_PVSYNC; 990 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) 991 temp |= TRANS_DDI_PHSYNC; 992 993 if (cpu_transcoder == TRANSCODER_EDP) { 994 switch (pipe) { 995 case PIPE_A: 996 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 997 break; 998 case PIPE_B: 999 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1000 break; 1001 case PIPE_C: 1002 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1003 break; 1004 default: 1005 BUG(); 1006 break; 1007 } 1008 } 1009 1010 if (type == INTEL_OUTPUT_HDMI) { 1011 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1012 1013 if (intel_hdmi->has_hdmi_sink) 1014 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1015 else 1016 temp |= TRANS_DDI_MODE_SELECT_DVI; 1017 1018 } else if (type == INTEL_OUTPUT_ANALOG) { 1019 temp |= TRANS_DDI_MODE_SELECT_FDI; 1020 temp |= (intel_crtc->fdi_lanes - 1) << 1; 1021 1022 } else if (type == INTEL_OUTPUT_DISPLAYPORT || 1023 type == INTEL_OUTPUT_EDP) { 1024 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1025 1026 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1027 1028 switch (intel_dp->lane_count) { 1029 case 1: 1030 temp |= TRANS_DDI_PORT_WIDTH_X1; 1031 break; 1032 case 2: 1033 temp |= TRANS_DDI_PORT_WIDTH_X2; 1034 break; 1035 case 4: 1036 temp |= TRANS_DDI_PORT_WIDTH_X4; 1037 break; 1038 default: 1039 temp |= TRANS_DDI_PORT_WIDTH_X4; 1040 WARN(1, "Unsupported lane count %d\n", 1041 intel_dp->lane_count); 1042 } 1043 1044 } else { 1045 WARN(1, "Invalid encoder type %d for pipe %d\n", 1046 intel_encoder->type, pipe); 1047 } 1048 1049 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1050} 1051 1052void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 1053 enum transcoder cpu_transcoder) 1054{ 1055 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); 1056 uint32_t val = I915_READ(reg); 1057 1058 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK); 1059 val |= TRANS_DDI_PORT_NONE; 1060 I915_WRITE(reg, val); 1061} 1062 1063bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1064{ 1065 struct drm_device *dev = intel_connector->base.dev; 1066 struct drm_i915_private *dev_priv = dev->dev_private; 1067 struct intel_encoder *intel_encoder = intel_connector->encoder; 1068 int type = intel_connector->base.connector_type; 1069 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1070 enum pipe pipe = 0; 1071 enum transcoder cpu_transcoder; 1072 uint32_t tmp; 1073 1074 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) 1075 return false; 1076 1077 if (port == PORT_A) 1078 cpu_transcoder = TRANSCODER_EDP; 1079 else 1080 cpu_transcoder = (enum transcoder)pipe; 1081 1082 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1083 1084 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 1085 case TRANS_DDI_MODE_SELECT_HDMI: 1086 case TRANS_DDI_MODE_SELECT_DVI: 1087 return (type == DRM_MODE_CONNECTOR_HDMIA); 1088 1089 case TRANS_DDI_MODE_SELECT_DP_SST: 1090 if (type == DRM_MODE_CONNECTOR_eDP) 1091 return true; 1092 case TRANS_DDI_MODE_SELECT_DP_MST: 1093 return (type == DRM_MODE_CONNECTOR_DisplayPort); 1094 1095 case TRANS_DDI_MODE_SELECT_FDI: 1096 return (type == DRM_MODE_CONNECTOR_VGA); 1097 1098 default: 1099 return false; 1100 } 1101} 1102 1103bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 1104 enum pipe *pipe) 1105{ 1106 struct drm_device *dev = encoder->base.dev; 1107 struct drm_i915_private *dev_priv = dev->dev_private; 1108 enum port port = intel_ddi_get_encoder_port(encoder); 1109 u32 tmp; 1110 int i; 1111 1112 tmp = I915_READ(DDI_BUF_CTL(port)); 1113 1114 if (!(tmp & DDI_BUF_CTL_ENABLE)) 1115 return false; 1116 1117 if (port == PORT_A) { 1118 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 1119 1120 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1121 case TRANS_DDI_EDP_INPUT_A_ON: 1122 case TRANS_DDI_EDP_INPUT_A_ONOFF: 1123 *pipe = PIPE_A; 1124 break; 1125 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1126 *pipe = PIPE_B; 1127 break; 1128 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1129 *pipe = PIPE_C; 1130 break; 1131 } 1132 1133 return true; 1134 } else { 1135 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { 1136 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); 1137 1138 if ((tmp & TRANS_DDI_PORT_MASK) 1139 == TRANS_DDI_SELECT_PORT(port)) { 1140 *pipe = i; 1141 return true; 1142 } 1143 } 1144 } 1145 1146 DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port); 1147 1148 return true; 1149} 1150 1151static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv, 1152 enum pipe pipe) 1153{ 1154 uint32_t temp, ret; 1155 enum port port; 1156 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 1157 pipe); 1158 int i; 1159 1160 if (cpu_transcoder == TRANSCODER_EDP) { 1161 port = PORT_A; 1162 } else { 1163 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1164 temp &= TRANS_DDI_PORT_MASK; 1165 1166 for (i = PORT_B; i <= PORT_E; i++) 1167 if (temp == TRANS_DDI_SELECT_PORT(i)) 1168 port = i; 1169 } 1170 1171 ret = I915_READ(PORT_CLK_SEL(port)); 1172 1173 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock 0x%08x\n", 1174 pipe_name(pipe), port_name(port), ret); 1175 1176 return ret; 1177} 1178 1179void intel_ddi_setup_hw_pll_state(struct drm_device *dev) 1180{ 1181 struct drm_i915_private *dev_priv = dev->dev_private; 1182 enum pipe pipe; 1183 struct intel_crtc *intel_crtc; 1184 1185 for_each_pipe(pipe) { 1186 intel_crtc = 1187 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 1188 1189 if (!intel_crtc->active) 1190 continue; 1191 1192 intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv, 1193 pipe); 1194 1195 switch (intel_crtc->ddi_pll_sel) { 1196 case PORT_CLK_SEL_SPLL: 1197 dev_priv->ddi_plls.spll_refcount++; 1198 break; 1199 case PORT_CLK_SEL_WRPLL1: 1200 dev_priv->ddi_plls.wrpll1_refcount++; 1201 break; 1202 case PORT_CLK_SEL_WRPLL2: 1203 dev_priv->ddi_plls.wrpll2_refcount++; 1204 break; 1205 } 1206 } 1207} 1208 1209void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) 1210{ 1211 struct drm_crtc *crtc = &intel_crtc->base; 1212 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 1213 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1214 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1215 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; 1216 1217 if (cpu_transcoder != TRANSCODER_EDP) 1218 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 1219 TRANS_CLK_SEL_PORT(port)); 1220} 1221 1222void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) 1223{ 1224 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 1225 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; 1226 1227 if (cpu_transcoder != TRANSCODER_EDP) 1228 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 1229 TRANS_CLK_SEL_DISABLED); 1230} 1231 1232static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) 1233{ 1234 struct drm_encoder *encoder = &intel_encoder->base; 1235 struct drm_crtc *crtc = encoder->crtc; 1236 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 1237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1238 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1239 int type = intel_encoder->type; 1240 1241 if (type == INTEL_OUTPUT_EDP) { 1242 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1243 ironlake_edp_panel_vdd_on(intel_dp); 1244 ironlake_edp_panel_on(intel_dp); 1245 ironlake_edp_panel_vdd_off(intel_dp, true); 1246 } 1247 1248 WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE); 1249 I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel); 1250 1251 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 1252 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1253 1254 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1255 intel_dp_start_link_train(intel_dp); 1256 intel_dp_complete_link_train(intel_dp); 1257 } 1258} 1259 1260static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) 1261{ 1262 struct drm_encoder *encoder = &intel_encoder->base; 1263 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 1264 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1265 int type = intel_encoder->type; 1266 uint32_t val; 1267 bool wait = false; 1268 1269 val = I915_READ(DDI_BUF_CTL(port)); 1270 if (val & DDI_BUF_CTL_ENABLE) { 1271 val &= ~DDI_BUF_CTL_ENABLE; 1272 I915_WRITE(DDI_BUF_CTL(port), val); 1273 wait = true; 1274 } 1275 1276 val = I915_READ(DP_TP_CTL(port)); 1277 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1278 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 1279 I915_WRITE(DP_TP_CTL(port), val); 1280 1281 if (wait) 1282 intel_wait_ddi_buf_idle(dev_priv, port); 1283 1284 if (type == INTEL_OUTPUT_EDP) { 1285 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1286 ironlake_edp_panel_vdd_on(intel_dp); 1287 ironlake_edp_panel_off(intel_dp); 1288 } 1289 1290 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1291} 1292 1293static void intel_enable_ddi(struct intel_encoder *intel_encoder) 1294{ 1295 struct drm_encoder *encoder = &intel_encoder->base; 1296 struct drm_device *dev = encoder->dev; 1297 struct drm_i915_private *dev_priv = dev->dev_private; 1298 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1299 int type = intel_encoder->type; 1300 1301 if (type == INTEL_OUTPUT_HDMI) { 1302 struct intel_digital_port *intel_dig_port = 1303 enc_to_dig_port(encoder); 1304 1305 /* In HDMI/DVI mode, the port width, and swing/emphasis values 1306 * are ignored so nothing special needs to be done besides 1307 * enabling the port. 1308 */ 1309 I915_WRITE(DDI_BUF_CTL(port), 1310 intel_dig_port->port_reversal | DDI_BUF_CTL_ENABLE); 1311 } else if (type == INTEL_OUTPUT_EDP) { 1312 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1313 1314 ironlake_edp_backlight_on(intel_dp); 1315 } 1316} 1317 1318static void intel_disable_ddi(struct intel_encoder *intel_encoder) 1319{ 1320 struct drm_encoder *encoder = &intel_encoder->base; 1321 int type = intel_encoder->type; 1322 1323 if (type == INTEL_OUTPUT_EDP) { 1324 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1325 1326 ironlake_edp_backlight_off(intel_dp); 1327 } 1328} 1329 1330int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) 1331{ 1332 if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) 1333 return 450; 1334 else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) == 1335 LCPLL_CLK_FREQ_450) 1336 return 450; 1337 else if (IS_ULT(dev_priv->dev)) 1338 return 338; 1339 else 1340 return 540; 1341} 1342 1343void intel_ddi_pll_init(struct drm_device *dev) 1344{ 1345 struct drm_i915_private *dev_priv = dev->dev_private; 1346 uint32_t val = I915_READ(LCPLL_CTL); 1347 1348 /* The LCPLL register should be turned on by the BIOS. For now let's 1349 * just check its state and print errors in case something is wrong. 1350 * Don't even try to turn it on. 1351 */ 1352 1353 DRM_DEBUG_KMS("CDCLK running at %dMHz\n", 1354 intel_ddi_get_cdclk_freq(dev_priv)); 1355 1356 if (val & LCPLL_CD_SOURCE_FCLK) 1357 DRM_ERROR("CDCLK source is not LCPLL\n"); 1358 1359 if (val & LCPLL_PLL_DISABLE) 1360 DRM_ERROR("LCPLL is disabled\n"); 1361} 1362 1363void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) 1364{ 1365 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 1366 struct intel_dp *intel_dp = &intel_dig_port->dp; 1367 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 1368 enum port port = intel_dig_port->port; 1369 bool wait = false; 1370 uint32_t val; 1371 1372 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { 1373 val = I915_READ(DDI_BUF_CTL(port)); 1374 if (val & DDI_BUF_CTL_ENABLE) { 1375 val &= ~DDI_BUF_CTL_ENABLE; 1376 I915_WRITE(DDI_BUF_CTL(port), val); 1377 wait = true; 1378 } 1379 1380 val = I915_READ(DP_TP_CTL(port)); 1381 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1382 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 1383 I915_WRITE(DP_TP_CTL(port), val); 1384 POSTING_READ(DP_TP_CTL(port)); 1385 1386 if (wait) 1387 intel_wait_ddi_buf_idle(dev_priv, port); 1388 } 1389 1390 val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST | 1391 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 1392 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) 1393 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 1394 I915_WRITE(DP_TP_CTL(port), val); 1395 POSTING_READ(DP_TP_CTL(port)); 1396 1397 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 1398 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); 1399 POSTING_READ(DDI_BUF_CTL(port)); 1400 1401 udelay(600); 1402} 1403 1404void intel_ddi_fdi_disable(struct drm_crtc *crtc) 1405{ 1406 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 1407 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1408 uint32_t val; 1409 1410 intel_ddi_post_disable(intel_encoder); 1411 1412 val = I915_READ(_FDI_RXA_CTL); 1413 val &= ~FDI_RX_ENABLE; 1414 I915_WRITE(_FDI_RXA_CTL, val); 1415 1416 val = I915_READ(_FDI_RXA_MISC); 1417 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1418 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 1419 I915_WRITE(_FDI_RXA_MISC, val); 1420 1421 val = I915_READ(_FDI_RXA_CTL); 1422 val &= ~FDI_PCDCLK; 1423 I915_WRITE(_FDI_RXA_CTL, val); 1424 1425 val = I915_READ(_FDI_RXA_CTL); 1426 val &= ~FDI_RX_PLL_ENABLE; 1427 I915_WRITE(_FDI_RXA_CTL, val); 1428} 1429 1430static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder) 1431{ 1432 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 1433 int type = intel_encoder->type; 1434 1435 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) 1436 intel_dp_check_link_status(intel_dp); 1437} 1438 1439static void intel_ddi_destroy(struct drm_encoder *encoder) 1440{ 1441 /* HDMI has nothing special to destroy, so we can go with this. */ 1442 intel_dp_encoder_destroy(encoder); 1443} 1444 1445static bool intel_ddi_mode_fixup(struct drm_encoder *encoder, 1446 const struct drm_display_mode *mode, 1447 struct drm_display_mode *adjusted_mode) 1448{ 1449 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 1450 int type = intel_encoder->type; 1451 1452 WARN(type == INTEL_OUTPUT_UNKNOWN, "mode_fixup() on unknown output!\n"); 1453 1454 if (type == INTEL_OUTPUT_HDMI) 1455 return intel_hdmi_mode_fixup(encoder, mode, adjusted_mode); 1456 else 1457 return intel_dp_mode_fixup(encoder, mode, adjusted_mode); 1458} 1459 1460static const struct drm_encoder_funcs intel_ddi_funcs = { 1461 .destroy = intel_ddi_destroy, 1462}; 1463 1464static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs = { 1465 .mode_fixup = intel_ddi_mode_fixup, 1466 .mode_set = intel_ddi_mode_set, 1467 .disable = intel_encoder_noop, 1468}; 1469 1470void intel_ddi_init(struct drm_device *dev, enum port port) 1471{ 1472 struct drm_i915_private *dev_priv = dev->dev_private; 1473 struct intel_digital_port *intel_dig_port; 1474 struct intel_encoder *intel_encoder; 1475 struct drm_encoder *encoder; 1476 struct intel_connector *hdmi_connector = NULL; 1477 struct intel_connector *dp_connector = NULL; 1478 1479 intel_dig_port = malloc(sizeof(struct intel_digital_port), DRM_MEM_KMS, M_WAITOK | M_ZERO); 1480 if (!intel_dig_port) 1481 return; 1482 1483 dp_connector = malloc(sizeof(struct intel_connector), DRM_MEM_KMS, M_WAITOK | M_ZERO); 1484 if (!dp_connector) { 1485 free(intel_dig_port, DRM_MEM_KMS); 1486 return; 1487 } 1488 1489 if (port != PORT_A) { 1490 hdmi_connector = malloc(sizeof(struct intel_connector), 1491 DRM_MEM_KMS, M_WAITOK | M_ZERO); 1492 if (!hdmi_connector) { 1493 free(dp_connector, DRM_MEM_KMS); 1494 free(intel_dig_port, DRM_MEM_KMS); 1495 return; 1496 } 1497 } 1498 1499 intel_encoder = &intel_dig_port->base; 1500 encoder = &intel_encoder->base; 1501 1502 drm_encoder_init(dev, encoder, &intel_ddi_funcs, 1503 DRM_MODE_ENCODER_TMDS); 1504 drm_encoder_helper_add(encoder, &intel_ddi_helper_funcs); 1505 1506 intel_encoder->enable = intel_enable_ddi; 1507 intel_encoder->pre_enable = intel_ddi_pre_enable; 1508 intel_encoder->disable = intel_disable_ddi; 1509 intel_encoder->post_disable = intel_ddi_post_disable; 1510 intel_encoder->get_hw_state = intel_ddi_get_hw_state; 1511 1512 intel_dig_port->port = port; 1513 intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) & 1514 DDI_BUF_PORT_REVERSAL; 1515 if (hdmi_connector) 1516 intel_dig_port->hdmi.sdvox_reg = DDI_BUF_CTL(port); 1517 else 1518 intel_dig_port->hdmi.sdvox_reg = 0; 1519 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 1520 1521 intel_encoder->type = INTEL_OUTPUT_UNKNOWN; 1522 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 1523 intel_encoder->cloneable = false; 1524 intel_encoder->hot_plug = intel_ddi_hot_plug; 1525 1526 if (hdmi_connector) 1527 intel_hdmi_init_connector(intel_dig_port, hdmi_connector); 1528 intel_dp_init_connector(intel_dig_port, dp_connector); 1529} 1530