1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33#ifndef __T4_IOCTL_H__ 34#define __T4_IOCTL_H__ 35 36#include <sys/types.h> 37#include <net/ethernet.h> 38#include <net/bpf.h> 39 40/* 41 * Ioctl commands specific to this driver. 42 */ 43enum { 44 T4_GETREG = 0x40, /* read register */ 45 T4_SETREG, /* write register */ 46 T4_REGDUMP, /* dump of all registers */ 47 T4_GET_FILTER_MODE, /* get global filter mode */ 48 T4_SET_FILTER_MODE, /* set global filter mode */ 49 T4_GET_FILTER, /* get information about a filter */ 50 T4_SET_FILTER, /* program a filter */ 51 T4_DEL_FILTER, /* delete a filter */ 52 T4_GET_SGE_CONTEXT, /* get SGE context for a queue */ 53 T4_LOAD_FW, /* flash firmware */ 54 T4_GET_MEM, /* read memory */ 55 T4_GET_I2C, /* read from i2c addressible device */ 56 T4_CLEAR_STATS, /* clear a port's MAC statistics */ 57 T4_SET_OFLD_POLICY, /* Set offload policy */ 58 T4_SET_SCHED_CLASS, /* set sched class */ 59 T4_SET_SCHED_QUEUE, /* set queue class */ 60 T4_GET_TRACER, /* get information about a tracer */ 61 T4_SET_TRACER, /* program a tracer */ 62 T4_LOAD_CFG, /* copy a config file to card's flash */ 63 T4_LOAD_BOOT, /* flash boot rom */ 64 T4_LOAD_BOOTCFG, /* flash bootcfg */ 65 T4_CUDBG_DUMP, /* debug dump of chip state */ 66}; 67 68struct t4_reg { 69 uint32_t addr; 70 uint32_t size; 71 uint64_t val; 72}; 73 74#define T4_REGDUMP_SIZE (160 * 1024) 75#define T5_REGDUMP_SIZE (332 * 1024) 76struct t4_regdump { 77 uint32_t version; 78 uint32_t len; /* bytes */ 79 uint32_t *data; 80}; 81 82struct t4_data { 83 uint32_t len; 84 uint8_t *data; 85}; 86 87struct t4_bootrom { 88 uint32_t pf_offset; 89 uint32_t pfidx_addr; 90 uint32_t len; 91 uint8_t *data; 92}; 93 94struct t4_i2c_data { 95 uint8_t port_id; 96 uint8_t dev_addr; 97 uint8_t offset; 98 uint8_t len; 99 uint8_t data[8]; 100}; 101 102/* 103 * A hardware filter is some valid combination of these. 104 */ 105#define T4_FILTER_IPv4 0x1 /* IPv4 packet */ 106#define T4_FILTER_IPv6 0x2 /* IPv6 packet */ 107#define T4_FILTER_IP_SADDR 0x4 /* Source IP address or network */ 108#define T4_FILTER_IP_DADDR 0x8 /* Destination IP address or network */ 109#define T4_FILTER_IP_SPORT 0x10 /* Source IP port */ 110#define T4_FILTER_IP_DPORT 0x20 /* Destination IP port */ 111#define T4_FILTER_FCoE 0x40 /* Fibre Channel over Ethernet packet */ 112#define T4_FILTER_PORT 0x80 /* Physical ingress port */ 113#define T4_FILTER_VNIC 0x100 /* VNIC id or outer VLAN */ 114#define T4_FILTER_VLAN 0x200 /* VLAN ID */ 115#define T4_FILTER_IP_TOS 0x400 /* IPv4 TOS/IPv6 Traffic Class */ 116#define T4_FILTER_IP_PROTO 0x800 /* IP protocol */ 117#define T4_FILTER_ETH_TYPE 0x1000 /* Ethernet Type */ 118#define T4_FILTER_MAC_IDX 0x2000 /* MPS MAC address match index */ 119#define T4_FILTER_MPS_HIT_TYPE 0x4000 /* MPS match type */ 120#define T4_FILTER_IP_FRAGMENT 0x8000 /* IP fragment */ 121 122#define T4_FILTER_IC_VNIC 0x80000000 /* TP Ingress Config's F_VNIC 123 bit. It indicates whether 124 T4_FILTER_VNIC bit means VNIC 125 id (PF/VF) or outer VLAN. 126 0 = oVLAN, 1 = VNIC */ 127 128/* Filter action */ 129enum { 130 FILTER_PASS = 0, /* default */ 131 FILTER_DROP, 132 FILTER_SWITCH 133}; 134 135/* 802.1q manipulation on FILTER_SWITCH */ 136enum { 137 VLAN_NOCHANGE = 0, /* default */ 138 VLAN_REMOVE, 139 VLAN_INSERT, 140 VLAN_REWRITE 141}; 142 143/* MPS match type */ 144enum { 145 UCAST_EXACT = 0, /* exact unicast match */ 146 UCAST_HASH = 1, /* inexact (hashed) unicast match */ 147 MCAST_EXACT = 2, /* exact multicast match */ 148 MCAST_HASH = 3, /* inexact (hashed) multicast match */ 149 PROMISC = 4, /* no match but port is promiscuous */ 150 HYPPROMISC = 5, /* port is hypervisor-promisuous + not bcast */ 151 BCAST = 6, /* broadcast packet */ 152}; 153 154/* Rx steering */ 155enum { 156 DST_MODE_QUEUE, /* queue is directly specified by filter */ 157 DST_MODE_RSS_QUEUE, /* filter specifies RSS entry containing queue */ 158 DST_MODE_RSS, /* queue selected by default RSS hash lookup */ 159 DST_MODE_FILT_RSS /* queue selected by hashing in filter-specified 160 RSS subtable */ 161}; 162 163enum { 164 NAT_MODE_NONE = 0, /* No NAT performed */ 165 NAT_MODE_DIP, /* NAT on Dst IP */ 166 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 167 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 168 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 169 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 170 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 171 NAT_MODE_ALL /* NAT on entire 4-tuple */ 172}; 173 174struct t4_filter_tuple { 175 /* 176 * These are always available. 177 */ 178 uint8_t sip[16]; /* source IP address (IPv4 in [3:0]) */ 179 uint8_t dip[16]; /* destination IP address (IPv4 in [3:0]) */ 180 uint16_t sport; /* source port */ 181 uint16_t dport; /* destination port */ 182 183 /* 184 * A combination of these (up to 36 bits) is available. TP_VLAN_PRI_MAP 185 * is used to select the global mode and all filters are limited to the 186 * set of fields allowed by the global mode. 187 */ 188 uint16_t vnic; /* VNIC id (PF/VF) or outer VLAN tag */ 189 uint16_t vlan; /* VLAN tag */ 190 uint16_t ethtype; /* Ethernet type */ 191 uint8_t tos; /* TOS/Traffic Type */ 192 uint8_t proto; /* protocol type */ 193 uint32_t fcoe:1; /* FCoE packet */ 194 uint32_t iport:3; /* ingress port */ 195 uint32_t matchtype:3; /* MPS match type */ 196 uint32_t frag:1; /* fragmentation extension header */ 197 uint32_t macidx:9; /* exact match MAC index */ 198 uint32_t vlan_vld:1; /* VLAN valid */ 199 uint32_t ovlan_vld:1; /* outer VLAN tag valid, value in "vnic" */ 200 uint32_t pfvf_vld:1; /* VNIC id (PF/VF) valid, value in "vnic" */ 201}; 202 203struct t4_filter_specification { 204 uint32_t hitcnts:1; /* count filter hits in TCB */ 205 uint32_t prio:1; /* filter has priority over active/server */ 206 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 207 uint32_t hash:1; /* 0 => LE TCAM, 1 => Hash */ 208 uint32_t action:2; /* drop, pass, switch */ 209 uint32_t rpttid:1; /* report TID in RSS hash field */ 210 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 211 uint32_t iq:10; /* ingress queue */ 212 uint32_t maskhash:1; /* dirsteer=0: steer to an RSS sub-region */ 213 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 214 /* 1 => TCB contains IQ ID */ 215 216 /* 217 * Switch proxy/rewrite fields. An ingress packet which matches a 218 * filter with "switch" set will be looped back out as an egress 219 * packet -- potentially with some Ethernet header rewriting. 220 */ 221 uint32_t eport:2; /* egress port to switch packet out */ 222 uint32_t newdmac:1; /* rewrite destination MAC address */ 223 uint32_t newsmac:1; /* rewrite source MAC address */ 224 uint32_t swapmac:1; /* swap SMAC/DMAC for loopback packet */ 225 uint32_t newvlan:2; /* rewrite VLAN Tag */ 226 uint32_t nat_mode:3; /* NAT operation mode */ 227 uint32_t nat_flag_chk:1;/* check TCP flags before NAT'ing */ 228 uint32_t nat_seq_chk; /* sequence value to use for NAT check*/ 229 uint8_t dmac[ETHER_ADDR_LEN]; /* new destination MAC address */ 230 uint8_t smac[ETHER_ADDR_LEN]; /* new source MAC address */ 231 uint16_t vlan; /* VLAN Tag to insert */ 232 233 uint8_t nat_dip[16]; /* destination IP to use after NAT'ing */ 234 uint8_t nat_sip[16]; /* source IP to use after NAT'ing */ 235 uint16_t nat_dport; /* destination port to use after NAT'ing */ 236 uint16_t nat_sport; /* source port to use after NAT'ing */ 237 238 /* 239 * Filter rule value/mask pairs. 240 */ 241 struct t4_filter_tuple val; 242 struct t4_filter_tuple mask; 243}; 244 245struct t4_filter { 246 uint32_t idx; 247 uint16_t l2tidx; 248 uint16_t smtidx; 249 uint64_t hits; 250 struct t4_filter_specification fs; 251}; 252 253/* Tx Scheduling Class parameters */ 254struct t4_sched_class_params { 255 int8_t level; /* scheduler hierarchy level */ 256 int8_t mode; /* per-class or per-flow */ 257 int8_t rateunit; /* bit or packet rate */ 258 int8_t ratemode; /* %port relative or kbps absolute */ 259 int8_t channel; /* scheduler channel [0..N] */ 260 int8_t cl; /* scheduler class [0..N] */ 261 int32_t minrate; /* minimum rate */ 262 int32_t maxrate; /* maximum rate */ 263 int16_t weight; /* percent weight */ 264 int16_t pktsize; /* average packet size */ 265}; 266 267/* 268 * Support for "sched-class" command to allow a TX Scheduling Class to be 269 * programmed with various parameters. 270 */ 271struct t4_sched_params { 272 int8_t subcmd; /* sub-command */ 273 int8_t type; /* packet or flow */ 274 union { 275 struct { /* sub-command SCHED_CLASS_CONFIG */ 276 int8_t minmax; /* minmax enable */ 277 } config; 278 struct t4_sched_class_params params; 279 uint8_t reserved[6 + 8 * 8]; 280 } u; 281}; 282 283enum { 284 SCHED_CLASS_SUBCMD_CONFIG, /* config sub-command */ 285 SCHED_CLASS_SUBCMD_PARAMS, /* params sub-command */ 286}; 287 288enum { 289 SCHED_CLASS_TYPE_PACKET, 290}; 291 292enum { 293 SCHED_CLASS_LEVEL_CL_RL, /* class rate limiter */ 294 SCHED_CLASS_LEVEL_CL_WRR, /* class weighted round robin */ 295 SCHED_CLASS_LEVEL_CH_RL, /* channel rate limiter */ 296}; 297 298enum { 299 SCHED_CLASS_MODE_CLASS, /* per-class scheduling */ 300 SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */ 301}; 302 303enum { 304 SCHED_CLASS_RATEUNIT_BITS, /* bit rate scheduling */ 305 SCHED_CLASS_RATEUNIT_PKTS, /* packet rate scheduling */ 306}; 307 308enum { 309 SCHED_CLASS_RATEMODE_REL, /* percent of port bandwidth */ 310 SCHED_CLASS_RATEMODE_ABS, /* Kb/s */ 311}; 312 313/* 314 * Support for "sched_queue" command to allow one or more NIC TX Queues to be 315 * bound to a TX Scheduling Class. 316 */ 317struct t4_sched_queue { 318 uint8_t port; 319 int8_t queue; /* queue index; -1 => all queues */ 320 int8_t cl; /* class index; -1 => unbind */ 321}; 322 323#define T4_SGE_CONTEXT_SIZE 24 324enum { 325 SGE_CONTEXT_EGRESS, 326 SGE_CONTEXT_INGRESS, 327 SGE_CONTEXT_FLM, 328 SGE_CONTEXT_CNM 329}; 330 331struct t4_sge_context { 332 uint32_t mem_id; 333 uint32_t cid; 334 uint32_t data[T4_SGE_CONTEXT_SIZE / 4]; 335}; 336 337struct t4_mem_range { 338 uint32_t addr; 339 uint32_t len; 340 uint32_t *data; 341}; 342 343#define T4_TRACE_LEN 112 344struct t4_trace_params { 345 uint32_t data[T4_TRACE_LEN / 4]; 346 uint32_t mask[T4_TRACE_LEN / 4]; 347 uint16_t snap_len; 348 uint16_t min_len; 349 uint8_t skip_ofst; 350 uint8_t skip_len; 351 uint8_t invert; 352 uint8_t port; 353}; 354 355struct t4_tracer { 356 uint8_t idx; 357 uint8_t enabled; 358 uint8_t valid; 359 struct t4_trace_params tp; 360}; 361 362struct t4_cudbg_dump { 363 uint8_t wr_flash; 364 uint8_t bitmap[16]; 365 uint32_t len; 366 uint8_t *data; 367}; 368 369enum { 370 OPEN_TYPE_LISTEN = 'L', 371 OPEN_TYPE_ACTIVE = 'A', 372 OPEN_TYPE_PASSIVE = 'P', 373 OPEN_TYPE_DONTCARE = 'D', 374}; 375 376struct offload_settings { 377 int8_t offload; 378 int8_t rx_coalesce; 379 int8_t cong_algo; 380 int8_t sched_class; 381 int8_t tstamp; 382 int8_t sack; 383 int8_t nagle; 384 int8_t ecn; 385 int8_t ddp; 386 int8_t tls; 387 int16_t txq; 388 int16_t rxq; 389 int16_t mss; 390}; 391 392struct offload_rule { 393 char open_type; 394 struct offload_settings settings; 395 struct bpf_program bpf_prog; /* compiled program/filter */ 396}; 397 398/* 399 * An offload policy consists of a set of rules matched in sequence. The 400 * settings of the first rule that matches are applied to that connection. 401 */ 402struct t4_offload_policy { 403 uint32_t nrules; 404 struct offload_rule *rule; 405}; 406 407#define CHELSIO_T4_GETREG _IOWR('f', T4_GETREG, struct t4_reg) 408#define CHELSIO_T4_SETREG _IOW('f', T4_SETREG, struct t4_reg) 409#define CHELSIO_T4_REGDUMP _IOWR('f', T4_REGDUMP, struct t4_regdump) 410#define CHELSIO_T4_GET_FILTER_MODE _IOWR('f', T4_GET_FILTER_MODE, uint32_t) 411#define CHELSIO_T4_SET_FILTER_MODE _IOW('f', T4_SET_FILTER_MODE, uint32_t) 412#define CHELSIO_T4_GET_FILTER _IOWR('f', T4_GET_FILTER, struct t4_filter) 413#define CHELSIO_T4_SET_FILTER _IOWR('f', T4_SET_FILTER, struct t4_filter) 414#define CHELSIO_T4_DEL_FILTER _IOW('f', T4_DEL_FILTER, struct t4_filter) 415#define CHELSIO_T4_GET_SGE_CONTEXT _IOWR('f', T4_GET_SGE_CONTEXT, \ 416 struct t4_sge_context) 417#define CHELSIO_T4_LOAD_FW _IOW('f', T4_LOAD_FW, struct t4_data) 418#define CHELSIO_T4_GET_MEM _IOW('f', T4_GET_MEM, struct t4_mem_range) 419#define CHELSIO_T4_GET_I2C _IOWR('f', T4_GET_I2C, struct t4_i2c_data) 420#define CHELSIO_T4_CLEAR_STATS _IOW('f', T4_CLEAR_STATS, uint32_t) 421#define CHELSIO_T4_SCHED_CLASS _IOW('f', T4_SET_SCHED_CLASS, \ 422 struct t4_sched_params) 423#define CHELSIO_T4_SCHED_QUEUE _IOW('f', T4_SET_SCHED_QUEUE, \ 424 struct t4_sched_queue) 425#define CHELSIO_T4_GET_TRACER _IOWR('f', T4_GET_TRACER, struct t4_tracer) 426#define CHELSIO_T4_SET_TRACER _IOW('f', T4_SET_TRACER, struct t4_tracer) 427#define CHELSIO_T4_LOAD_CFG _IOW('f', T4_LOAD_CFG, struct t4_data) 428#define CHELSIO_T4_LOAD_BOOT _IOW('f', T4_LOAD_BOOT, struct t4_bootrom) 429#define CHELSIO_T4_LOAD_BOOTCFG _IOW('f', T4_LOAD_BOOTCFG, struct t4_data) 430#define CHELSIO_T4_CUDBG_DUMP _IOWR('f', T4_CUDBG_DUMP, struct t4_cudbg_dump) 431#define CHELSIO_T4_SET_OFLD_POLICY _IOW('f', T4_SET_OFLD_POLICY, struct t4_offload_policy) 432#endif 433