1/*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 5 * Copyright (c) 2010-2015 Broadcom Corporation 6 * All rights reserved. 7 * 8 * This file is derived from the sbchipc.h header contributed by Broadcom 9 * to to the Linux staging repository, as well as later revisions of sbchipc.h 10 * distributed with the Asus RT-N16 firmware source code release. 11 * 12 * Permission to use, copy, modify, and/or distribute this software for any 13 * purpose with or without fee is hereby granted, provided that the above 14 * copyright notice and this permission notice appear in all copies. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 17 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 20 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 21 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 22 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 23 * 24 * $FreeBSD$ 25 */ 26 27#ifndef _BHND_CORES_CHIPC_CHIPCREG_H_ 28#define _BHND_CORES_CHIPC_CHIPCREG_H_ 29 30/** Evaluates to true if the given ChipCommon core revision supports 31 * the CHIPC_CORECTRL register */ 32#define CHIPC_HWREV_HAS_CORECTRL(hwrev) ((hwrev) >= 1) 33 34/** Evaluates to true if the given ChipCommon core revision provides 35 * the core count via the chip identification register. */ 36#define CHIPC_NCORES_MIN_HWREV(hwrev) ((hwrev) == 4 || (hwrev) >= 6) 37 38/** Evaluates to true if the given ChipCommon core revision supports 39 * the CHIPC_CAPABILITIES_EXT register */ 40#define CHIPC_HWREV_HAS_CAP_EXT(hwrev) ((hwrev) >= 35) 41 42/** Evaluates to true if the chipcommon core (determined from the provided 43 * @p _chipid (CHIPC_ID) register value) provides a pointer to the enumeration 44 * table via CHIPC_EROMPTR */ 45#define CHIPC_HAS_EROMPTR(_chipid) \ 46 (CHIPC_GET_BITS((_chipid), CHIPC_ID_BUS) != BHND_CHIPTYPE_SIBA) 47 48#define CHIPC_GET_FLAG(_value, _flag) (((_value) & _flag) != 0) 49#define CHIPC_GET_BITS(_value, _field) \ 50 ((_value & _field ## _MASK) >> _field ## _SHIFT) 51 52 53#define CHIPC_ID 0x00 54#define CHIPC_CAPABILITIES 0x04 55#define CHIPC_CORECTRL 0x08 /* rev >= 1 */ 56#define CHIPC_BIST 0x0C 57 58#define CHIPC_OTPST 0x10 /**< otp status */ 59#define CHIPC_OTPCTRL 0x14 /**< otp control */ 60#define CHIPC_OTPPROG 0x18 61#define CHIPC_OTPLAYOUT 0x1C /**< otp layout (IPX OTP) */ 62 63#define CHIPC_INTST 0x20 /**< interrupt status */ 64#define CHIPC_INTM 0x24 /**< interrupt mask */ 65 66#define CHIPC_CHIPCTRL 0x28 /**< chip control (rev >= 11) */ 67#define CHIPC_CHIPST 0x2C /**< chip status (rev >= 11) */ 68 69#define CHIPC_JTAGCMD 0x30 70#define CHIPC_JTAGIR 0x34 71#define CHIPC_JTAGDR 0x38 72#define CHIPC_JTAGCTRL 0x3c 73 74#define CHIPC_SFLASH_BASE 0x40 75#define CHIPC_SFLASH_SIZE 12 76#define CHIPC_SFLASHCTRL 0x40 77#define CHIPC_SFLASHADDR 0x44 78#define CHIPC_SFLASHDATA 0x48 79 80/* siba backplane configuration broadcast (siba-only) */ 81#define CHIPC_SBBCAST_ADDR 0x50 82#define CHIPC_SBBCAST_DATA 0x54 83 84#define CHIPC_GPIOPU 0x58 /**< pull-up mask (rev >= 20) */ 85#define CHIPC_GPIOPD 0x5C /**< pull down mask (rev >= 20) */ 86#define CHIPC_GPIOIN 0x60 87#define CHIPC_GPIOOUT 0x64 88#define CHIPC_GPIOOUTEN 0x68 89#define CHIPC_GPIOCTRL 0x6C 90#define CHIPC_GPIOPOL 0x70 91#define CHIPC_GPIOINTM 0x74 /**< gpio interrupt mask */ 92 93#define CHIPC_GPIOEVENT 0x78 /**< gpio event (rev >= 11) */ 94#define CHIPC_GPIOEVENT_INTM 0x7C /**< gpio event interrupt mask (rev >= 11) */ 95 96#define CHIPC_WATCHDOG 0x80 /**< watchdog timer */ 97 98#define CHIPC_GPIOEVENT_INTPOLARITY 0x84 /**< gpio even interrupt polarity (rev >= 11) */ 99 100#define CHIPC_GPIOTIMERVAL 0x88 /**< gpio-based LED duty cycle (rev >= 16) */ 101#define CHIPC_GPIOTIMEROUTMASK 0x8C 102 103/* clock control registers (non-PMU devices) */ 104#define CHIPC_CLKC_N 0x90 105#define CHIPC_CLKC_SB 0x94 /* m0 (backplane) */ 106#define CHIPC_CLKC_PCI 0x98 /* m1 */ 107#define CHIPC_CLKC_M2 0x9C /* mii/uart/mipsref */ 108#define CHIPC_CLKC_M3 0xA0 /* cpu */ 109#define CHIPC_CLKDIV 0xA4 /* rev >= 3 */ 110 111#define CHIPC_GPIODEBUGSEL 0xA8 /* rev >= 28 */ 112#define CHIPC_CAPABILITIES_EXT 0xAC 113 114/* pll/slowclk clock control registers (rev >= 4) */ 115#define CHIPC_PLL_ON_DELAY 0xB0 /* rev >= 4 */ 116#define CHIPC_PLL_FREFSEL_DELAY 0xB4 /* rev >= 4 */ 117#define CHIPC_PLL_SLOWCLK_CTL 0xB8 /* "slowclock" (rev 6-9) */ 118 119 /* "instaclock" clock control registers */ 120#define CHIPC_SYS_CLK_CTL 0xC0 /* "instaclock" (rev >= 10) */ 121#define CHIPC_SYS_CLK_ST_STRETCH 0xC4 /* state strech (?) rev >= 10 */ 122 123/* indirect backplane access (rev >= 10) */ 124#define CHIPC_BP_ADDRLOW 0xD0 125#define CHIPC_BP_ADDRHIGH 0xD4 126#define CHIPC_BP_DATA 0xD8 127#define CHIPC_BP_INDACCESS 0xE0 128 129/* SPI/I2C (rev >= 37) */ 130#define CHIPC_GSIO_CTRL 0xE4 131#define CHIPC_GSIO_ADDR 0xE8 132#define CHIPC_GSIO_DATA 0xEC 133 134/* More clock dividers (corerev >= 32) */ 135#define CHIPC_CLKDIV2 0xF0 136 137#define CHIPC_EROMPTR 0xFC /**< 32-bit EROM base address 138 * on BCMA devices */ 139 140/* ExtBus control registers (rev >= 3) */ 141#define CHIPC_PCMCIA_CFG 0x100 142#define CHIPC_PCMCIA_MEMWAIT 0x104 143#define CHIPC_PCMCIA_ATTRWAIT 0x108 144#define CHIPC_PCMCIA_IOWAIT 0x10C 145#define CHIPC_IDE_CFG 0x110 146#define CHIPC_IDE_MEMWAIT 0x114 147#define CHIPC_IDE_ATTRWAIT 0x118 148#define CHIPC_IDE_IOWAIT 0x11C 149#define CHIPC_PROG_CFG 0x120 150#define CHIPC_PROG_WAITCOUNT 0x124 151#define CHIPC_FLASH_CFG 0x128 152#define CHIPC_FLASH_WAITCOUNT 0x12C 153#define CHIPC_SECI_CFG 0x130 154#define CHIPC_SECI_ST 0x134 155#define CHIPC_SECI_STM 0x138 156#define CHIPC_SECI_RXNBC 0x13C 157 158/* Enhanced Coexistence Interface (ECI) registers (rev 21-34) */ 159#define CHIPC_ECI_OUTPUT 0x140 160#define CHIPC_ECI_CTRL 0x144 161#define CHIPC_ECI_INPUTLO 0x148 162#define CHIPC_ECI_INPUTMI 0x14C 163#define CHIPC_ECI_INPUTHI 0x150 164#define CHIPC_ECI_INPUTINTPOLARITYLO 0x154 165#define CHIPC_ECI_INPUTINTPOLARITYMI 0x158 166#define CHIPC_ECI_INPUTINTPOLARITYHI 0x15C 167#define CHIPC_ECI_INTMASKLO 0x160 168#define CHIPC_ECI_INTMASKMI 0x164 169#define CHIPC_ECI_INTMASKHI 0x168 170#define CHIPC_ECI_EVENTLO 0x16C 171#define CHIPC_ECI_EVENTMI 0x170 172#define CHIPC_ECI_EVENTHI 0x174 173#define CHIPC_ECI_EVENTMASKLO 0x178 174#define CHIPC_ECI_EVENTMASKMI 0x17C 175#define CHIPC_ECI_EVENTMASKHI 0x180 176 177#define CHIPC_FLASHSTRCFG 0x18C /**< BCM4706 NAND flash config */ 178 179#define CHIPC_SPROM_CTRL 0x190 /**< SPROM interface (rev >= 32) */ 180#define CHIPC_SPROM_ADDR 0x194 181#define CHIPC_SPROM_DATA 0x198 182 183/* Clock control and hardware workarounds (corerev >= 20) */ 184#define CHIPC_CLK_CTL_ST 0x1E0 185#define CHIPC_SPROM_HWWAR 0x19 186 187#define CHIPC_UART_BASE 0x300 188#define CHIPC_UART_SIZE 0x100 189#define CHIPC_UART_MAX 3 /**< max UART blocks */ 190#define CHIPC_UART(_n) (CHIPC_UART_BASE + (CHIPC_UART_SIZE*_n)) 191 192/* PMU register block (rev >= 20) */ 193#define CHIPC_PMU_BASE 0x600 194#define CHIPC_PMU_SIZE 0x70 195 196#define CHIPC_SPROM_OTP 0x800 /* SPROM/OTP address space */ 197#define CHIPC_SPROM_OTP_SIZE 0x400 198 199/** chipid */ 200#define CHIPC_ID_CHIP_MASK 0x0000FFFF /**< chip id */ 201#define CHIPC_ID_CHIP_SHIFT 0 202#define CHIPC_ID_REV_MASK 0x000F0000 /**< chip revision */ 203#define CHIPC_ID_REV_SHIFT 16 204#define CHIPC_ID_PKG_MASK 0x00F00000 /**< physical package ID */ 205#define CHIPC_ID_PKG_SHIFT 20 206#define CHIPC_ID_NUMCORE_MASK 0x0F000000 /**< number of cores on chip (rev >= 4) */ 207#define CHIPC_ID_NUMCORE_SHIFT 24 208#define CHIPC_ID_BUS_MASK 0xF0000000 /**< chip/interconnect type (BHND_CHIPTYPE_*) */ 209#define CHIPC_ID_BUS_SHIFT 28 210 211/* capabilities */ 212#define CHIPC_CAP_NUM_UART_MASK 0x00000003 /* Number of UARTs (1-3) */ 213#define CHIPC_CAP_NUM_UART_SHIFT 0 214#define CHIPC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */ 215#define CHIPC_CAP_UCLKSEL_MASK 0x00000018 /* UARTs clock select */ 216#define CHIPC_CAP_UCLKSEL_SHIFT 3 217#define CHIPC_CAP_UCLKSEL_UINTCLK 0x1 /* UARTs are driven by internal divided clock */ 218#define CHIPC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */ 219#define CHIPC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */ 220#define CHIPC_CAP_EXTBUS_SHIFT 6 221#define CHIPC_CAP_EXTBUS_NONE 0x0 /* No ExtBus present */ 222#define CHIPC_CAP_EXTBUS_FULL 0x1 /* ExtBus: PCMCIA, IDE & Prog */ 223#define CHIPC_CAP_EXTBUS_PROG 0x2 /* ExtBus: ProgIf only */ 224#define CHIPC_CAP_FLASH_MASK 0x00000700 /* Type of flash */ 225#define CHIPC_CAP_FLASH_SHIFT 8 226#define CHIPC_CAP_FLASH_NONE 0x0 /* No flash */ 227#define CHIPC_CAP_SFLASH_ST 0x1 /* ST serial flash */ 228#define CHIPC_CAP_SFLASH_AT 0x2 /* Atmel serial flash */ 229#define CHIPC_CAP_NFLASH 0x3 /* NAND flash */ 230#define CHIPC_CAP_PFLASH 0x7 /* Parallel flash */ 231#define CHIPC_CAP_PLL_MASK 0x00038000 /* Type of PLL */ 232#define CHIPC_CAP_PLL_SHIFT 15 233#define CHIPC_CAP_PWR_CTL 0x00040000 /* Power/clock control */ 234#define CHIPC_CAP_OTP_SIZE_MASK 0x00380000 /* OTP Size (0 = none) */ 235#define CHIPC_CAP_OTP_SIZE_SHIFT 19 /* OTP Size shift */ 236#define CHIPC_CAP_OTP_SIZE_BASE 5 /* OTP Size base */ 237#define CHIPC_CAP_JTAGP 0x00400000 /* JTAG Master Present */ 238#define CHIPC_CAP_ROM 0x00800000 /* Internal boot rom active */ 239#define CHIPC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */ 240#define CHIPC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */ 241#define CHIPC_CAP_ECI 0x20000000 /* Enhanced Coexistence Interface */ 242#define CHIPC_CAP_SPROM 0x40000000 /* SPROM Present, rev >= 32 */ 243#define CHIPC_CAP_4706_NFLASH 0x80000000 /* NAND flash present, BCM4706 or chipc rev38 (BCM5357)? */ 244 245#define CHIPC_CAP2_SECI 0x00000001 /* SECI Present, rev >= 36 */ 246#define CHIPC_CAP2_GSIO 0x00000002 /* GSIO (spi/i2c) present, rev >= 37 */ 247#define CHIPC_CAP2_GCI 0x00000004 /* GCI present (rev >= ??) */ 248#define CHIPC_CAP2_AOB 0x00000040 /* Always on Bus present (rev >= 49) 249 * 250 * If set, PMU and GCI registers 251 * are found in dedicated cores. 252 * 253 * This appears to be a lower power 254 * APB bus, bridged via ARM APB IP. */ 255 256/* 257 * ChipStatus (Common) 258 */ 259 260/** ChipStatus CIS/OTP/SPROM values used to advertise OTP/SPROM availability in 261 * chipcommon revs 11-31. */ 262enum { 263 CHIPC_CST_DEFCIS_SEL = 0, /**< OTP is powered up, use default CIS, no SPROM */ 264 CHIPC_CST_SPROM_SEL = 1, /**< OTP is powered up, SPROM is present */ 265 CHIPC_CST_OTP_SEL = 2, /**< OTP is powered up, no SPROM */ 266 CHIPC_CST_OTP_PWRDN = 3 /**< OTP is powered down, SPROM is present (rev <= 22 only) */ 267}; 268 269 270#define CHIPC_CST_SPROM_OTP_SEL_R22_MASK 0x00000003 /**< chipstatus OTP/SPROM SEL value (rev 22) */ 271#define CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT 0 272#define CHIPC_CST_SPROM_OTP_SEL_R23_MASK 0x000000c0 /**< chipstatus OTP/SPROM SEL value (revs 23-31) 273 * 274 * it is unknown whether this is supported on 275 * any CC revs >= 32 that also vend CHIPC_CAP_* 276 * constants for OTP/SPROM/NVRAM availability. 277 */ 278#define CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT 6 279 280/* PLL type */ 281#define CHIPC_PLL_NONE 0x0 282#define CHIPC_PLL_TYPE1 0x2 /* 48MHz base, 3 dividers */ 283#define CHIPC_PLL_TYPE2 0x4 /* 48MHz, 4 dividers */ 284#define CHIPC_PLL_TYPE3 0x6 /* 25MHz, 2 dividers */ 285#define CHIPC_PLL_TYPE4 0x1 /* 48MHz, 4 dividers */ 286#define CHIPC_PLL_TYPE5 0x3 /* 25MHz, 4 dividers */ 287#define CHIPC_PLL_TYPE6 0x5 /* 100/200 or 120/240 only */ 288#define CHIPC_PLL_TYPE7 0x7 /* 25MHz, 4 dividers */ 289 290/* dynamic clock control defines */ 291#define CHIPC_LPOMINFREQ 25000 /* low power oscillator min */ 292#define CHIPC_LPOMAXFREQ 43000 /* low power oscillator max */ 293#define CHIPC_XTALMINFREQ 19800000 /* 20 MHz - 1% */ 294#define CHIPC_XTALMAXFREQ 20200000 /* 20 MHz + 1% */ 295#define CHIPC_PCIMINFREQ 25000000 /* 25 MHz */ 296#define CHIPC_PCIMAXFREQ 34000000 /* 33 MHz + fudge */ 297 298#define CHIPC_ILP_DIV_5MHZ 0 /* ILP = 5 MHz */ 299#define CHIPC_ILP_DIV_1MHZ 4 /* ILP = 1 MHz */ 300 301/* Power Control Defines */ 302#define CHIPC_PLL_DELAY 150 /* us pll on delay */ 303#define CHIPC_FREF_DELAY 200 /* us fref change delay */ 304#define CHIPC_MIN_SLOW_CLK 32 /* us Slow clock period */ 305#define CHIPC_XTAL_ON_DELAY 1000 /* us crystal power-on delay */ 306 307/* corecontrol */ 308#define CHIPC_UARTCLKO 0x00000001 /* Drive UART with internal clock */ 309#define CHIPC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ 310#define CHIPC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */ 311 312/* chipcontrol */ 313#define CHIPCTRL_4321A0_DEFAULT 0x3a4 314#define CHIPCTRL_4321A1_DEFAULT 0x0a4 315#define CHIPCTRL_4321_PLL_DOWN 0x800000 /* serdes PLL down override */ 316 317/* Fields in the otpstatus register in rev >= 21 */ 318#define CHIPC_OTPS_OL_MASK 0x000000ff 319#define CHIPC_OTPS_OL_MFG 0x00000001 /* manuf row is locked */ 320#define CHIPC_OTPS_OL_OR1 0x00000002 /* otp redundancy row 1 is locked */ 321#define CHIPC_OTPS_OL_OR2 0x00000004 /* otp redundancy row 2 is locked */ 322#define CHIPC_OTPS_OL_GU 0x00000008 /* general use region is locked */ 323#define CHIPC_OTPS_GUP_MASK 0x00000f00 324#define CHIPC_OTPS_GUP_SHIFT 8 325#define CHIPC_OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */ 326#define CHIPC_OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */ 327#define CHIPC_OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */ 328#define CHIPC_OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */ 329#define CHIPC_OTPS_READY 0x00001000 330#define CHIPC_OTPS_RV(x) (1 << (16 + (x))) /* redundancy entry valid */ 331#define CHIPC_OTPS_RV_MASK 0x0fff0000 332 333/* IPX OTP fields in the otpcontrol register */ 334#define CHIPC_OTPC_PROGSEL 0x00000001 335#define CHIPC_OTPC_PCOUNT_MASK 0x0000000e 336#define CHIPC_OTPC_PCOUNT_SHIFT 1 337#define CHIPC_OTPC_VSEL_MASK 0x000000f0 338#define CHIPC_OTPC_VSEL_SHIFT 4 339#define CHIPC_OTPC_TMM_MASK 0x00000700 340#define CHIPC_OTPC_TMM_SHIFT 8 341#define CHIPC_OTPC_ODM 0x00000800 342#define CHIPC_OTPC_PROGEN 0x80000000 343 344/* Fields in otpprog in IPX OTP and HND OTP */ 345#define CHIPC_OTPP_COL_MASK 0x000000ff 346#define CHIPC_OTPP_COL_SHIFT 0 347#define CHIPC_OTPP_ROW_MASK 0x0000ff00 348#define CHIPC_OTPP_ROW_SHIFT 8 349#define CHIPC_OTPP_OC_MASK 0x0f000000 350#define CHIPC_OTPP_OC_SHIFT 24 351#define CHIPC_OTPP_READERR 0x10000000 352#define CHIPC_OTPP_VALUE_MASK 0x20000000 353#define CHIPC_OTPP_VALUE_SHIFT 29 354#define CHIPC_OTPP_START_BUSY 0x80000000 355#define CHIPC_OTPP_READ 0x40000000 /* HND OTP */ 356 357/* otplayout */ 358#define CHIPC_OTPL_SIZE_MASK 0x0000f000 /* rev >= 49 */ 359#define CHIPC_OTPL_SIZE_SHIFT 12 360#define CHIPC_OTPL_GUP_MASK 0x00000FFF /* bit offset to general use region */ 361#define CHIPC_OTPL_GUP_SHIFT 0 362#define CHIPC_OTPL_CISFORMAT_NEW 0x80000000 /* rev >= 36 */ 363 364/* Opcodes for OTPP_OC field */ 365#define CHIPC_OTPPOC_READ 0 366#define CHIPC_OTPPOC_BIT_PROG 1 367#define CHIPC_OTPPOC_VERIFY 3 368#define CHIPC_OTPPOC_INIT 4 369#define CHIPC_OTPPOC_SET 5 370#define CHIPC_OTPPOC_RESET 6 371#define CHIPC_OTPPOC_OCST 7 372#define CHIPC_OTPPOC_ROW_LOCK 8 373#define CHIPC_OTPPOC_PRESCN_TEST 9 374 375/* Jtagm characteristics that appeared at a given corerev */ 376#define CHIPC_JTAGM_CREV_OLD 10 /* Old command set, 16bit max IR */ 377#define CHIPC_JTAGM_CREV_IRP 22 /* Able to do pause-ir */ 378#define CHIPC_JTAGM_CREV_RTI 28 /* Able to do return-to-idle */ 379 380/* jtagcmd */ 381#define CHIPC_JCMD_START 0x80000000 382#define CHIPC_JCMD_BUSY 0x80000000 383#define CHIPC_JCMD_STATE_MASK 0x60000000 384#define CHIPC_JCMD_STATE_TLR 0x00000000 /* Test-logic-reset */ 385#define CHIPC_JCMD_STATE_PIR 0x20000000 /* Pause IR */ 386#define CHIPC_JCMD_STATE_PDR 0x40000000 /* Pause DR */ 387#define CHIPC_JCMD_STATE_RTI 0x60000000 /* Run-test-idle */ 388#define CHIPC_JCMD0_ACC_MASK 0x0000f000 389#define CHIPC_JCMD0_ACC_IRDR 0x00000000 390#define CHIPC_JCMD0_ACC_DR 0x00001000 391#define CHIPC_JCMD0_ACC_IR 0x00002000 392#define CHIPC_JCMD0_ACC_RESET 0x00003000 393#define CHIPC_JCMD0_ACC_IRPDR 0x00004000 394#define CHIPC_JCMD0_ACC_PDR 0x00005000 395#define CHIPC_JCMD0_IRW_MASK 0x00000f00 396#define CHIPC_JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */ 397#define CHIPC_JCMD_ACC_IRDR 0x00000000 398#define CHIPC_JCMD_ACC_DR 0x00010000 399#define CHIPC_JCMD_ACC_IR 0x00020000 400#define CHIPC_JCMD_ACC_RESET 0x00030000 401#define CHIPC_JCMD_ACC_IRPDR 0x00040000 402#define CHIPC_JCMD_ACC_PDR 0x00050000 403#define CHIPC_JCMD_ACC_PIR 0x00060000 404#define CHIPC_JCMD_ACC_IRDR_I 0x00070000 /* rev 28: return to run-test-idle */ 405#define CHIPC_JCMD_ACC_DR_I 0x00080000 /* rev 28: return to run-test-idle */ 406#define CHIPC_JCMD_IRW_MASK 0x00001f00 407#define CHIPC_JCMD_IRW_SHIFT 8 408#define CHIPC_JCMD_DRW_MASK 0x0000003f 409 410/* jtagctrl */ 411#define CHIPC_JCTRL_FORCE_CLK 4 /* Force clock */ 412#define CHIPC_JCTRL_EXT_EN 2 /* Enable external targets */ 413#define CHIPC_JCTRL_EN 1 /* Enable Jtag master */ 414 415/* Fields in clkdiv */ 416#define CHIPC_CLKD_SFLASH 0x0f000000 417#define CHIPC_CLKD_SFLASH_SHIFT 24 418#define CHIPC_CLKD_OTP 0x000f0000 419#define CHIPC_CLKD_OTP_SHIFT 16 420#define CHIPC_CLKD_JTAG 0x00000f00 421#define CHIPC_CLKD_JTAG_SHIFT 8 422#define CHIPC_CLKD_UART 0x000000ff 423 424#define CHIPC_CLKD2_SPROM 0x00000003 425 426/* intstatus/intmask */ 427#define CHIPC_CI_GPIO 0x00000001 /* gpio intr */ 428#define CHIPC_CI_EI 0x00000002 /* extif intr (corerev >= 3) */ 429#define CHIPC_CI_TEMP 0x00000004 /* temp. ctrl intr (corerev >= 15) */ 430#define CHIPC_CI_SIRQ 0x00000008 /* serial IRQ intr (corerev >= 15) */ 431#define CHIPC_CI_PMU 0x00000020 /* pmu intr (corerev >= 21) */ 432#define CHIPC_CI_UART 0x00000040 /* uart intr (corerev >= 21) */ 433#define CHIPC_CI_WDRESET 0x80000000 /* watchdog reset occurred */ 434 435/* slow_clk_ctl */ 436#define CHIPC_SCC_SS_MASK 0x00000007 /* slow clock source mask */ 437#define CHIPC_SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */ 438#define CHIPC_SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */ 439#define CHIPC_SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */ 440#define CHIPC_SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ 441#define CHIPC_SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 442 * 0: LPO is enabled 443 */ 444#define CHIPC_SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 445 * 0: power logic control 446 */ 447#define CHIPC_SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors 448 * PLL clock disable requests from core 449 */ 450#define CHIPC_SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't 451 * disable crystal when appropriate 452 */ 453#define CHIPC_SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */ 454#define CHIPC_SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */ 455#define CHIPC_SCC_CD_SHIFT 16 456 457/* system_clk_ctl */ 458#define CHIPC_SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */ 459#define CHIPC_SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */ 460#define CHIPC_SYCC_FP 0x00000004 /* ForcePLLOn */ 461#define CHIPC_SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */ 462#define CHIPC_SYCC_HR 0x00000010 /* Force HT */ 463#define CHIPC_SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */ 464#define CHIPC_SYCC_CD_SHIFT 16 465 466/* Indirect backplane access */ 467#define CHIPC_BPIA_BYTEEN 0x0000000f 468#define CHIPC_BPIA_SZ1 0x00000001 469#define CHIPC_BPIA_SZ2 0x00000003 470#define CHIPC_BPIA_SZ4 0x00000007 471#define CHIPC_BPIA_SZ8 0x0000000f 472#define CHIPC_BPIA_WRITE 0x00000100 473#define CHIPC_BPIA_START 0x00000200 474#define CHIPC_BPIA_BUSY 0x00000200 475#define CHIPC_BPIA_ERROR 0x00000400 476 477/* pcmcia/prog/flash_config */ 478#define CHIPC_CF_EN 0x00000001 /* enable */ 479#define CHIPC_CF_EM_MASK 0x0000000e /* mode */ 480#define CHIPC_CF_EM_SHIFT 1 481#define CHIPC_CF_EM_FLASH 0 /* flash/asynchronous mode */ 482#define CHIPC_CF_EM_SYNC 2 /* synchronous mode */ 483#define CHIPC_CF_EM_PCMCIA 4 /* pcmcia mode */ 484#define CHIPC_CF_DS 0x00000010 /* destsize: 0=8bit, 1=16bit */ 485#define CHIPC_CF_BS 0x00000020 /* byteswap */ 486#define CHIPC_CF_CD_MASK 0x000000c0 /* clock divider */ 487#define CHIPC_CF_CD_SHIFT 6 488#define CHIPC_CF_CD_DIV2 0x00000000 /* backplane/2 */ 489#define CHIPC_CF_CD_DIV3 0x00000040 /* backplane/3 */ 490#define CHIPC_CF_CD_DIV4 0x00000080 /* backplane/4 */ 491#define CHIPC_CF_CE 0x00000100 /* clock enable */ 492#define CHIPC_CF_SB 0x00000200 /* size/bytestrobe (synch only) */ 493 494/* pcmcia_memwait */ 495#define CHIPC_PM_W0_MASK 0x0000003f /* waitcount0 */ 496#define CHIPC_PM_W1_MASK 0x00001f00 /* waitcount1 */ 497#define CHIPC_PM_W1_SHIFT 8 498#define CHIPC_PM_W2_MASK 0x001f0000 /* waitcount2 */ 499#define CHIPC_PM_W2_SHIFT 16 500#define CHIPC_PM_W3_MASK 0x1f000000 /* waitcount3 */ 501#define CHIPC_PM_W3_SHIFT 24 502 503/* pcmcia_attrwait */ 504#define CHIPC_PA_W0_MASK 0x0000003f /* waitcount0 */ 505#define CHIPC_PA_W1_MASK 0x00001f00 /* waitcount1 */ 506#define CHIPC_PA_W1_SHIFT 8 507#define CHIPC_PA_W2_MASK 0x001f0000 /* waitcount2 */ 508#define CHIPC_PA_W2_SHIFT 16 509#define CHIPC_PA_W3_MASK 0x1f000000 /* waitcount3 */ 510#define CHIPC_PA_W3_SHIFT 24 511 512/* pcmcia_iowait */ 513#define CHIPC_PI_W0_MASK 0x0000003f /* waitcount0 */ 514#define CHIPC_PI_W1_MASK 0x00001f00 /* waitcount1 */ 515#define CHIPC_PI_W1_SHIFT 8 516#define CHIPC_PI_W2_MASK 0x001f0000 /* waitcount2 */ 517#define CHIPC_PI_W2_SHIFT 16 518#define CHIPC_PI_W3_MASK 0x1f000000 /* waitcount3 */ 519#define CHIPC_PI_W3_SHIFT 24 520 521/* prog_waitcount */ 522#define CHIPC_PW_W0_MASK 0x0000001f /* waitcount0 */ 523#define CHIPC_PW_W1_MASK 0x00001f00 /* waitcount1 */ 524#define CHIPC_PW_W1_SHIFT 8 525#define CHIPC_PW_W2_MASK 0x001f0000 /* waitcount2 */ 526#define CHIPC_PW_W2_SHIFT 16 527#define CHIPC_PW_W3_MASK 0x1f000000 /* waitcount3 */ 528#define CHIPC_PW_W3_SHIFT 24 529 530#define CHIPC_PW_W0 0x0000000c 531#define CHIPC_PW_W1 0x00000a00 532#define CHIPC_PW_W2 0x00020000 533#define CHIPC_PW_W3 0x01000000 534 535/* flash_waitcount */ 536#define CHIPC_FW_W0_MASK 0x0000003f /* waitcount0 */ 537#define CHIPC_FW_W1_MASK 0x00001f00 /* waitcount1 */ 538#define CHIPC_FW_W1_SHIFT 8 539#define CHIPC_FW_W2_MASK 0x001f0000 /* waitcount2 */ 540#define CHIPC_FW_W2_SHIFT 16 541#define CHIPC_FW_W3_MASK 0x1f000000 /* waitcount3 */ 542#define CHIPC_FW_W3_SHIFT 24 543 544/* When SPROM support present, fields in spromcontrol */ 545#define CHIPC_SRC_START 0x80000000 546#define CHIPC_SRC_BUSY 0x80000000 547#define CHIPC_SRC_OPCODE 0x60000000 548#define CHIPC_SRC_OP_READ 0x00000000 549#define CHIPC_SRC_OP_WRITE 0x20000000 550#define CHIPC_SRC_OP_WRDIS 0x40000000 551#define CHIPC_SRC_OP_WREN 0x60000000 552#define CHIPC_SRC_OTPSEL 0x00000010 553#define CHIPC_SRC_LOCK 0x00000008 554#define CHIPC_SRC_SIZE_MASK 0x00000006 555#define CHIPC_SRC_SIZE_1K 0x00000000 556#define CHIPC_SRC_SIZE_4K 0x00000002 557#define CHIPC_SRC_SIZE_16K 0x00000004 558#define CHIPC_SRC_SIZE_SHIFT 1 559#define CHIPC_SRC_PRESENT 0x00000001 560 561/* gpiotimerval */ 562#define CHIPC_GPIO_ONTIME_SHIFT 16 563#define CHIPC_GPIOTIMERVAL_DEFAULT_ON 10 /**< default 10% on duty cycle */ 564#define CHIPC_GPIOTIMERVAL_DEFAULT_OFF 90 /**< default 90% off duty cycle */ 565#define CHIPC_GPIOTIMERVAL_DEFAULT \ 566 ((CHIPC_GPIOTIMERVAL_DEFAULT_ON << CHIPC_GPIO_ONTIME_SHIFT) | \ 567 (CHIPC_GPIOTIMERVAL_DEFAULT_OFF)) 568 569/* clockcontrol_n */ 570#define CHIPC_CN_N1_MASK 0x3f /* n1 control */ 571#define CHIPC_CN_N1_SHIFT 0 572#define CHIPC_CN_N2_MASK 0x3f00 /* n2 control */ 573#define CHIPC_CN_N2_SHIFT 8 574#define CHIPC_CN_PLLC_MASK 0xf0000 /* pll control */ 575#define CHIPC_CN_PLLC_SHIFT 16 576 577/* clockcontrol_sb/pci/uart */ 578#define CHIPC_M1_MASK 0x3f /* m1 control */ 579#define CHIPC_M1_SHIFT 0 580#define CHIPC_M2_MASK 0x3f00 /* m2 control */ 581#define CHIPC_M2_SHIFT 8 582#define CHIPC_M3_MASK 0x3f0000 /* m3 control */ 583#define CHIPC_M3_SHIFT 16 584#define CHIPC_MC_MASK 0x1f000000 /* mux control */ 585#define CHIPC_MC_SHIFT 24 586 587/* N3M Clock control magic field values */ 588#define CHIPC_F6_2 0x02 /* A factor of 2 in */ 589#define CHIPC_F6_3 0x03 /* 6-bit fields like */ 590#define CHIPC_F6_4 0x05 /* N1, M1 or M3 */ 591#define CHIPC_F6_5 0x09 592#define CHIPC_F6_6 0x11 593#define CHIPC_F6_7 0x21 594 595#define CHIPC_F5_BIAS 5 /* 5-bit fields get this added */ 596 597#define CHIPC_MC_BYPASS 0x08 598#define CHIPC_MC_M1 0x04 599#define CHIPC_MC_M1M2 0x02 600#define CHIPC_MC_M1M2M3 0x01 601#define CHIPC_MC_M1M3 0x11 602 603/* Type 2 Clock control magic field values */ 604#define CHIPC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */ 605#define CHIPC_T2M2_BIAS 3 /* m2 bias */ 606 607#define CHIPC_T2MC_M1BYP 1 608#define CHIPC_T2MC_M2BYP 2 609#define CHIPC_T2MC_M3BYP 4 610 611/* Type 6 Clock control magic field values */ 612#define CHIPC_T6_MMASK 1 /* bits of interest in m */ 613#define CHIPC_T6_M0 120000000 /* sb clock for m = 0 */ 614#define CHIPC_T6_M1 100000000 /* sb clock for m = 1 */ 615#define CHIPC_SB2MIPS_T6(sb) (2 * (sb)) 616 617/* Common clock base */ 618#define CHIPC_CLOCK_BASE1 24000000 /* Half the clock freq */ 619#define CHIPC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLLs */ 620 621/* Clock control values for 200MHz in 5350 */ 622#define CHIPC_CLKC_5350_N 0x0311 623#define CHIPC_CLKC_5350_M 0x04020009 624 625/* Bits in the ExtBus config registers */ 626#define CHIPC_CFG_EN 0x0001 /* Enable */ 627#define CHIPC_CFG_EM_MASK 0x000e /* Extif Mode */ 628#define CHIPC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */ 629#define CHIPC_CFG_EM_SYNC 0x0002 /* Synchronous */ 630#define CHIPC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */ 631#define CHIPC_CFG_EM_IDE 0x0006 /* IDE */ 632#define CHIPC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */ 633#define CHIPC_FLASH_CFG_CD_MASK 0x00e0 /* Sync: Clock divisor, rev >= 20 */ 634#define CHIPC_FLASH_CFG_CE 0x0100 /* Sync: Clock enable, rev >= 20 */ 635#define CHIPC_FLASH_CFG_SB 0x0200 /* Sync: Size/Bytestrobe, rev >= 20 */ 636#define CHIPC_FLASH_CFG_IS 0x0400 /* Extif Sync Clk Select, rev >= 20 */ 637 638/* ExtBus address space */ 639#define CHIPC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */ 640#define CHIPC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */ 641#define CHIPC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */ 642#define CHIPC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */ 643#define CHIPC_EB_IDE 0x1a800000 /* IDE memory base */ 644#define CHIPC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */ 645#define CHIPC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */ 646#define CHIPC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */ 647#define CHIPC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */ 648 649/* Start/busy bit in flashcontrol */ 650#define CHIPC_SFLASH_OPCODE 0x000000ff 651#define CHIPC_SFLASH_ACTION 0x00000700 652#define CHIPC_SFLASH_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */ 653#define CHIPC_SFLASH_START 0x80000000 654#define CHIPC_SFLASH_BUSY SFLASH_START 655 656/* flashcontrol action codes */ 657#define CHIPC_SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */ 658#define CHIPC_SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */ 659#define CHIPC_SFLASH_ACT_OP3A 0x0200 /* opcode + 3 addr bytes */ 660#define CHIPC_SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addr & 1 data bytes */ 661#define CHIPC_SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addr & 4 data bytes */ 662#define CHIPC_SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addr, 4 don't care & 4 data bytes */ 663#define CHIPC_SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addr, 1 don't care & 4 data bytes */ 664 665/* flashcontrol action+opcodes for ST flashes */ 666#define CHIPC_SFLASH_ST_WREN 0x0006 /* Write Enable */ 667#define CHIPC_SFLASH_ST_WRDIS 0x0004 /* Write Disable */ 668#define CHIPC_SFLASH_ST_RDSR 0x0105 /* Read Status Register */ 669#define CHIPC_SFLASH_ST_WRSR 0x0101 /* Write Status Register */ 670#define CHIPC_SFLASH_ST_READ 0x0303 /* Read Data Bytes */ 671#define CHIPC_SFLASH_ST_PP 0x0302 /* Page Program */ 672#define CHIPC_SFLASH_ST_SE 0x02d8 /* Sector Erase */ 673#define CHIPC_SFLASH_ST_BE 0x00c7 /* Bulk Erase */ 674#define CHIPC_SFLASH_ST_DP 0x00b9 /* Deep Power-down */ 675#define CHIPC_SFLASH_ST_RES 0x03ab /* Read Electronic Signature */ 676#define CHIPC_SFLASH_ST_CSA 0x1000 /* Keep chip select asserted */ 677#define CHIPC_SFLASH_ST_SSE 0x0220 /* Sub-sector Erase */ 678 679/* Status register bits for ST flashes */ 680#define CHIPC_SFLASH_ST_WIP 0x01 /* Write In Progress */ 681#define CHIPC_SFLASH_ST_WEL 0x02 /* Write Enable Latch */ 682#define CHIPC_SFLASH_ST_BP_MASK 0x1c /* Block Protect */ 683#define CHIPC_SFLASH_ST_BP_SHIFT 2 684#define CHIPC_SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */ 685 686/* flashcontrol action+opcodes for Atmel flashes */ 687#define CHIPC_SFLASH_AT_READ 0x07e8 688#define CHIPC_SFLASH_AT_PAGE_READ 0x07d2 689#define CHIPC_SFLASH_AT_BUF1_READ 690#define CHIPC_SFLASH_AT_BUF2_READ 691#define CHIPC_SFLASH_AT_STATUS 0x01d7 692#define CHIPC_SFLASH_AT_BUF1_WRITE 0x0384 693#define CHIPC_SFLASH_AT_BUF2_WRITE 0x0387 694#define CHIPC_SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283 695#define CHIPC_SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286 696#define CHIPC_SFLASH_AT_BUF1_PROGRAM 0x0288 697#define CHIPC_SFLASH_AT_BUF2_PROGRAM 0x0289 698#define CHIPC_SFLASH_AT_PAGE_ERASE 0x0281 699#define CHIPC_SFLASH_AT_BLOCK_ERASE 0x0250 700#define CHIPC_SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 701#define CHIPC_SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 702#define CHIPC_SFLASH_AT_BUF1_LOAD 0x0253 703#define CHIPC_SFLASH_AT_BUF2_LOAD 0x0255 704#define CHIPC_SFLASH_AT_BUF1_COMPARE 0x0260 705#define CHIPC_SFLASH_AT_BUF2_COMPARE 0x0261 706#define CHIPC_SFLASH_AT_BUF1_REPROGRAM 0x0258 707#define CHIPC_SFLASH_AT_BUF2_REPROGRAM 0x0259 708 709/* Status register bits for Atmel flashes */ 710#define CHIPC_SFLASH_AT_READY 0x80 711#define CHIPC_SFLASH_AT_MISMATCH 0x40 712#define CHIPC_SFLASH_AT_ID_MASK 0x38 713#define CHIPC_SFLASH_AT_ID_SHIFT 3 714 715/* 716 * These are the UART port assignments, expressed as offsets from the base 717 * register. These assignments should hold for any serial port based on 718 * a 8250, 16450, or 16550(A). 719 */ 720 721#define CHIPC_UART_RX 0 /* In: Receive buffer (DLAB=0) */ 722#define CHIPC_UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ 723#define CHIPC_UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ 724#define CHIPC_UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */ 725#define CHIPC_UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */ 726#define CHIPC_UART_IIR 2 /* In: Interrupt Identity Register */ 727#define CHIPC_UART_FCR 2 /* Out: FIFO Control Register */ 728#define CHIPC_UART_LCR 3 /* Out: Line Control Register */ 729#define CHIPC_UART_MCR 4 /* Out: Modem Control Register */ 730#define CHIPC_UART_LSR 5 /* In: Line Status Register */ 731#define CHIPC_UART_MSR 6 /* In: Modem Status Register */ 732#define CHIPC_UART_SCR 7 /* I/O: Scratch Register */ 733#define CHIPC_UART_LCR_DLAB 0x80 /* Divisor latch access bit */ 734#define CHIPC_UART_LCR_WLEN8 0x03 /* Word length: 8 bits */ 735#define CHIPC_UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */ 736#define CHIPC_UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 737#define CHIPC_UART_LSR_RX_FIFO 0x80 /* Receive FIFO error */ 738#define CHIPC_UART_LSR_TDHR 0x40 /* Data-hold-register empty */ 739#define CHIPC_UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ 740#define CHIPC_UART_LSR_BREAK 0x10 /* Break interrupt */ 741#define CHIPC_UART_LSR_FRAMING 0x08 /* Framing error */ 742#define CHIPC_UART_LSR_PARITY 0x04 /* Parity error */ 743#define CHIPC_UART_LSR_OVERRUN 0x02 /* Overrun error */ 744#define CHIPC_UART_LSR_RXRDY 0x01 /* Receiver ready */ 745#define CHIPC_UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */ 746 747/* Interrupt Identity Register (IIR) bits */ 748#define CHIPC_UART_IIR_FIFO_MASK 0xc0 /* IIR FIFO disable/enabled mask */ 749#define CHIPC_UART_IIR_INT_MASK 0xf /* IIR interrupt ID source */ 750#define CHIPC_UART_IIR_MDM_CHG 0x0 /* Modem status changed */ 751#define CHIPC_UART_IIR_NOINT 0x1 /* No interrupt pending */ 752#define CHIPC_UART_IIR_THRE 0x2 /* THR empty */ 753#define CHIPC_UART_IIR_RCVD_DATA 0x4 /* Received data available */ 754#define CHIPC_UART_IIR_RCVR_STATUS 0x6 /* Receiver status */ 755#define CHIPC_UART_IIR_CHAR_TIME 0xc /* Character time */ 756 757/* Interrupt Enable Register (IER) bits */ 758#define CHIPC_UART_IER_EDSSI 8 /* enable modem status interrupt */ 759#define CHIPC_UART_IER_ELSI 4 /* enable receiver line status interrupt */ 760#define CHIPC_UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */ 761#define CHIPC_UART_IER_ERBFI 1 /* enable data available interrupt */ 762 763/* 4325 chip-specific ChipStatus register bits */ 764#define CHIPC_CST4325_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK 765#define CHIPC_CST4325_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT 766#define CHIPC_CST4325_SDIO_USB_MODE_MASK 0x00000004 767#define CHIPC_CST4325_SDIO_USB_MODE_SHIFT 2 768#define CHIPC_CST4325_RCAL_VALID_MASK 0x00000008 769#define CHIPC_CST4325_RCAL_VALID_SHIFT 3 770#define CHIPC_CST4325_RCAL_VALUE_MASK 0x000001f0 771#define CHIPC_CST4325_RCAL_VALUE_SHIFT 4 772#define CHIPC_CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */ 773#define CHIPC_CST4325_PMUTOP_2B_SHIFT 9 774 775/* 4329 chip-specific ChipStatus register bits */ 776#define CHIPC_CST4329_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK 777#define CHIPC_CST4329_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT 778#define CHIPC_CST4329_SPI_SDIO_MODE_MASK 0x00000004 779#define CHIPC_CST4329_SPI_SDIO_MODE_SHIFT 2 780 781/* 4312 chip-specific ChipStatus register bits */ 782#define CHIPC_CST4312_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK 783#define CHIPC_CST4312_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT 784 785 786/* 4322 chip-specific ChipStatus register bits */ 787#define CHIPC_CST4322_XTAL_FREQ_20_40MHZ 0x00000020 788#define CHIPC_CST4322_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R23_MASK 789#define CHIPC_CST4322_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT 790#define CHIPC_CST4322_PCI_OR_USB 0x00000100 791#define CHIPC_CST4322_BOOT_MASK 0x00000600 792#define CHIPC_CST4322_BOOT_SHIFT 9 793#define CHIPC_CST4322_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ 794#define CHIPC_CST4322_BOOT_FROM_ROM 1 /* boot from ROM */ 795#define CHIPC_CST4322_BOOT_FROM_FLASH 2 /* boot from FLASH */ 796#define CHIPC_CST4322_BOOT_FROM_INVALID 3 797#define CHIPC_CST4322_ILP_DIV_EN 0x00000800 798#define CHIPC_CST4322_FLASH_TYPE_MASK 0x00001000 799#define CHIPC_CST4322_FLASH_TYPE_SHIFT 12 800#define CHIPC_CST4322_FLASH_TYPE_SHIFT_ST 0 /* ST serial FLASH */ 801#define CHIPC_CST4322_FLASH_TYPE_SHIFT_ATMEL 1 /* ATMEL flash */ 802#define CHIPC_CST4322_ARM_TAP_SEL 0x00002000 803#define CHIPC_CST4322_RES_INIT_MODE_MASK 0x0000c000 804#define CHIPC_CST4322_RES_INIT_MODE_SHIFT 14 805#define CHIPC_CST4322_RES_INIT_MODE_ILPAVAIL 0 /* resinitmode: ILP available */ 806#define CHIPC_CST4322_RES_INIT_MODE_ILPREQ 1 /* resinitmode: ILP request */ 807#define CHIPC_CST4322_RES_INIT_MODE_ALPAVAIL 2 /* resinitmode: ALP available */ 808#define CHIPC_CST4322_RES_INIT_MODE_HTAVAIL 3 /* resinitmode: HT available */ 809#define CHIPC_CST4322_PCIPLLCLK_GATING 0x00010000 810#define CHIPC_CST4322_CLK_SWITCH_PCI_TO_ALP 0x00020000 811#define CHIPC_CST4322_PCI_CARDBUS_MODE 0x00040000 812 813/* 43236 Chip specific ChipStatus register bits */ 814#define CHIPC_CST43236_SFLASH_MASK 0x00000040 815#define CHIPC_CST43236_OTP_SEL_MASK 0x00000080 816#define CHIPC_CST43236_OTP_SEL_SHIFT 7 817#define CHIPC_CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */ 818#define CHIPC_CST43236_BP_CLK 0x00000200 /* 120/96Mbps */ 819#define CHIPC_CST43236_BOOT_MASK 0x00001800 820#define CHIPC_CST43236_BOOT_SHIFT 11 821#define CHIPC_CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ 822#define CHIPC_CST43236_BOOT_FROM_ROM 1 /* boot from ROM */ 823#define CHIPC_CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */ 824#define CHIPC_CST43236_BOOT_FROM_INVALID 3 825 826/* 43237 Chip specific ChipStatus register bits */ 827#define CHIPC_CST43237_BP_CLK 0x00000200 /* 96/80Mbps */ 828 829/* 4331 Chip specific ChipStatus register bits */ 830#define CHIPC_CST4331_XTAL_FREQ 0x00000001 /* crystal frequency 20/40Mhz */ 831#define CHIPC_CST4331_SPROM_PRESENT 0x00000002 832#define CHIPC_CST4331_OTP_PRESENT 0x00000004 833#define CHIPC_CST4331_LDO_RF 0x00000008 834#define CHIPC_CST4331_LDO_PAR 0x00000010 835 836/* 4331 chip-specific CHIPCTRL register bits */ 837#define CHIPC_CCTRL4331_BT_COEXIST (1<<0) /* 0 disable */ 838#define CHIPC_CCTRL4331_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ 839#define CHIPC_CCTRL4331_EXT_LNA (1<<2) /* 0 disable */ 840#define CHIPC_CCTRL4331_SPROM_GPIO13_15 (1<<3) /* sprom/gpio13-15 mux */ 841#define CHIPC_CCTRL4331_EXTPA_EN (1<<4) /* 0 ext pa disable, 1 ext pa enabled */ 842#define CHIPC_CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5) /* set drive out GPIO_CLK on sprom_cs pin */ 843#define CHIPC_CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) /* use sprom_cs pin as PCIE mdio interface */ 844#define CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) /* aband extpa will be at gpio2/5 and sprom_dout */ 845#define CHIPC_CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) /* override core control on pipe_AuxClkEnable */ 846#define CHIPC_CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) /* override core control on pipe_AuxPowerDown */ 847#define CHIPC_CCTRL4331_PCIE_AUXCLKEN (1<<10) /* pcie_auxclkenable */ 848#define CHIPC_CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11) /* pcie_pipe_pllpowerdown */ 849#define CHIPC_CCTRL4331_EXTPA_EN2 (1<<12) /* 0 ext pa2 disable, 1 ext pa2 enabled */ 850#define CHIPC_CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16) /* enable bt_shd0 at gpio4 */ 851#define CHIPC_CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17) /* enable bt_shd1 at gpio5 */ 852 853/* 4315 chip-specific ChipStatus register bits */ 854#define CHIPC_CST4315_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK 855#define CHIPC_CST4315_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT 856#define CHIPC_CST4315_SDIO_MODE 0x00000004 /* gpio [8], sdio/usb mode */ 857#define CHIPC_CST4315_RCAL_VALID 0x00000008 858#define CHIPC_CST4315_RCAL_VALUE_MASK 0x000001f0 859#define CHIPC_CST4315_RCAL_VALUE_SHIFT 4 860#define CHIPC_CST4315_PALDO_EXTPNP 0x00000200 /* PALDO is configured with external PNP */ 861#define CHIPC_CST4315_CBUCK_MODE_MASK 0x00000c00 862#define CHIPC_CST4315_CBUCK_MODE_BURST 0x00000400 863#define CHIPC_CST4315_CBUCK_MODE_LPBURST 0x00000c00 864 865/* 4319 chip-specific ChipStatus register bits */ 866#define CHIPC_CST4319_SPI_CPULESSUSB 0x00000001 867#define CHIPC_CST4319_SPI_CLK_POL 0x00000002 868#define CHIPC_CST4319_SPI_CLK_PH 0x00000008 869#define CHIPC_CST4319_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R23_MASK /* gpio [7:6], SDIO CIS selection */ 870#define CHIPC_CST4319_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT 871#define CHIPC_CST4319_SDIO_USB_MODE 0x00000100 /* gpio [8], sdio/usb mode */ 872#define CHIPC_CST4319_REMAP_SEL_MASK 0x00000600 873#define CHIPC_CST4319_ILPDIV_EN 0x00000800 874#define CHIPC_CST4319_XTAL_PD_POL 0x00001000 875#define CHIPC_CST4319_LPO_SEL 0x00002000 876#define CHIPC_CST4319_RES_INIT_MODE 0x0000c000 877#define CHIPC_CST4319_PALDO_EXTPNP 0x00010000 /* PALDO is configured with external PNP */ 878#define CHIPC_CST4319_CBUCK_MODE_MASK 0x00060000 879#define CHIPC_CST4319_CBUCK_MODE_BURST 0x00020000 880#define CHIPC_CST4319_CBUCK_MODE_LPBURST 0x00060000 881#define CHIPC_CST4319_RCAL_VALID 0x01000000 882#define CHIPC_CST4319_RCAL_VALUE_MASK 0x3e000000 883#define CHIPC_CST4319_RCAL_VALUE_SHIFT 25 884 885/* 4336 chip-specific ChipStatus register bits */ 886#define CHIPC_CST4336_SPI_MODE_MASK 0x00000001 887#define CHIPC_CST4336_SPROM_PRESENT 0x00000002 888#define CHIPC_CST4336_OTP_PRESENT 0x00000004 889#define CHIPC_CST4336_ARMREMAP_0 0x00000008 890#define CHIPC_CST4336_ILPDIV_EN_MASK 0x00000010 891#define CHIPC_CST4336_ILPDIV_EN_SHIFT 4 892#define CHIPC_CST4336_XTAL_PD_POL_MASK 0x00000020 893#define CHIPC_CST4336_XTAL_PD_POL_SHIFT 5 894#define CHIPC_CST4336_LPO_SEL_MASK 0x00000040 895#define CHIPC_CST4336_LPO_SEL_SHIFT 6 896#define CHIPC_CST4336_RES_INIT_MODE_MASK 0x00000180 897#define CHIPC_CST4336_RES_INIT_MODE_SHIFT 7 898#define CHIPC_CST4336_CBUCK_MODE_MASK 0x00000600 899#define CHIPC_CST4336_CBUCK_MODE_SHIFT 9 900 901/* 4330 chip-specific ChipStatus register bits */ 902#define CHIPC_CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6) /* SDIO || gSPI */ 903#define CHIPC_CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6) /* USB || USBDA */ 904#define CHIPC_CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0) /* SDIO */ 905#define CHIPC_CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4) /* gSPI */ 906#define CHIPC_CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6) /* USB packet-oriented */ 907#define CHIPC_CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7) /* USB Direct Access */ 908#define CHIPC_CST4330_OTP_PRESENT 0x00000010 909#define CHIPC_CST4330_LPO_AUTODET_EN 0x00000020 910#define CHIPC_CST4330_ARMREMAP_0 0x00000040 911#define CHIPC_CST4330_SPROM_PRESENT 0x00000080 /* takes priority over OTP if both set */ 912#define CHIPC_CST4330_ILPDIV_EN 0x00000100 913#define CHIPC_CST4330_LPO_SEL 0x00000200 914#define CHIPC_CST4330_RES_INIT_MODE_SHIFT 10 915#define CHIPC_CST4330_RES_INIT_MODE_MASK 0x00000c00 916#define CHIPC_CST4330_CBUCK_MODE_SHIFT 12 917#define CHIPC_CST4330_CBUCK_MODE_MASK 0x00003000 918#define CHIPC_CST4330_CBUCK_POWER_OK 0x00004000 919#define CHIPC_CST4330_BB_PLL_LOCKED 0x00008000 920#define CHIPC_SOCDEVRAM_4330_BP_ADDR 0x1E000000 921#define CHIPC_SOCDEVRAM_4330_ARM_ADDR 0x00800000 922 923/* 4313 chip-specific ChipStatus register bits */ 924#define CHIPC_CST4313_SPROM_PRESENT 1 925#define CHIPC_CST4313_OTP_PRESENT 2 926#define CHIPC_CST4313_SPROM_OTP_SEL_MASK 0x00000002 927#define CHIPC_CST4313_SPROM_OTP_SEL_SHIFT 0 928 929/* 43228 chipstatus reg bits */ 930#define CHIPC_CST43228_ILP_DIV_EN 0x1 931#define CHIPC_CST43228_OTP_PRESENT 0x2 932#define CHIPC_CST43228_SERDES_REFCLK_PADSEL 0x4 933#define CHIPC_CST43228_SDIO_MODE 0x8 934 935#define CHIPC_CST43228_SDIO_OTP_PRESENT 0x10 936#define CHIPC_CST43228_SDIO_RESET 0x20 937 938/* 4706 chipstatus reg bits */ 939#define CHIPC_CST4706_LOWCOST_PKG (1<<0) /* 0: full-featured package 1: low-cost package */ 940#define CHIPC_CST4706_SFLASH_PRESENT (1<<1) /* 0: parallel, 1: serial flash is present */ 941#define CHIPC_CST4706_SFLASH_TYPE (1<<2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */ 942#define CHIPC_CST4706_MIPS_BENDIAN (1<<3) /* 0: little, 1: big endian */ 943#define CHIPC_CST4706_PCIE1_DISABLE (1<<5) /* PCIE1 enable strap pin */ 944 945/* 4706 flashstrconfig reg bits */ 946#define CHIPC_FLSTRCF4706_MASK 0x000000ff 947#define CHIPC_FLSTRCF4706_SF1 0x00000001 /* 2nd serial flash present */ 948#define CHIPC_FLSTRCF4706_PF1 0x00000002 /* 2nd parallel flash present */ 949#define CHIPC_FLSTRCF4706_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */ 950#define CHIPC_FLSTRCF4706_NF1 0x00000008 /* 2nd NAND flash present */ 951#define CHIPC_FLSTRCF4706_1ST_MADDR_SEG_MASK 0x000000f0 /* Valid value mask */ 952#define CHIPC_FLSTRCF4706_1ST_MADDR_SEG_SHIFT 4 953#define CHIPC_FLSTRCF4706_1ST_MADDR_SEG_4MB 0x1 /* 4MB */ 954#define CHIPC_FLSTRCF4706_1ST_MADDR_SEG_8MB 0x2 /* 8MB */ 955#define CHIPC_FLSTRCF4706_1ST_MADDR_SEG_16MB 0x3 /* 16MB */ 956#define CHIPC_FLSTRCF4706_1ST_MADDR_SEG_32MB 0x4 /* 32MB */ 957#define CHIPC_FLSTRCF4706_1ST_MADDR_SEG_64MB 0x5 /* 64MB */ 958#define CHIPC_FLSTRCF4706_1ST_MADDR_SEG_128MB 0x6 /* 128MB */ 959#define CHIPC_FLSTRCF4706_1ST_MADDR_SEG_256MB 0x7 /* 256MB */ 960 961/* 962* Register eci_inputlo bitfield values. 963* - BT packet type information bits [7:0] 964*/ 965/* [3:0] - Task (link) type */ 966#define CHIPC_BT_ACL 0x00 967#define CHIPC_BT_SCO 0x01 968#define CHIPC_BT_eSCO 0x02 969#define CHIPC_BT_A2DP 0x03 970#define CHIPC_BT_SNIFF 0x04 971#define CHIPC_BT_PAGE_SCAN 0x05 972#define CHIPC_BT_INQUIRY_SCAN 0x06 973#define CHIPC_BT_PAGE 0x07 974#define CHIPC_BT_INQUIRY 0x08 975#define CHIPC_BT_MSS 0x09 976#define CHIPC_BT_PARK 0x0a 977#define CHIPC_BT_RSSISCAN 0x0b 978#define CHIPC_BT_MD_ACL 0x0c 979#define CHIPC_BT_MD_eSCO 0x0d 980#define CHIPC_BT_SCAN_WITH_SCO_LINK 0x0e 981#define CHIPC_BT_SCAN_WITHOUT_SCO_LINK 0x0f 982/* [7:4] = packet duration code */ 983/* [8] - Master / Slave */ 984#define CHIPC_BT_MASTER 0 985#define CHIPC_BT_SLAVE 1 986/* [11:9] - multi-level priority */ 987#define CHIPC_BT_LOWEST_PRIO 0x0 988#define CHIPC_BT_HIGHEST_PRIO 0x3 989 990#endif /* _BHND_CORES_CHIPC_CHIPCREG_H_ */ 991