1/*- 2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD$"); 32 33/* 34 * Resource specifications and register maps for Broadcom PCI/PCIe cores 35 * configured as PCI-BHND bridges. 36 */ 37 38#include <sys/param.h> 39#include <sys/bus.h> 40 41#include <machine/bus.h> 42#include <sys/rman.h> 43#include <machine/resource.h> 44 45#include <dev/pci/pcireg.h> 46#include <dev/pci/pcivar.h> 47 48#include <dev/bhnd/cores/pci/bhnd_pcireg.h> 49#include <dev/bhnd/cores/pcie2/bhnd_pcie2_reg.h> 50 51#include "bhndbvar.h" 52#include "bhndb_pcireg.h" 53 54static const struct bhndb_hwcfg bhndb_pci_hwcfg_v0; 55static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci; 56static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie; 57static const struct bhndb_hwcfg bhndb_pci_hwcfg_v2; 58static const struct bhndb_hwcfg bhndb_pci_hwcfg_v3; 59 60/** 61 * Define a bhndb_hw match entry. 62 * 63 * @param _name The entry name. 64 * @param _vers The configuration version associated with this entry. 65 */ 66#define BHNDB_HW_MATCH(_name, _vers, ...) { \ 67 .name = _name, \ 68 .hw_reqs = _BHNDB_HW_REQ_ARRAY(__VA_ARGS__), \ 69 .num_hw_reqs = (sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)) / \ 70 sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)[0])), \ 71 .cfg = &bhndb_pci_hwcfg_ ## _vers \ 72} 73 74#define _BHNDB_HW_REQ_ARRAY(...) (struct bhnd_core_match[]) { __VA_ARGS__ } 75 76/** 77 * Generic PCI-SIBA bridge configuration usable with all known siba(4)-based 78 * PCI devices; this configuration is adequate for enumerating a bridged 79 * siba(4) bus to determine the full hardware configuration. 80 * 81 * @par Compatibility 82 * - Compatible with PCI_V0, PCI_V1, PCI_V2, and PCI_V3 devices. 83 * - Compatible with siba(4) bus enumeration. 84 * - Compatible with bcma(4) bus enumeration if the ChipCommon core is mapped 85 * at the default enumeration address (0x18000000). 86 */ 87const struct bhndb_hwcfg bhndb_pci_siba_generic_hwcfg = { 88 .resource_specs = (const struct resource_spec[]) { 89 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 90 { -1, 0, 0 } 91 }, 92 93 .register_windows = (const struct bhndb_regwin[]) { 94 /* bar0+0x0000: configurable backplane window */ 95 { 96 .win_type = BHNDB_REGWIN_T_DYN, 97 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 98 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 99 .d.dyn = { 100 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL 101 }, 102 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 103 }, 104 BHNDB_REGWIN_TABLE_END 105 }, 106 107 /* DMA unsupported under generic configuration */ 108 .dma_translations = NULL, 109}; 110 111 112/** 113 * Generic PCI-BCMA bridge configuration usable with all known bcma(4)-based 114 * PCI devices; this configuration is adequate for enumerating a bridged 115 * bcma(4) bus to determine the full hardware configuration. 116 * 117 * @par Compatibility 118 * - Compatible with PCI_V1, PCI_V2, and PCI_V3 devices. 119 * - Compatible with both siba(4) and bcma(4) bus enumeration. 120 */ 121const struct bhndb_hwcfg bhndb_pci_bcma_generic_hwcfg = { 122 .resource_specs = (const struct resource_spec[]) { 123 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 124 { -1, 0, 0 } 125 }, 126 127 .register_windows = (const struct bhndb_regwin[]) { 128 /* bar0+0x0000: configurable backplane window */ 129 { 130 .win_type = BHNDB_REGWIN_T_DYN, 131 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 132 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 133 .d.dyn = { 134 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL, 135 }, 136 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 137 }, 138 139 /* bar0+0x3000: chipc core registers */ 140 { 141 .win_type = BHNDB_REGWIN_T_CORE, 142 .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, 143 .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, 144 .d.core = { 145 .class = BHND_DEVCLASS_CC, 146 .unit = 0, 147 .port = 0, 148 .region = 0, 149 .port_type = BHND_PORT_DEVICE 150 }, 151 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 152 }, 153 154 BHNDB_REGWIN_TABLE_END 155 }, 156 157 /* DMA unsupported under generic configuration */ 158 .dma_translations = NULL, 159}; 160 161/** 162 * Hardware configuration tables for Broadcom HND PCI NICs. 163 */ 164const struct bhndb_hw bhndb_pci_generic_hw_table[] = { 165 /* PCI/V0 WLAN */ 166 BHNDB_HW_MATCH("PCI/v0 WLAN", v0, 167 /* PCI Core */ 168 { 169 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 170 BHND_MATCH_CORE_ID (BHND_COREID_PCI), 171 BHND_MATCH_CORE_REV( 172 HWREV_LTE (BHNDB_PCI_V0_MAX_PCI_HWREV)), 173 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCI), 174 BHND_MATCH_CORE_UNIT (0) 175 }, 176 177 /* 802.11 Core */ 178 { 179 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 180 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN), 181 BHND_MATCH_CORE_UNIT (0) 182 } 183 ), 184 185 /* PCI/V1 WLAN */ 186 BHNDB_HW_MATCH("PCI/v1 WLAN", v1_pci, 187 /* PCI Core */ 188 { 189 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 190 BHND_MATCH_CORE_ID (BHND_COREID_PCI), 191 BHND_MATCH_CORE_REV( 192 HWREV_GTE (BHNDB_PCI_V1_MIN_PCI_HWREV)), 193 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCI), 194 BHND_MATCH_CORE_UNIT (0) 195 }, 196 197 /* 802.11 Core */ 198 { 199 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 200 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN), 201 BHND_MATCH_CORE_UNIT (0) 202 } 203 ), 204 205 /* PCIE/V1 WLAN */ 206 BHNDB_HW_MATCH("PCIe/v1 WLAN", v1_pcie, 207 /* PCIe Core */ 208 { 209 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 210 BHND_MATCH_CORE_ID (BHND_COREID_PCIE), 211 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCIE), 212 BHND_MATCH_CORE_UNIT (0) 213 }, 214 215 /* ChipCommon (revision <= 31) */ 216 { 217 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 218 BHND_MATCH_CORE_ID (BHND_COREID_CC), 219 BHND_MATCH_CORE_REV( 220 HWREV_LTE (BHNDB_PCI_V1_MAX_CHIPC_HWREV)), 221 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_CC), 222 BHND_MATCH_CORE_UNIT (0) 223 }, 224 225 /* 802.11 Core */ 226 { 227 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 228 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN), 229 BHND_MATCH_CORE_UNIT (0) 230 } 231 ), 232 233 /* PCIE/V2 WLAN */ 234 BHNDB_HW_MATCH("PCIe/v2 WLAN", v2, 235 /* PCIe Core */ 236 { 237 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 238 BHND_MATCH_CORE_ID (BHND_COREID_PCIE), 239 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCIE), 240 BHND_MATCH_CORE_UNIT (0) 241 }, 242 243 /* ChipCommon (revision >= 32) */ 244 { 245 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 246 BHND_MATCH_CORE_ID (BHND_COREID_CC), 247 BHND_MATCH_CORE_REV( 248 HWREV_GTE (BHNDB_PCI_V2_MIN_CHIPC_HWREV)), 249 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_CC), 250 BHND_MATCH_CORE_UNIT (0) 251 }, 252 253 /* 802.11 Core */ 254 { 255 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 256 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN), 257 BHND_MATCH_CORE_UNIT (0) 258 } 259 ), 260 261 262 /* PCIE/V3 WLAN */ 263 BHNDB_HW_MATCH("PCIe-Gen2/v3 WLAN", v3, 264 /* PCIe Gen2 Core */ 265 { 266 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 267 BHND_MATCH_CORE_ID (BHND_COREID_PCIE2), 268 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCIE), 269 BHND_MATCH_CORE_UNIT (0) 270 }, 271 272 /* 802.11 Core */ 273 { 274 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 275 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN), 276 BHND_MATCH_CORE_UNIT (0) 277 } 278 ), 279 280 { NULL, NULL, 0, NULL } 281}; 282 283/** 284 * PCI_V0 hardware configuration. 285 * 286 * Applies to: 287 * - PCI (cid=0x804, revision <= 12) 288 */ 289static const struct bhndb_hwcfg bhndb_pci_hwcfg_v0 = { 290 .resource_specs = (const struct resource_spec[]) { 291 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 292 { -1, 0, 0 } 293 }, 294 295 .register_windows = (const struct bhndb_regwin[]) { 296 /* bar0+0x0000: configurable backplane window */ 297 { 298 .win_type = BHNDB_REGWIN_T_DYN, 299 .win_offset = BHNDB_PCI_V0_BAR0_WIN0_OFFSET, 300 .win_size = BHNDB_PCI_V0_BAR0_WIN0_SIZE, 301 .d.dyn = { 302 .cfg_offset = BHNDB_PCI_V0_BAR0_WIN0_CONTROL 303 }, 304 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 305 }, 306 307 /* bar0+0x1000: sprom shadow */ 308 { 309 .win_type = BHNDB_REGWIN_T_SPROM, 310 .win_offset = BHNDB_PCI_V0_BAR0_SPROM_OFFSET, 311 .win_size = BHNDB_PCI_V0_BAR0_SPROM_SIZE, 312 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 313 }, 314 315 /* 316 * bar0+0x1800: pci core registers. 317 * 318 * Does not include the SSB CFG registers found at the end of 319 * the 4K core register block; these are mapped non-contigiously 320 * by the next entry. 321 */ 322 { 323 .win_type = BHNDB_REGWIN_T_CORE, 324 .win_offset = BHNDB_PCI_V0_BAR0_PCIREG_OFFSET, 325 .win_size = BHNDB_PCI_V0_BAR0_PCIREG_SIZE, 326 .d.core = { 327 .class = BHND_DEVCLASS_PCI, 328 .unit = 0, 329 .port = 0, 330 .region = 0, 331 .port_type = BHND_PORT_DEVICE, 332 }, 333 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 334 }, 335 336 /* bar0+0x1E00: pci core (SSB CFG registers) */ 337 { 338 .win_type = BHNDB_REGWIN_T_CORE, 339 .win_offset = BHNDB_PCI_V0_BAR0_PCISB_OFFSET , 340 .win_size = BHNDB_PCI_V0_BAR0_PCISB_SIZE, 341 .d.core = { 342 .class = BHND_DEVCLASS_PCI, 343 .unit = 0, 344 .port = 0, 345 .region = 0, 346 .offset = BHNDB_PCI_V0_BAR0_PCISB_COREOFF, 347 .port_type = BHND_PORT_DEVICE 348 }, 349 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 350 }, 351 352 BHNDB_REGWIN_TABLE_END 353 }, 354 355 .dma_translations = (const struct bhnd_dma_translation[]) { 356 { 357 .base_addr = BHND_PCI_DMA32_TRANSLATION, 358 .addr_mask = ~BHND_PCI_DMA32_MASK, 359 .addrext_mask = BHND_PCI_DMA32_MASK 360 }, 361 BHND_DMA_TRANSLATION_TABLE_END 362 } 363}; 364 365/** 366 * PCI_V1 (PCI-only) hardware configuration (PCI version) 367 * 368 * Applies to: 369 * - PCI (cid=0x804, revision >= 13) 370 */ 371static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci = { 372 .resource_specs = (const struct resource_spec[]) { 373 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 374 { -1, 0, 0 } 375 }, 376 377 .register_windows = (const struct bhndb_regwin[]) { 378 /* bar0+0x0000: configurable backplane window */ 379 { 380 .win_type = BHNDB_REGWIN_T_DYN, 381 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 382 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 383 .d.dyn = { 384 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL 385 }, 386 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 387 }, 388 389 /* bar0+0x1000: sprom shadow */ 390 { 391 .win_type = BHNDB_REGWIN_T_SPROM, 392 .win_offset = BHNDB_PCI_V1_BAR0_SPROM_OFFSET, 393 .win_size = BHNDB_PCI_V1_BAR0_SPROM_SIZE, 394 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 395 }, 396 397 /* bar0+0x2000: pci core registers */ 398 { 399 .win_type = BHNDB_REGWIN_T_CORE, 400 .win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET, 401 .win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE, 402 .d.core = { 403 .class = BHND_DEVCLASS_PCI, 404 .unit = 0, 405 .port = 0, 406 .region = 0, 407 .port_type = BHND_PORT_DEVICE 408 }, 409 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 410 }, 411 412 /* bar0+0x3000: chipc core registers */ 413 { 414 .win_type = BHNDB_REGWIN_T_CORE, 415 .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, 416 .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, 417 .d.core = { 418 .class = BHND_DEVCLASS_CC, 419 .unit = 0, 420 .port = 0, 421 .region = 0, 422 .port_type = BHND_PORT_DEVICE 423 }, 424 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 425 }, 426 427 BHNDB_REGWIN_TABLE_END 428 }, 429 430 .dma_translations = (const struct bhnd_dma_translation[]) { 431 { 432 .base_addr = BHND_PCI_DMA32_TRANSLATION, 433 .addr_mask = ~BHND_PCI_DMA32_MASK, 434 .addrext_mask = BHND_PCI_DMA32_MASK 435 }, 436 BHND_DMA_TRANSLATION_TABLE_END 437 } 438}; 439 440/** 441 * PCI_V1 hardware configuration (PCIE version). 442 * 443 * Applies to: 444 * - PCIE (cid=0x820) with ChipCommon (revision <= 31) 445 */ 446static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie = { 447 .resource_specs = (const struct resource_spec[]) { 448 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 449 { -1, 0, 0 } 450 }, 451 452 .register_windows = (const struct bhndb_regwin[]) { 453 /* bar0+0x0000: configurable backplane window */ 454 { 455 .win_type = BHNDB_REGWIN_T_DYN, 456 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 457 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 458 .d.dyn = { 459 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL 460 }, 461 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 462 }, 463 464 /* bar0+0x1000: sprom shadow */ 465 { 466 .win_type = BHNDB_REGWIN_T_SPROM, 467 .win_offset = BHNDB_PCI_V1_BAR0_SPROM_OFFSET, 468 .win_size = BHNDB_PCI_V1_BAR0_SPROM_SIZE, 469 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 470 }, 471 472 /* bar0+0x2000: pci core registers */ 473 { 474 .win_type = BHNDB_REGWIN_T_CORE, 475 .win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET, 476 .win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE, 477 .d.core = { 478 .class = BHND_DEVCLASS_PCIE, 479 .unit = 0, 480 .port = 0, 481 .region = 0, 482 .port_type = BHND_PORT_DEVICE 483 }, 484 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 485 }, 486 487 /* bar0+0x3000: chipc core registers */ 488 { 489 .win_type = BHNDB_REGWIN_T_CORE, 490 .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, 491 .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, 492 .d.core = { 493 .class = BHND_DEVCLASS_CC, 494 .unit = 0, 495 .port = 0, 496 .region = 0, 497 .port_type = BHND_PORT_DEVICE 498 }, 499 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 500 }, 501 502 BHNDB_REGWIN_TABLE_END 503 }, 504 505 .dma_translations = (const struct bhnd_dma_translation[]) { 506 { 507 .base_addr = BHND_PCIE_DMA32_TRANSLATION, 508 .addr_mask = ~BHND_PCIE_DMA32_MASK, 509 .addrext_mask = BHND_PCIE_DMA32_MASK 510 }, 511 { 512 .base_addr = BHND_PCIE_DMA64_TRANSLATION, 513 .addr_mask = ~BHND_PCIE_DMA64_MASK, 514 .addrext_mask = BHND_PCIE_DMA64_MASK 515 }, 516 BHND_DMA_TRANSLATION_TABLE_END 517 } 518}; 519 520/** 521 * PCI_V2 hardware configuration. 522 * 523 * Applies to: 524 * - PCIE (cid=0x820) with ChipCommon (revision >= 32) 525 */ 526static const struct bhndb_hwcfg bhndb_pci_hwcfg_v2 = { 527 .resource_specs = (const struct resource_spec[]) { 528 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 529 { -1, 0, 0 } 530 }, 531 532 .register_windows = (const struct bhndb_regwin[]) { 533 /* bar0+0x0000: configurable backplane window */ 534 { 535 .win_type = BHNDB_REGWIN_T_DYN, 536 .win_offset = BHNDB_PCI_V2_BAR0_WIN0_OFFSET, 537 .win_size = BHNDB_PCI_V2_BAR0_WIN0_SIZE, 538 .d.dyn = { 539 .cfg_offset = BHNDB_PCI_V2_BAR0_WIN0_CONTROL, 540 }, 541 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 542 }, 543 544 /* bar0+0x1000: configurable backplane window */ 545 { 546 .win_type = BHNDB_REGWIN_T_DYN, 547 .win_offset = BHNDB_PCI_V2_BAR0_WIN1_OFFSET, 548 .win_size = BHNDB_PCI_V2_BAR0_WIN1_SIZE, 549 .d.dyn = { 550 .cfg_offset = BHNDB_PCI_V2_BAR0_WIN1_CONTROL, 551 }, 552 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 553 }, 554 555 /* bar0+0x2000: pcie core registers */ 556 { 557 .win_type = BHNDB_REGWIN_T_CORE, 558 .win_offset = BHNDB_PCI_V2_BAR0_PCIREG_OFFSET, 559 .win_size = BHNDB_PCI_V2_BAR0_PCIREG_SIZE, 560 .d.core = { 561 .class = BHND_DEVCLASS_PCIE, 562 .unit = 0, 563 .port = 0, 564 .region = 0, 565 .port_type = BHND_PORT_DEVICE 566 }, 567 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 568 }, 569 570 /* bar0+0x3000: chipc core registers */ 571 { 572 .win_type = BHNDB_REGWIN_T_CORE, 573 .win_offset = BHNDB_PCI_V2_BAR0_CCREGS_OFFSET, 574 .win_size = BHNDB_PCI_V2_BAR0_CCREGS_SIZE, 575 .d.core = { 576 .class = BHND_DEVCLASS_CC, 577 .unit = 0, 578 .port = 0, 579 .region = 0, 580 .port_type = BHND_PORT_DEVICE 581 }, 582 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 583 }, 584 585 BHNDB_REGWIN_TABLE_END 586 }, 587 588 .dma_translations = (const struct bhnd_dma_translation[]) { 589 { 590 .base_addr = BHND_PCIE_DMA32_TRANSLATION, 591 .addr_mask = ~BHND_PCIE_DMA32_MASK, 592 .addrext_mask = BHND_PCIE_DMA32_MASK 593 }, 594 { 595 .base_addr = BHND_PCIE_DMA64_TRANSLATION, 596 .addr_mask = ~BHND_PCIE_DMA64_MASK, 597 .addrext_mask = BHND_PCIE_DMA64_MASK 598 }, 599 BHND_DMA_TRANSLATION_TABLE_END 600 } 601}; 602 603/** 604 * PCI_V3 hardware configuration. 605 * 606 * Applies to: 607 * - PCIE2 (cid=0x83c) 608 */ 609static const struct bhndb_hwcfg bhndb_pci_hwcfg_v3 = { 610 .resource_specs = (const struct resource_spec[]) { 611 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 612 { -1, 0, 0 } 613 }, 614 615 .register_windows = (const struct bhndb_regwin[]) { 616 /* bar0+0x0000: configurable backplane window */ 617 { 618 .win_type = BHNDB_REGWIN_T_DYN, 619 .win_offset = BHNDB_PCI_V3_BAR0_WIN0_OFFSET, 620 .win_size = BHNDB_PCI_V3_BAR0_WIN0_SIZE, 621 .d.dyn = { 622 .cfg_offset = BHNDB_PCI_V3_BAR0_WIN0_CONTROL, 623 }, 624 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 625 }, 626 627 /* bar0+0x1000: configurable backplane window */ 628 { 629 .win_type = BHNDB_REGWIN_T_DYN, 630 .win_offset = BHNDB_PCI_V3_BAR0_WIN1_OFFSET, 631 .win_size = BHNDB_PCI_V3_BAR0_WIN1_SIZE, 632 .d.dyn = { 633 .cfg_offset = BHNDB_PCI_V3_BAR0_WIN1_CONTROL, 634 }, 635 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 636 }, 637 638 /* bar0+0x2000: pcie core registers */ 639 { 640 .win_type = BHNDB_REGWIN_T_CORE, 641 .win_offset = BHNDB_PCI_V3_BAR0_PCIREG_OFFSET, 642 .win_size = BHNDB_PCI_V3_BAR0_PCIREG_SIZE, 643 .d.core = { 644 .class = BHND_DEVCLASS_PCIE, 645 .unit = 0, 646 .port = 0, 647 .region = 0, 648 .port_type = BHND_PORT_DEVICE 649 }, 650 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 651 }, 652 653 /* bar0+0x3000: chipc core registers */ 654 { 655 .win_type = BHNDB_REGWIN_T_CORE, 656 .win_offset = BHNDB_PCI_V3_BAR0_CCREGS_OFFSET, 657 .win_size = BHNDB_PCI_V3_BAR0_CCREGS_SIZE, 658 .d.core = { 659 .class = BHND_DEVCLASS_CC, 660 .unit = 0, 661 .port = 0, 662 .region = 0, 663 .port_type = BHND_PORT_DEVICE 664 }, 665 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 666 }, 667 668 BHNDB_REGWIN_TABLE_END 669 }, 670 671 .dma_translations = (const struct bhnd_dma_translation[]) { 672 { 673 .base_addr = BHND_PCIE2_DMA64_TRANSLATION, 674 .addr_mask = ~BHND_PCIE2_DMA64_MASK, 675 .addrext_mask = BHND_PCIE_DMA64_MASK 676 }, 677 BHND_DMA_TRANSLATION_TABLE_END 678 } 679}; 680