1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD$"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/endian.h> 39#include <sys/kernel.h> 40#include <sys/lock.h> 41#include <sys/malloc.h> 42#include <sys/mbuf.h> 43#include <sys/module.h> 44#include <sys/mutex.h> 45#include <sys/rman.h> 46#include <sys/queue.h> 47#include <sys/socket.h> 48#include <sys/sockio.h> 49#include <sys/sysctl.h> 50#include <sys/taskqueue.h> 51 52#include <net/bpf.h> 53#include <net/if.h> 54#include <net/if_var.h> 55#include <net/if_arp.h> 56#include <net/ethernet.h> 57#include <net/if_dl.h> 58#include <net/if_llc.h> 59#include <net/if_media.h> 60#include <net/if_types.h> 61#include <net/if_vlan_var.h> 62 63#include <netinet/in.h> 64#include <netinet/in_systm.h> 65#include <netinet/ip.h> 66#include <netinet/tcp.h> 67#include <netinet/netdump/netdump.h> 68 69#include <dev/mii/mii.h> 70#include <dev/mii/miivar.h> 71 72#include <dev/pci/pcireg.h> 73#include <dev/pci/pcivar.h> 74 75#include <machine/bus.h> 76#include <machine/in_cksum.h> 77 78#include <dev/alc/if_alcreg.h> 79#include <dev/alc/if_alcvar.h> 80 81/* "device miibus" required. See GENERIC if you get errors here. */ 82#include "miibus_if.h" 83#undef ALC_USE_CUSTOM_CSUM 84 85#ifdef ALC_USE_CUSTOM_CSUM 86#define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 87#else 88#define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 89#endif 90 91MODULE_DEPEND(alc, pci, 1, 1, 1); 92MODULE_DEPEND(alc, ether, 1, 1, 1); 93MODULE_DEPEND(alc, miibus, 1, 1, 1); 94 95/* Tunables. */ 96static int msi_disable = 0; 97static int msix_disable = 0; 98TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 99TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 100 101/* 102 * Devices supported by this driver. 103 */ 104static struct alc_ident alc_ident_table[] = { 105 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 106 "Atheros AR8131 PCIe Gigabit Ethernet" }, 107 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 108 "Atheros AR8132 PCIe Fast Ethernet" }, 109 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 110 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 111 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 112 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 113 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 114 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 115 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 116 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 117 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024, 118 "Atheros AR8161 PCIe Gigabit Ethernet" }, 119 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024, 120 "Atheros AR8162 PCIe Fast Ethernet" }, 121 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024, 122 "Atheros AR8171 PCIe Gigabit Ethernet" }, 123 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024, 124 "Atheros AR8172 PCIe Fast Ethernet" }, 125 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024, 126 "Killer E2200 Gigabit Ethernet" }, 127 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2400, 9 * 1024, 128 "Killer E2400 Gigabit Ethernet" }, 129 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2500, 9 * 1024, 130 "Killer E2500 Gigabit Ethernet" }, 131 { 0, 0, 0, NULL} 132}; 133 134static void alc_aspm(struct alc_softc *, int, int); 135static void alc_aspm_813x(struct alc_softc *, int); 136static void alc_aspm_816x(struct alc_softc *, int); 137static int alc_attach(device_t); 138static int alc_check_boundary(struct alc_softc *); 139static void alc_config_msi(struct alc_softc *); 140static int alc_detach(device_t); 141static void alc_disable_l0s_l1(struct alc_softc *); 142static int alc_dma_alloc(struct alc_softc *); 143static void alc_dma_free(struct alc_softc *); 144static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 145static void alc_dsp_fixup(struct alc_softc *, int); 146static int alc_encap(struct alc_softc *, struct mbuf **); 147static struct alc_ident * 148 alc_find_ident(device_t); 149#ifndef __NO_STRICT_ALIGNMENT 150static struct mbuf * 151 alc_fixup_rx(struct ifnet *, struct mbuf *); 152#endif 153static void alc_get_macaddr(struct alc_softc *); 154static void alc_get_macaddr_813x(struct alc_softc *); 155static void alc_get_macaddr_816x(struct alc_softc *); 156static void alc_get_macaddr_par(struct alc_softc *); 157static void alc_init(void *); 158static void alc_init_cmb(struct alc_softc *); 159static void alc_init_locked(struct alc_softc *); 160static void alc_init_rr_ring(struct alc_softc *); 161static int alc_init_rx_ring(struct alc_softc *); 162static void alc_init_smb(struct alc_softc *); 163static void alc_init_tx_ring(struct alc_softc *); 164static void alc_int_task(void *, int); 165static int alc_intr(void *); 166static int alc_ioctl(struct ifnet *, u_long, caddr_t); 167static void alc_mac_config(struct alc_softc *); 168static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 169static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 170static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int); 171static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int); 172static int alc_miibus_readreg(device_t, int, int); 173static void alc_miibus_statchg(device_t); 174static int alc_miibus_writereg(device_t, int, int, int); 175static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 176static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int); 177static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 178static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 179static int alc_mediachange(struct ifnet *); 180static int alc_mediachange_locked(struct alc_softc *); 181static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 182static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 183static void alc_osc_reset(struct alc_softc *); 184static void alc_phy_down(struct alc_softc *); 185static void alc_phy_reset(struct alc_softc *); 186static void alc_phy_reset_813x(struct alc_softc *); 187static void alc_phy_reset_816x(struct alc_softc *); 188static int alc_probe(device_t); 189static void alc_reset(struct alc_softc *); 190static int alc_resume(device_t); 191static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 192static int alc_rxintr(struct alc_softc *, int); 193static void alc_rxfilter(struct alc_softc *); 194static void alc_rxvlan(struct alc_softc *); 195static void alc_setlinkspeed(struct alc_softc *); 196static void alc_setwol(struct alc_softc *); 197static void alc_setwol_813x(struct alc_softc *); 198static void alc_setwol_816x(struct alc_softc *); 199static int alc_shutdown(device_t); 200static void alc_start(struct ifnet *); 201static void alc_start_locked(struct ifnet *); 202static void alc_start_queue(struct alc_softc *); 203static void alc_start_tx(struct alc_softc *); 204static void alc_stats_clear(struct alc_softc *); 205static void alc_stats_update(struct alc_softc *); 206static void alc_stop(struct alc_softc *); 207static void alc_stop_mac(struct alc_softc *); 208static void alc_stop_queue(struct alc_softc *); 209static int alc_suspend(device_t); 210static void alc_sysctl_node(struct alc_softc *); 211static void alc_tick(void *); 212static void alc_txeof(struct alc_softc *); 213static void alc_watchdog(struct alc_softc *); 214static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 215static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 216static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 217 218NETDUMP_DEFINE(alc); 219 220static device_method_t alc_methods[] = { 221 /* Device interface. */ 222 DEVMETHOD(device_probe, alc_probe), 223 DEVMETHOD(device_attach, alc_attach), 224 DEVMETHOD(device_detach, alc_detach), 225 DEVMETHOD(device_shutdown, alc_shutdown), 226 DEVMETHOD(device_suspend, alc_suspend), 227 DEVMETHOD(device_resume, alc_resume), 228 229 /* MII interface. */ 230 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 231 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 232 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 233 234 DEVMETHOD_END 235}; 236 237static driver_t alc_driver = { 238 "alc", 239 alc_methods, 240 sizeof(struct alc_softc) 241}; 242 243static devclass_t alc_devclass; 244 245DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0); 246MODULE_PNP_INFO("U16:vendor;U16:device", pci, alc, alc_ident_table, 247 nitems(alc_ident_table) - 1); 248DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0); 249 250static struct resource_spec alc_res_spec_mem[] = { 251 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 252 { -1, 0, 0 } 253}; 254 255static struct resource_spec alc_irq_spec_legacy[] = { 256 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 257 { -1, 0, 0 } 258}; 259 260static struct resource_spec alc_irq_spec_msi[] = { 261 { SYS_RES_IRQ, 1, RF_ACTIVE }, 262 { -1, 0, 0 } 263}; 264 265static struct resource_spec alc_irq_spec_msix[] = { 266 { SYS_RES_IRQ, 1, RF_ACTIVE }, 267 { -1, 0, 0 } 268}; 269 270static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 }; 271 272static int 273alc_miibus_readreg(device_t dev, int phy, int reg) 274{ 275 struct alc_softc *sc; 276 int v; 277 278 sc = device_get_softc(dev); 279 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 280 v = alc_mii_readreg_816x(sc, phy, reg); 281 else 282 v = alc_mii_readreg_813x(sc, phy, reg); 283 return (v); 284} 285 286static uint32_t 287alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 288{ 289 uint32_t v; 290 int i; 291 292 /* 293 * For AR8132 fast ethernet controller, do not report 1000baseT 294 * capability to mii(4). Even though AR8132 uses the same 295 * model/revision number of F1 gigabit PHY, the PHY has no 296 * ability to establish 1000baseT link. 297 */ 298 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 299 reg == MII_EXTSR) 300 return (0); 301 302 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 303 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 304 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 305 DELAY(5); 306 v = CSR_READ_4(sc, ALC_MDIO); 307 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 308 break; 309 } 310 311 if (i == 0) { 312 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 313 return (0); 314 } 315 316 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 317} 318 319static uint32_t 320alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 321{ 322 uint32_t clk, v; 323 int i; 324 325 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 326 clk = MDIO_CLK_25_128; 327 else 328 clk = MDIO_CLK_25_4; 329 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 330 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 331 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 332 DELAY(5); 333 v = CSR_READ_4(sc, ALC_MDIO); 334 if ((v & MDIO_OP_BUSY) == 0) 335 break; 336 } 337 338 if (i == 0) { 339 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 340 return (0); 341 } 342 343 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 344} 345 346static int 347alc_miibus_writereg(device_t dev, int phy, int reg, int val) 348{ 349 struct alc_softc *sc; 350 int v; 351 352 sc = device_get_softc(dev); 353 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 354 v = alc_mii_writereg_816x(sc, phy, reg, val); 355 else 356 v = alc_mii_writereg_813x(sc, phy, reg, val); 357 return (v); 358} 359 360static uint32_t 361alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 362{ 363 uint32_t v; 364 int i; 365 366 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 367 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 368 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 369 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 370 DELAY(5); 371 v = CSR_READ_4(sc, ALC_MDIO); 372 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 373 break; 374 } 375 376 if (i == 0) 377 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 378 379 return (0); 380} 381 382static uint32_t 383alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 384{ 385 uint32_t clk, v; 386 int i; 387 388 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 389 clk = MDIO_CLK_25_128; 390 else 391 clk = MDIO_CLK_25_4; 392 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 393 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 394 MDIO_SUP_PREAMBLE | clk); 395 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 396 DELAY(5); 397 v = CSR_READ_4(sc, ALC_MDIO); 398 if ((v & MDIO_OP_BUSY) == 0) 399 break; 400 } 401 402 if (i == 0) 403 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 404 405 return (0); 406} 407 408static void 409alc_miibus_statchg(device_t dev) 410{ 411 struct alc_softc *sc; 412 struct mii_data *mii; 413 struct ifnet *ifp; 414 uint32_t reg; 415 416 sc = device_get_softc(dev); 417 418 mii = device_get_softc(sc->alc_miibus); 419 ifp = sc->alc_ifp; 420 if (mii == NULL || ifp == NULL || 421 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 422 return; 423 424 sc->alc_flags &= ~ALC_FLAG_LINK; 425 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 426 (IFM_ACTIVE | IFM_AVALID)) { 427 switch (IFM_SUBTYPE(mii->mii_media_active)) { 428 case IFM_10_T: 429 case IFM_100_TX: 430 sc->alc_flags |= ALC_FLAG_LINK; 431 break; 432 case IFM_1000_T: 433 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 434 sc->alc_flags |= ALC_FLAG_LINK; 435 break; 436 default: 437 break; 438 } 439 } 440 /* Stop Rx/Tx MACs. */ 441 alc_stop_mac(sc); 442 443 /* Program MACs with resolved speed/duplex/flow-control. */ 444 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 445 alc_start_queue(sc); 446 alc_mac_config(sc); 447 /* Re-enable Tx/Rx MACs. */ 448 reg = CSR_READ_4(sc, ALC_MAC_CFG); 449 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 450 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 451 } 452 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 453 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 454} 455 456static uint32_t 457alc_miidbg_readreg(struct alc_softc *sc, int reg) 458{ 459 460 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 461 reg); 462 return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 463 ALC_MII_DBG_DATA)); 464} 465 466static uint32_t 467alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 468{ 469 470 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 471 reg); 472 return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 473 ALC_MII_DBG_DATA, val)); 474} 475 476static uint32_t 477alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 478{ 479 uint32_t clk, v; 480 int i; 481 482 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 483 EXT_MDIO_DEVADDR(devaddr)); 484 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 485 clk = MDIO_CLK_25_128; 486 else 487 clk = MDIO_CLK_25_4; 488 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 489 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 490 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 491 DELAY(5); 492 v = CSR_READ_4(sc, ALC_MDIO); 493 if ((v & MDIO_OP_BUSY) == 0) 494 break; 495 } 496 497 if (i == 0) { 498 device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n", 499 devaddr, reg); 500 return (0); 501 } 502 503 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 504} 505 506static uint32_t 507alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 508{ 509 uint32_t clk, v; 510 int i; 511 512 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 513 EXT_MDIO_DEVADDR(devaddr)); 514 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 515 clk = MDIO_CLK_25_128; 516 else 517 clk = MDIO_CLK_25_4; 518 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 519 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 520 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 521 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 522 DELAY(5); 523 v = CSR_READ_4(sc, ALC_MDIO); 524 if ((v & MDIO_OP_BUSY) == 0) 525 break; 526 } 527 528 if (i == 0) 529 device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n", 530 devaddr, reg); 531 532 return (0); 533} 534 535static void 536alc_dsp_fixup(struct alc_softc *sc, int media) 537{ 538 uint16_t agc, len, val; 539 540 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 541 return; 542 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 543 return; 544 545 /* 546 * Vendor PHY magic. 547 * 1000BT/AZ, wrong cable length 548 */ 549 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 550 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 551 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 552 EXT_CLDCTL6_CAB_LEN_MASK; 553 agc = alc_miidbg_readreg(sc, MII_DBG_AGC); 554 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; 555 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 556 agc > DBG_AGC_LONG1G_LIMT) || 557 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 558 agc > DBG_AGC_LONG1G_LIMT)) { 559 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 560 DBG_AZ_ANADECT_LONG); 561 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 562 MII_EXT_ANEG_AFE); 563 val |= ANEG_AFEE_10BT_100M_TH; 564 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 565 val); 566 } else { 567 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 568 DBG_AZ_ANADECT_DEFAULT); 569 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 570 MII_EXT_ANEG_AFE); 571 val &= ~ANEG_AFEE_10BT_100M_TH; 572 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 573 val); 574 } 575 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 576 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 577 if (media == IFM_1000_T) { 578 /* 579 * Giga link threshold, raise the tolerance of 580 * noise 50%. 581 */ 582 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 583 val &= ~DBG_MSE20DB_TH_MASK; 584 val |= (DBG_MSE20DB_TH_HI << 585 DBG_MSE20DB_TH_SHIFT); 586 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 587 } else if (media == IFM_100_TX) 588 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 589 DBG_MSE16DB_UP); 590 } 591 } else { 592 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 593 val &= ~ANEG_AFEE_10BT_100M_TH; 594 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 595 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 596 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 597 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 598 DBG_MSE16DB_DOWN); 599 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 600 val &= ~DBG_MSE20DB_TH_MASK; 601 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 602 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 603 } 604 } 605} 606 607static void 608alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 609{ 610 struct alc_softc *sc; 611 struct mii_data *mii; 612 613 sc = ifp->if_softc; 614 ALC_LOCK(sc); 615 if ((ifp->if_flags & IFF_UP) == 0) { 616 ALC_UNLOCK(sc); 617 return; 618 } 619 mii = device_get_softc(sc->alc_miibus); 620 621 mii_pollstat(mii); 622 ifmr->ifm_status = mii->mii_media_status; 623 ifmr->ifm_active = mii->mii_media_active; 624 ALC_UNLOCK(sc); 625} 626 627static int 628alc_mediachange(struct ifnet *ifp) 629{ 630 struct alc_softc *sc; 631 int error; 632 633 sc = ifp->if_softc; 634 ALC_LOCK(sc); 635 error = alc_mediachange_locked(sc); 636 ALC_UNLOCK(sc); 637 638 return (error); 639} 640 641static int 642alc_mediachange_locked(struct alc_softc *sc) 643{ 644 struct mii_data *mii; 645 struct mii_softc *miisc; 646 int error; 647 648 ALC_LOCK_ASSERT(sc); 649 650 mii = device_get_softc(sc->alc_miibus); 651 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 652 PHY_RESET(miisc); 653 error = mii_mediachg(mii); 654 655 return (error); 656} 657 658static struct alc_ident * 659alc_find_ident(device_t dev) 660{ 661 struct alc_ident *ident; 662 uint16_t vendor, devid; 663 664 vendor = pci_get_vendor(dev); 665 devid = pci_get_device(dev); 666 for (ident = alc_ident_table; ident->name != NULL; ident++) { 667 if (vendor == ident->vendorid && devid == ident->deviceid) 668 return (ident); 669 } 670 671 return (NULL); 672} 673 674static int 675alc_probe(device_t dev) 676{ 677 struct alc_ident *ident; 678 679 ident = alc_find_ident(dev); 680 if (ident != NULL) { 681 device_set_desc(dev, ident->name); 682 return (BUS_PROBE_DEFAULT); 683 } 684 685 return (ENXIO); 686} 687 688static void 689alc_get_macaddr(struct alc_softc *sc) 690{ 691 692 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 693 alc_get_macaddr_816x(sc); 694 else 695 alc_get_macaddr_813x(sc); 696} 697 698static void 699alc_get_macaddr_813x(struct alc_softc *sc) 700{ 701 uint32_t opt; 702 uint16_t val; 703 int eeprom, i; 704 705 eeprom = 0; 706 opt = CSR_READ_4(sc, ALC_OPT_CFG); 707 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 708 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 709 /* 710 * EEPROM found, let TWSI reload EEPROM configuration. 711 * This will set ethernet address of controller. 712 */ 713 eeprom++; 714 switch (sc->alc_ident->deviceid) { 715 case DEVICEID_ATHEROS_AR8131: 716 case DEVICEID_ATHEROS_AR8132: 717 if ((opt & OPT_CFG_CLK_ENB) == 0) { 718 opt |= OPT_CFG_CLK_ENB; 719 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 720 CSR_READ_4(sc, ALC_OPT_CFG); 721 DELAY(1000); 722 } 723 break; 724 case DEVICEID_ATHEROS_AR8151: 725 case DEVICEID_ATHEROS_AR8151_V2: 726 case DEVICEID_ATHEROS_AR8152_B: 727 case DEVICEID_ATHEROS_AR8152_B2: 728 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 729 ALC_MII_DBG_ADDR, 0x00); 730 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 731 ALC_MII_DBG_DATA); 732 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 733 ALC_MII_DBG_DATA, val & 0xFF7F); 734 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 735 ALC_MII_DBG_ADDR, 0x3B); 736 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 737 ALC_MII_DBG_DATA); 738 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 739 ALC_MII_DBG_DATA, val | 0x0008); 740 DELAY(20); 741 break; 742 } 743 744 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 745 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 746 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 747 CSR_READ_4(sc, ALC_WOL_CFG); 748 749 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 750 TWSI_CFG_SW_LD_START); 751 for (i = 100; i > 0; i--) { 752 DELAY(1000); 753 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 754 TWSI_CFG_SW_LD_START) == 0) 755 break; 756 } 757 if (i == 0) 758 device_printf(sc->alc_dev, 759 "reloading EEPROM timeout!\n"); 760 } else { 761 if (bootverbose) 762 device_printf(sc->alc_dev, "EEPROM not found!\n"); 763 } 764 if (eeprom != 0) { 765 switch (sc->alc_ident->deviceid) { 766 case DEVICEID_ATHEROS_AR8131: 767 case DEVICEID_ATHEROS_AR8132: 768 if ((opt & OPT_CFG_CLK_ENB) != 0) { 769 opt &= ~OPT_CFG_CLK_ENB; 770 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 771 CSR_READ_4(sc, ALC_OPT_CFG); 772 DELAY(1000); 773 } 774 break; 775 case DEVICEID_ATHEROS_AR8151: 776 case DEVICEID_ATHEROS_AR8151_V2: 777 case DEVICEID_ATHEROS_AR8152_B: 778 case DEVICEID_ATHEROS_AR8152_B2: 779 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 780 ALC_MII_DBG_ADDR, 0x00); 781 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 782 ALC_MII_DBG_DATA); 783 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 784 ALC_MII_DBG_DATA, val | 0x0080); 785 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 786 ALC_MII_DBG_ADDR, 0x3B); 787 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 788 ALC_MII_DBG_DATA); 789 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 790 ALC_MII_DBG_DATA, val & 0xFFF7); 791 DELAY(20); 792 break; 793 } 794 } 795 796 alc_get_macaddr_par(sc); 797} 798 799static void 800alc_get_macaddr_816x(struct alc_softc *sc) 801{ 802 uint32_t reg; 803 int i, reloaded; 804 805 reloaded = 0; 806 /* Try to reload station address via TWSI. */ 807 for (i = 100; i > 0; i--) { 808 reg = CSR_READ_4(sc, ALC_SLD); 809 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 810 break; 811 DELAY(1000); 812 } 813 if (i != 0) { 814 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 815 for (i = 100; i > 0; i--) { 816 DELAY(1000); 817 reg = CSR_READ_4(sc, ALC_SLD); 818 if ((reg & SLD_START) == 0) 819 break; 820 } 821 if (i != 0) 822 reloaded++; 823 else if (bootverbose) 824 device_printf(sc->alc_dev, 825 "reloading station address via TWSI timed out!\n"); 826 } 827 828 /* Try to reload station address from EEPROM or FLASH. */ 829 if (reloaded == 0) { 830 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 831 if ((reg & (EEPROM_LD_EEPROM_EXIST | 832 EEPROM_LD_FLASH_EXIST)) != 0) { 833 for (i = 100; i > 0; i--) { 834 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 835 if ((reg & (EEPROM_LD_PROGRESS | 836 EEPROM_LD_START)) == 0) 837 break; 838 DELAY(1000); 839 } 840 if (i != 0) { 841 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 842 EEPROM_LD_START); 843 for (i = 100; i > 0; i--) { 844 DELAY(1000); 845 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 846 if ((reg & EEPROM_LD_START) == 0) 847 break; 848 } 849 } else if (bootverbose) 850 device_printf(sc->alc_dev, 851 "reloading EEPROM/FLASH timed out!\n"); 852 } 853 } 854 855 alc_get_macaddr_par(sc); 856} 857 858static void 859alc_get_macaddr_par(struct alc_softc *sc) 860{ 861 uint32_t ea[2]; 862 863 ea[0] = CSR_READ_4(sc, ALC_PAR0); 864 ea[1] = CSR_READ_4(sc, ALC_PAR1); 865 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 866 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 867 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 868 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 869 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 870 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 871} 872 873static void 874alc_disable_l0s_l1(struct alc_softc *sc) 875{ 876 uint32_t pmcfg; 877 878 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 879 /* Another magic from vendor. */ 880 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 881 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 882 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 883 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 884 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 885 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 886 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 887 } 888} 889 890static void 891alc_phy_reset(struct alc_softc *sc) 892{ 893 894 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 895 alc_phy_reset_816x(sc); 896 else 897 alc_phy_reset_813x(sc); 898} 899 900static void 901alc_phy_reset_813x(struct alc_softc *sc) 902{ 903 uint16_t data; 904 905 /* Reset magic from Linux. */ 906 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 907 CSR_READ_2(sc, ALC_GPHY_CFG); 908 DELAY(10 * 1000); 909 910 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 911 GPHY_CFG_SEL_ANA_RESET); 912 CSR_READ_2(sc, ALC_GPHY_CFG); 913 DELAY(10 * 1000); 914 915 /* DSP fixup, Vendor magic. */ 916 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 917 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 918 ALC_MII_DBG_ADDR, 0x000A); 919 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 920 ALC_MII_DBG_DATA); 921 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 922 ALC_MII_DBG_DATA, data & 0xDFFF); 923 } 924 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 925 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 926 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 927 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 928 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 929 ALC_MII_DBG_ADDR, 0x003B); 930 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 931 ALC_MII_DBG_DATA); 932 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 933 ALC_MII_DBG_DATA, data & 0xFFF7); 934 DELAY(20 * 1000); 935 } 936 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 937 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 938 ALC_MII_DBG_ADDR, 0x0029); 939 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 940 ALC_MII_DBG_DATA, 0x929D); 941 } 942 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 943 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 944 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 945 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 946 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 947 ALC_MII_DBG_ADDR, 0x0029); 948 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 949 ALC_MII_DBG_DATA, 0xB6DD); 950 } 951 952 /* Load DSP codes, vendor magic. */ 953 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 954 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 955 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 956 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 957 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 958 ALC_MII_DBG_DATA, data); 959 960 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 961 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 962 ANA_SERDES_EN_LCKDT; 963 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 964 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 965 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 966 ALC_MII_DBG_DATA, data); 967 968 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 969 ANA_LONG_CABLE_TH_100_MASK) | 970 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 971 ANA_SHORT_CABLE_TH_100_SHIFT) | 972 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 973 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 974 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 975 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 976 ALC_MII_DBG_DATA, data); 977 978 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 979 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 980 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 981 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 982 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 983 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 984 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 985 ALC_MII_DBG_DATA, data); 986 987 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 988 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 989 ANA_OEN_125M; 990 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 991 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 992 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 993 ALC_MII_DBG_DATA, data); 994 DELAY(1000); 995 996 /* Disable hibernation. */ 997 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 998 0x0029); 999 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 1000 ALC_MII_DBG_DATA); 1001 data &= ~0x8000; 1002 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1003 data); 1004 1005 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 1006 0x000B); 1007 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 1008 ALC_MII_DBG_DATA); 1009 data &= ~0x8000; 1010 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1011 data); 1012} 1013 1014static void 1015alc_phy_reset_816x(struct alc_softc *sc) 1016{ 1017 uint32_t val; 1018 1019 val = CSR_READ_4(sc, ALC_GPHY_CFG); 1020 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1021 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 1022 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 1023 val |= GPHY_CFG_SEL_ANA_RESET; 1024#ifdef notyet 1025 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 1026#else 1027 /* Disable PHY hibernation. */ 1028 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 1029#endif 1030 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 1031 DELAY(10); 1032 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 1033 DELAY(800); 1034 1035 /* Vendor PHY magic. */ 1036#ifdef notyet 1037 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 1038 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 1039 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 1040 EXT_VDRVBIAS_DEFAULT); 1041#else 1042 /* Disable PHY hibernation. */ 1043 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 1044 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 1045 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 1046 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 1047 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 1048#endif 1049 1050 /* XXX Disable EEE. */ 1051 val = CSR_READ_4(sc, ALC_LPI_CTL); 1052 val &= ~LPI_CTL_ENB; 1053 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 1054 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 1055 1056 /* PHY power saving. */ 1057 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 1058 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 1059 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 1060 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 1061 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1062 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 1063 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1064 1065 /* RTL8139C, 120m issue. */ 1066 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 1067 ANEG_NLP78_120M_DEFAULT); 1068 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 1069 ANEG_S3DIG10_DEFAULT); 1070 1071 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 1072 /* Turn off half amplitude. */ 1073 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 1074 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 1075 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 1076 /* Turn off Green feature. */ 1077 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1078 val |= DBG_GREENCFG2_BP_GREEN; 1079 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1080 /* Turn off half bias. */ 1081 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 1082 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 1083 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 1084 } 1085} 1086 1087static void 1088alc_phy_down(struct alc_softc *sc) 1089{ 1090 uint32_t gphy; 1091 1092 switch (sc->alc_ident->deviceid) { 1093 case DEVICEID_ATHEROS_AR8161: 1094 case DEVICEID_ATHEROS_E2200: 1095 case DEVICEID_ATHEROS_E2400: 1096 case DEVICEID_ATHEROS_E2500: 1097 case DEVICEID_ATHEROS_AR8162: 1098 case DEVICEID_ATHEROS_AR8171: 1099 case DEVICEID_ATHEROS_AR8172: 1100 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 1101 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1102 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 1103 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 1104 GPHY_CFG_SEL_ANA_RESET; 1105 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 1106 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 1107 break; 1108 case DEVICEID_ATHEROS_AR8151: 1109 case DEVICEID_ATHEROS_AR8151_V2: 1110 case DEVICEID_ATHEROS_AR8152_B: 1111 case DEVICEID_ATHEROS_AR8152_B2: 1112 /* 1113 * GPHY power down caused more problems on AR8151 v2.0. 1114 * When driver is reloaded after GPHY power down, 1115 * accesses to PHY/MAC registers hung the system. Only 1116 * cold boot recovered from it. I'm not sure whether 1117 * AR8151 v1.0 also requires this one though. I don't 1118 * have AR8151 v1.0 controller in hand. 1119 * The only option left is to isolate the PHY and 1120 * initiates power down the PHY which in turn saves 1121 * more power when driver is unloaded. 1122 */ 1123 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1124 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1125 break; 1126 default: 1127 /* Force PHY down. */ 1128 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1129 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1130 GPHY_CFG_PWDOWN_HW); 1131 DELAY(1000); 1132 break; 1133 } 1134} 1135 1136static void 1137alc_aspm(struct alc_softc *sc, int init, int media) 1138{ 1139 1140 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1141 alc_aspm_816x(sc, init); 1142 else 1143 alc_aspm_813x(sc, media); 1144} 1145 1146static void 1147alc_aspm_813x(struct alc_softc *sc, int media) 1148{ 1149 uint32_t pmcfg; 1150 uint16_t linkcfg; 1151 1152 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1153 return; 1154 1155 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1156 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1157 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1158 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1159 PCIER_LINK_CTL); 1160 else 1161 linkcfg = 0; 1162 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1163 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1164 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1165 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1166 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1167 1168 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1169 /* Disable extended sync except AR8152 B v1.0 */ 1170 linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC; 1171 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1172 sc->alc_rev == ATHEROS_AR8152_B_V10) 1173 linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC; 1174 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, 1175 linkcfg); 1176 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1177 PM_CFG_HOTRST); 1178 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1179 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1180 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1181 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1182 PM_CFG_PM_REQ_TIMER_SHIFT); 1183 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1184 } 1185 1186 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1187 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1188 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1189 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1190 pmcfg |= PM_CFG_ASPM_L1_ENB; 1191 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1192 if (sc->alc_ident->deviceid == 1193 DEVICEID_ATHEROS_AR8152_B) 1194 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1195 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1196 PM_CFG_SERDES_PLL_L1_ENB | 1197 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1198 pmcfg |= PM_CFG_CLK_SWH_L1; 1199 if (media == IFM_100_TX || media == IFM_1000_T) { 1200 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1201 switch (sc->alc_ident->deviceid) { 1202 case DEVICEID_ATHEROS_AR8152_B: 1203 pmcfg |= (7 << 1204 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1205 break; 1206 case DEVICEID_ATHEROS_AR8152_B2: 1207 case DEVICEID_ATHEROS_AR8151_V2: 1208 pmcfg |= (4 << 1209 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1210 break; 1211 default: 1212 pmcfg |= (15 << 1213 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1214 break; 1215 } 1216 } 1217 } else { 1218 pmcfg |= PM_CFG_SERDES_L1_ENB | 1219 PM_CFG_SERDES_PLL_L1_ENB | 1220 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1221 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1222 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1223 } 1224 } else { 1225 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1226 PM_CFG_SERDES_PLL_L1_ENB); 1227 pmcfg |= PM_CFG_CLK_SWH_L1; 1228 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1229 pmcfg |= PM_CFG_ASPM_L1_ENB; 1230 } 1231 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1232} 1233 1234static void 1235alc_aspm_816x(struct alc_softc *sc, int init) 1236{ 1237 uint32_t pmcfg; 1238 1239 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1240 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1241 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1242 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1243 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1244 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1245 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1246 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1247 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1248 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1249 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1250 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1251 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1252 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1253 (sc->alc_rev & 0x01) != 0) 1254 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1255 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1256 /* Link up, enable both L0s, L1s. */ 1257 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1258 PM_CFG_MAC_ASPM_CHK; 1259 } else { 1260 if (init != 0) 1261 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1262 PM_CFG_MAC_ASPM_CHK; 1263 else if ((sc->alc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1264 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1265 } 1266 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1267} 1268 1269static void 1270alc_init_pcie(struct alc_softc *sc) 1271{ 1272 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1273 uint32_t cap, ctl, val; 1274 int state; 1275 1276 /* Clear data link and flow-control protocol error. */ 1277 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1278 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1279 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1280 1281 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1282 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1283 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1284 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1285 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1286 PCIE_PHYMISC_FORCE_RCV_DET); 1287 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1288 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1289 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1290 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1291 PCIE_PHYMISC2_SERDES_TH_MASK); 1292 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1293 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1294 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1295 } 1296 /* Disable ASPM L0S and L1. */ 1297 cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP); 1298 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1299 ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL); 1300 if ((ctl & PCIEM_LINK_CTL_RCB) != 0) 1301 sc->alc_rcb = DMA_CFG_RCB_128; 1302 if (bootverbose) 1303 device_printf(sc->alc_dev, "RCB %u bytes\n", 1304 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1305 state = ctl & PCIEM_LINK_CTL_ASPMC; 1306 if (state & PCIEM_LINK_CTL_ASPMC_L0S) 1307 sc->alc_flags |= ALC_FLAG_L0S; 1308 if (state & PCIEM_LINK_CTL_ASPMC_L1) 1309 sc->alc_flags |= ALC_FLAG_L1S; 1310 if (bootverbose) 1311 device_printf(sc->alc_dev, "ASPM %s %s\n", 1312 aspm_state[state], 1313 state == 0 ? "disabled" : "enabled"); 1314 alc_disable_l0s_l1(sc); 1315 } else { 1316 if (bootverbose) 1317 device_printf(sc->alc_dev, 1318 "no ASPM support\n"); 1319 } 1320 } else { 1321 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1322 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1323 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1324 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1325 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1326 (sc->alc_rev & 0x01) != 0) { 1327 if ((val & MASTER_WAKEN_25M) == 0 || 1328 (val & MASTER_CLK_SEL_DIS) == 0) { 1329 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1330 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1331 } 1332 } else { 1333 if ((val & MASTER_WAKEN_25M) == 0 || 1334 (val & MASTER_CLK_SEL_DIS) != 0) { 1335 val |= MASTER_WAKEN_25M; 1336 val &= ~MASTER_CLK_SEL_DIS; 1337 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1338 } 1339 } 1340 } 1341 alc_aspm(sc, 1, IFM_UNKNOWN); 1342} 1343 1344static void 1345alc_config_msi(struct alc_softc *sc) 1346{ 1347 uint32_t ctl, mod; 1348 1349 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 1350 /* 1351 * It seems interrupt moderation is controlled by 1352 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. 1353 * Driver uses RX interrupt moderation parameter to 1354 * program ALC_MSI_RETRANS_TIMER register. 1355 */ 1356 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); 1357 ctl &= ~MSI_RETRANS_TIMER_MASK; 1358 ctl &= ~MSI_RETRANS_MASK_SEL_LINE; 1359 mod = ALC_USECS(sc->alc_int_rx_mod); 1360 if (mod == 0) 1361 mod = 1; 1362 ctl |= mod; 1363 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1364 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1365 MSI_RETRANS_MASK_SEL_STD); 1366 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1367 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1368 MSI_RETRANS_MASK_SEL_LINE); 1369 else 1370 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); 1371 } 1372} 1373 1374static int 1375alc_attach(device_t dev) 1376{ 1377 struct alc_softc *sc; 1378 struct ifnet *ifp; 1379 int base, error, i, msic, msixc; 1380 uint16_t burst; 1381 1382 error = 0; 1383 sc = device_get_softc(dev); 1384 sc->alc_dev = dev; 1385 sc->alc_rev = pci_get_revid(dev); 1386 1387 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1388 MTX_DEF); 1389 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 1390 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 1391 sc->alc_ident = alc_find_ident(dev); 1392 1393 /* Map the device. */ 1394 pci_enable_busmaster(dev); 1395 sc->alc_res_spec = alc_res_spec_mem; 1396 sc->alc_irq_spec = alc_irq_spec_legacy; 1397 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 1398 if (error != 0) { 1399 device_printf(dev, "cannot allocate memory resources.\n"); 1400 goto fail; 1401 } 1402 1403 /* Set PHY address. */ 1404 sc->alc_phyaddr = ALC_PHY_ADDR; 1405 1406 /* 1407 * One odd thing is AR8132 uses the same PHY hardware(F1 1408 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1409 * the PHY supports 1000Mbps but that's not true. The PHY 1410 * used in AR8132 can't establish gigabit link even if it 1411 * shows the same PHY model/revision number of AR8131. 1412 */ 1413 switch (sc->alc_ident->deviceid) { 1414 case DEVICEID_ATHEROS_E2200: 1415 case DEVICEID_ATHEROS_E2400: 1416 case DEVICEID_ATHEROS_E2500: 1417 sc->alc_flags |= ALC_FLAG_E2X00; 1418 /* FALLTHROUGH */ 1419 case DEVICEID_ATHEROS_AR8161: 1420 if (pci_get_subvendor(dev) == VENDORID_ATHEROS && 1421 pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0) 1422 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1423 /* FALLTHROUGH */ 1424 case DEVICEID_ATHEROS_AR8171: 1425 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1426 break; 1427 case DEVICEID_ATHEROS_AR8162: 1428 case DEVICEID_ATHEROS_AR8172: 1429 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1430 break; 1431 case DEVICEID_ATHEROS_AR8152_B: 1432 case DEVICEID_ATHEROS_AR8152_B2: 1433 sc->alc_flags |= ALC_FLAG_APS; 1434 /* FALLTHROUGH */ 1435 case DEVICEID_ATHEROS_AR8132: 1436 sc->alc_flags |= ALC_FLAG_FASTETHER; 1437 break; 1438 case DEVICEID_ATHEROS_AR8151: 1439 case DEVICEID_ATHEROS_AR8151_V2: 1440 sc->alc_flags |= ALC_FLAG_APS; 1441 if (CSR_READ_4(sc, ALC_MT_MAGIC) == MT_MAGIC) 1442 sc->alc_flags |= ALC_FLAG_MT; 1443 /* FALLTHROUGH */ 1444 default: 1445 break; 1446 } 1447 sc->alc_flags |= ALC_FLAG_JUMBO; 1448 1449 /* 1450 * It seems that AR813x/AR815x has silicon bug for SMB. In 1451 * addition, Atheros said that enabling SMB wouldn't improve 1452 * performance. However I think it's bad to access lots of 1453 * registers to extract MAC statistics. 1454 */ 1455 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1456 /* 1457 * Don't use Tx CMB. It is known to have silicon bug. 1458 */ 1459 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1460 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1461 MASTER_CHIP_REV_SHIFT; 1462 if (bootverbose) { 1463 device_printf(dev, "PCI device revision : 0x%04x\n", 1464 sc->alc_rev); 1465 device_printf(dev, "Chip id/revision : 0x%04x\n", 1466 sc->alc_chip_rev); 1467 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1468 device_printf(dev, "AR816x revision : 0x%x\n", 1469 AR816X_REV(sc->alc_rev)); 1470 } 1471 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 1472 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1473 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1474 1475 /* Initialize DMA parameters. */ 1476 sc->alc_dma_rd_burst = 0; 1477 sc->alc_dma_wr_burst = 0; 1478 sc->alc_rcb = DMA_CFG_RCB_64; 1479 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { 1480 sc->alc_flags |= ALC_FLAG_PCIE; 1481 sc->alc_expcap = base; 1482 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); 1483 sc->alc_dma_rd_burst = 1484 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; 1485 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; 1486 if (bootverbose) { 1487 device_printf(dev, "Read request size : %u bytes.\n", 1488 alc_dma_burst[sc->alc_dma_rd_burst]); 1489 device_printf(dev, "TLP payload size : %u bytes.\n", 1490 alc_dma_burst[sc->alc_dma_wr_burst]); 1491 } 1492 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1493 sc->alc_dma_rd_burst = 3; 1494 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1495 sc->alc_dma_wr_burst = 3; 1496 /* 1497 * Force maximum payload size to 128 bytes for 1498 * E2200/E2400/E2500. 1499 * Otherwise it triggers DMA write error. 1500 */ 1501 if ((sc->alc_flags & ALC_FLAG_E2X00) != 0) 1502 sc->alc_dma_wr_burst = 0; 1503 alc_init_pcie(sc); 1504 } 1505 1506 /* Reset PHY. */ 1507 alc_phy_reset(sc); 1508 1509 /* Reset the ethernet controller. */ 1510 alc_stop_mac(sc); 1511 alc_reset(sc); 1512 1513 /* Allocate IRQ resources. */ 1514 msixc = pci_msix_count(dev); 1515 msic = pci_msi_count(dev); 1516 if (bootverbose) { 1517 device_printf(dev, "MSIX count : %d\n", msixc); 1518 device_printf(dev, "MSI count : %d\n", msic); 1519 } 1520 if (msixc > 1) 1521 msixc = 1; 1522 if (msic > 1) 1523 msic = 1; 1524 /* 1525 * Prefer MSIX over MSI. 1526 * AR816x controller has a silicon bug that MSI interrupt 1527 * does not assert if PCIM_CMD_INTxDIS bit of command 1528 * register is set. pci(4) was taught to handle that case. 1529 */ 1530 if (msix_disable == 0 || msi_disable == 0) { 1531 if (msix_disable == 0 && msixc > 0 && 1532 pci_alloc_msix(dev, &msixc) == 0) { 1533 if (msic == 1) { 1534 device_printf(dev, 1535 "Using %d MSIX message(s).\n", msixc); 1536 sc->alc_flags |= ALC_FLAG_MSIX; 1537 sc->alc_irq_spec = alc_irq_spec_msix; 1538 } else 1539 pci_release_msi(dev); 1540 } 1541 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 1542 msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 1543 if (msic == 1) { 1544 device_printf(dev, 1545 "Using %d MSI message(s).\n", msic); 1546 sc->alc_flags |= ALC_FLAG_MSI; 1547 sc->alc_irq_spec = alc_irq_spec_msi; 1548 } else 1549 pci_release_msi(dev); 1550 } 1551 } 1552 1553 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1554 if (error != 0) { 1555 device_printf(dev, "cannot allocate IRQ resources.\n"); 1556 goto fail; 1557 } 1558 1559 /* Create device sysctl node. */ 1560 alc_sysctl_node(sc); 1561 1562 if ((error = alc_dma_alloc(sc)) != 0) 1563 goto fail; 1564 1565 /* Load station address. */ 1566 alc_get_macaddr(sc); 1567 1568 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 1569 if (ifp == NULL) { 1570 device_printf(dev, "cannot allocate ifnet structure.\n"); 1571 error = ENXIO; 1572 goto fail; 1573 } 1574 1575 ifp->if_softc = sc; 1576 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1577 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1578 ifp->if_ioctl = alc_ioctl; 1579 ifp->if_start = alc_start; 1580 ifp->if_init = alc_init; 1581 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1; 1582 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1583 IFQ_SET_READY(&ifp->if_snd); 1584 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1585 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 1586 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) { 1587 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 1588 sc->alc_flags |= ALC_FLAG_PM; 1589 sc->alc_pmcap = base; 1590 } 1591 ifp->if_capenable = ifp->if_capabilities; 1592 1593 /* Set up MII bus. */ 1594 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, 1595 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, 1596 MIIF_DOPAUSE); 1597 if (error != 0) { 1598 device_printf(dev, "attaching PHYs failed\n"); 1599 goto fail; 1600 } 1601 1602 ether_ifattach(ifp, sc->alc_eaddr); 1603 1604 /* VLAN capability setup. */ 1605 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 1606 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 1607 ifp->if_capenable = ifp->if_capabilities; 1608 /* 1609 * XXX 1610 * It seems enabling Tx checksum offloading makes more trouble. 1611 * Sometimes the controller does not receive any frames when 1612 * Tx checksum offloading is enabled. I'm not sure whether this 1613 * is a bug in Tx checksum offloading logic or I got broken 1614 * sample boards. To safety, don't enable Tx checksum offloading 1615 * by default but give chance to users to toggle it if they know 1616 * their controllers work without problems. 1617 * Fortunately, Tx checksum offloading for AR816x family 1618 * seems to work. 1619 */ 1620 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1621 ifp->if_capenable &= ~IFCAP_TXCSUM; 1622 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 1623 } 1624 1625 /* Tell the upper layer(s) we support long frames. */ 1626 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1627 1628 /* Create local taskq. */ 1629 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1630 taskqueue_thread_enqueue, &sc->alc_tq); 1631 if (sc->alc_tq == NULL) { 1632 device_printf(dev, "could not create taskqueue.\n"); 1633 ether_ifdetach(ifp); 1634 error = ENXIO; 1635 goto fail; 1636 } 1637 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1638 device_get_nameunit(sc->alc_dev)); 1639 1640 alc_config_msi(sc); 1641 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1642 msic = ALC_MSIX_MESSAGES; 1643 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1644 msic = ALC_MSI_MESSAGES; 1645 else 1646 msic = 1; 1647 for (i = 0; i < msic; i++) { 1648 error = bus_setup_intr(dev, sc->alc_irq[i], 1649 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1650 &sc->alc_intrhand[i]); 1651 if (error != 0) 1652 break; 1653 } 1654 if (error != 0) { 1655 device_printf(dev, "could not set up interrupt handler.\n"); 1656 taskqueue_free(sc->alc_tq); 1657 sc->alc_tq = NULL; 1658 ether_ifdetach(ifp); 1659 goto fail; 1660 } 1661 1662 /* Attach driver netdump methods. */ 1663 NETDUMP_SET(ifp, alc); 1664 1665fail: 1666 if (error != 0) 1667 alc_detach(dev); 1668 1669 return (error); 1670} 1671 1672static int 1673alc_detach(device_t dev) 1674{ 1675 struct alc_softc *sc; 1676 struct ifnet *ifp; 1677 int i, msic; 1678 1679 sc = device_get_softc(dev); 1680 1681 ifp = sc->alc_ifp; 1682 if (device_is_attached(dev)) { 1683 ether_ifdetach(ifp); 1684 ALC_LOCK(sc); 1685 alc_stop(sc); 1686 ALC_UNLOCK(sc); 1687 callout_drain(&sc->alc_tick_ch); 1688 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1689 } 1690 1691 if (sc->alc_tq != NULL) { 1692 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1693 taskqueue_free(sc->alc_tq); 1694 sc->alc_tq = NULL; 1695 } 1696 1697 if (sc->alc_miibus != NULL) { 1698 device_delete_child(dev, sc->alc_miibus); 1699 sc->alc_miibus = NULL; 1700 } 1701 bus_generic_detach(dev); 1702 alc_dma_free(sc); 1703 1704 if (ifp != NULL) { 1705 if_free(ifp); 1706 sc->alc_ifp = NULL; 1707 } 1708 1709 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1710 msic = ALC_MSIX_MESSAGES; 1711 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1712 msic = ALC_MSI_MESSAGES; 1713 else 1714 msic = 1; 1715 for (i = 0; i < msic; i++) { 1716 if (sc->alc_intrhand[i] != NULL) { 1717 bus_teardown_intr(dev, sc->alc_irq[i], 1718 sc->alc_intrhand[i]); 1719 sc->alc_intrhand[i] = NULL; 1720 } 1721 } 1722 if (sc->alc_res[0] != NULL) 1723 alc_phy_down(sc); 1724 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1725 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1726 pci_release_msi(dev); 1727 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1728 mtx_destroy(&sc->alc_mtx); 1729 1730 return (0); 1731} 1732 1733#define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1734 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1735#define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1736 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1737 1738static void 1739alc_sysctl_node(struct alc_softc *sc) 1740{ 1741 struct sysctl_ctx_list *ctx; 1742 struct sysctl_oid_list *child, *parent; 1743 struct sysctl_oid *tree; 1744 struct alc_hw_stats *stats; 1745 int error; 1746 1747 stats = &sc->alc_stats; 1748 ctx = device_get_sysctl_ctx(sc->alc_dev); 1749 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1750 1751 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1752 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 1753 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1754 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1755 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 1756 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1757 /* Pull in device tunables. */ 1758 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1759 error = resource_int_value(device_get_name(sc->alc_dev), 1760 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1761 if (error == 0) { 1762 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1763 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1764 device_printf(sc->alc_dev, "int_rx_mod value out of " 1765 "range; using default: %d\n", 1766 ALC_IM_RX_TIMER_DEFAULT); 1767 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1768 } 1769 } 1770 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1771 error = resource_int_value(device_get_name(sc->alc_dev), 1772 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1773 if (error == 0) { 1774 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1775 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1776 device_printf(sc->alc_dev, "int_tx_mod value out of " 1777 "range; using default: %d\n", 1778 ALC_IM_TX_TIMER_DEFAULT); 1779 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1780 } 1781 } 1782 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1783 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 1784 sysctl_hw_alc_proc_limit, "I", 1785 "max number of Rx events to process"); 1786 /* Pull in device tunables. */ 1787 sc->alc_process_limit = ALC_PROC_DEFAULT; 1788 error = resource_int_value(device_get_name(sc->alc_dev), 1789 device_get_unit(sc->alc_dev), "process_limit", 1790 &sc->alc_process_limit); 1791 if (error == 0) { 1792 if (sc->alc_process_limit < ALC_PROC_MIN || 1793 sc->alc_process_limit > ALC_PROC_MAX) { 1794 device_printf(sc->alc_dev, 1795 "process_limit value out of range; " 1796 "using default: %d\n", ALC_PROC_DEFAULT); 1797 sc->alc_process_limit = ALC_PROC_DEFAULT; 1798 } 1799 } 1800 1801 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1802 NULL, "ALC statistics"); 1803 parent = SYSCTL_CHILDREN(tree); 1804 1805 /* Rx statistics. */ 1806 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1807 NULL, "Rx MAC statistics"); 1808 child = SYSCTL_CHILDREN(tree); 1809 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1810 &stats->rx_frames, "Good frames"); 1811 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1812 &stats->rx_bcast_frames, "Good broadcast frames"); 1813 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1814 &stats->rx_mcast_frames, "Good multicast frames"); 1815 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1816 &stats->rx_pause_frames, "Pause control frames"); 1817 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1818 &stats->rx_control_frames, "Control frames"); 1819 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1820 &stats->rx_crcerrs, "CRC errors"); 1821 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1822 &stats->rx_lenerrs, "Frames with length mismatched"); 1823 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1824 &stats->rx_bytes, "Good octets"); 1825 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1826 &stats->rx_bcast_bytes, "Good broadcast octets"); 1827 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1828 &stats->rx_mcast_bytes, "Good multicast octets"); 1829 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1830 &stats->rx_runts, "Too short frames"); 1831 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1832 &stats->rx_fragments, "Fragmented frames"); 1833 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1834 &stats->rx_pkts_64, "64 bytes frames"); 1835 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1836 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1837 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1838 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1839 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1840 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1841 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1842 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1843 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1844 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1845 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1846 &stats->rx_pkts_1519_max, "1519 to max frames"); 1847 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1848 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1849 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1850 &stats->rx_fifo_oflows, "FIFO overflows"); 1851 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1852 &stats->rx_rrs_errs, "Return status write-back errors"); 1853 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1854 &stats->rx_alignerrs, "Alignment errors"); 1855 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1856 &stats->rx_pkts_filtered, 1857 "Frames dropped due to address filtering"); 1858 1859 /* Tx statistics. */ 1860 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1861 NULL, "Tx MAC statistics"); 1862 child = SYSCTL_CHILDREN(tree); 1863 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1864 &stats->tx_frames, "Good frames"); 1865 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1866 &stats->tx_bcast_frames, "Good broadcast frames"); 1867 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1868 &stats->tx_mcast_frames, "Good multicast frames"); 1869 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1870 &stats->tx_pause_frames, "Pause control frames"); 1871 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1872 &stats->tx_control_frames, "Control frames"); 1873 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1874 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1875 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1876 &stats->tx_excess_defer, "Frames with derferrals"); 1877 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1878 &stats->tx_bytes, "Good octets"); 1879 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1880 &stats->tx_bcast_bytes, "Good broadcast octets"); 1881 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1882 &stats->tx_mcast_bytes, "Good multicast octets"); 1883 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1884 &stats->tx_pkts_64, "64 bytes frames"); 1885 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1886 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1887 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1888 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1889 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1890 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1891 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1892 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1893 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1894 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1895 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1896 &stats->tx_pkts_1519_max, "1519 to max frames"); 1897 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1898 &stats->tx_single_colls, "Single collisions"); 1899 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1900 &stats->tx_multi_colls, "Multiple collisions"); 1901 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1902 &stats->tx_late_colls, "Late collisions"); 1903 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1904 &stats->tx_excess_colls, "Excessive collisions"); 1905 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1906 &stats->tx_underrun, "FIFO underruns"); 1907 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1908 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1909 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1910 &stats->tx_lenerrs, "Frames with length mismatched"); 1911 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1912 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1913} 1914 1915#undef ALC_SYSCTL_STAT_ADD32 1916#undef ALC_SYSCTL_STAT_ADD64 1917 1918struct alc_dmamap_arg { 1919 bus_addr_t alc_busaddr; 1920}; 1921 1922static void 1923alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1924{ 1925 struct alc_dmamap_arg *ctx; 1926 1927 if (error != 0) 1928 return; 1929 1930 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1931 1932 ctx = (struct alc_dmamap_arg *)arg; 1933 ctx->alc_busaddr = segs[0].ds_addr; 1934} 1935 1936/* 1937 * Normal and high Tx descriptors shares single Tx high address. 1938 * Four Rx descriptor/return rings and CMB shares the same Rx 1939 * high address. 1940 */ 1941static int 1942alc_check_boundary(struct alc_softc *sc) 1943{ 1944 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1945 1946 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1947 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1948 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1949 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1950 1951 /* 4GB boundary crossing is not allowed. */ 1952 if ((ALC_ADDR_HI(rx_ring_end) != 1953 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1954 (ALC_ADDR_HI(rr_ring_end) != 1955 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1956 (ALC_ADDR_HI(cmb_end) != 1957 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1958 (ALC_ADDR_HI(tx_ring_end) != 1959 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1960 return (EFBIG); 1961 /* 1962 * Make sure Rx return descriptor/Rx descriptor/CMB use 1963 * the same high address. 1964 */ 1965 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1966 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1967 return (EFBIG); 1968 1969 return (0); 1970} 1971 1972static int 1973alc_dma_alloc(struct alc_softc *sc) 1974{ 1975 struct alc_txdesc *txd; 1976 struct alc_rxdesc *rxd; 1977 bus_addr_t lowaddr; 1978 struct alc_dmamap_arg ctx; 1979 int error, i; 1980 1981 lowaddr = BUS_SPACE_MAXADDR; 1982 if (sc->alc_flags & ALC_FLAG_MT) 1983 lowaddr = BUS_SPACE_MAXSIZE_32BIT; 1984again: 1985 /* Create parent DMA tag. */ 1986 error = bus_dma_tag_create( 1987 bus_get_dma_tag(sc->alc_dev), /* parent */ 1988 1, 0, /* alignment, boundary */ 1989 lowaddr, /* lowaddr */ 1990 BUS_SPACE_MAXADDR, /* highaddr */ 1991 NULL, NULL, /* filter, filterarg */ 1992 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1993 0, /* nsegments */ 1994 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1995 0, /* flags */ 1996 NULL, NULL, /* lockfunc, lockarg */ 1997 &sc->alc_cdata.alc_parent_tag); 1998 if (error != 0) { 1999 device_printf(sc->alc_dev, 2000 "could not create parent DMA tag.\n"); 2001 goto fail; 2002 } 2003 2004 /* Create DMA tag for Tx descriptor ring. */ 2005 error = bus_dma_tag_create( 2006 sc->alc_cdata.alc_parent_tag, /* parent */ 2007 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 2008 BUS_SPACE_MAXADDR, /* lowaddr */ 2009 BUS_SPACE_MAXADDR, /* highaddr */ 2010 NULL, NULL, /* filter, filterarg */ 2011 ALC_TX_RING_SZ, /* maxsize */ 2012 1, /* nsegments */ 2013 ALC_TX_RING_SZ, /* maxsegsize */ 2014 0, /* flags */ 2015 NULL, NULL, /* lockfunc, lockarg */ 2016 &sc->alc_cdata.alc_tx_ring_tag); 2017 if (error != 0) { 2018 device_printf(sc->alc_dev, 2019 "could not create Tx ring DMA tag.\n"); 2020 goto fail; 2021 } 2022 2023 /* Create DMA tag for Rx free descriptor ring. */ 2024 error = bus_dma_tag_create( 2025 sc->alc_cdata.alc_parent_tag, /* parent */ 2026 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 2027 BUS_SPACE_MAXADDR, /* lowaddr */ 2028 BUS_SPACE_MAXADDR, /* highaddr */ 2029 NULL, NULL, /* filter, filterarg */ 2030 ALC_RX_RING_SZ, /* maxsize */ 2031 1, /* nsegments */ 2032 ALC_RX_RING_SZ, /* maxsegsize */ 2033 0, /* flags */ 2034 NULL, NULL, /* lockfunc, lockarg */ 2035 &sc->alc_cdata.alc_rx_ring_tag); 2036 if (error != 0) { 2037 device_printf(sc->alc_dev, 2038 "could not create Rx ring DMA tag.\n"); 2039 goto fail; 2040 } 2041 /* Create DMA tag for Rx return descriptor ring. */ 2042 error = bus_dma_tag_create( 2043 sc->alc_cdata.alc_parent_tag, /* parent */ 2044 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 2045 BUS_SPACE_MAXADDR, /* lowaddr */ 2046 BUS_SPACE_MAXADDR, /* highaddr */ 2047 NULL, NULL, /* filter, filterarg */ 2048 ALC_RR_RING_SZ, /* maxsize */ 2049 1, /* nsegments */ 2050 ALC_RR_RING_SZ, /* maxsegsize */ 2051 0, /* flags */ 2052 NULL, NULL, /* lockfunc, lockarg */ 2053 &sc->alc_cdata.alc_rr_ring_tag); 2054 if (error != 0) { 2055 device_printf(sc->alc_dev, 2056 "could not create Rx return ring DMA tag.\n"); 2057 goto fail; 2058 } 2059 2060 /* Create DMA tag for coalescing message block. */ 2061 error = bus_dma_tag_create( 2062 sc->alc_cdata.alc_parent_tag, /* parent */ 2063 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 2064 BUS_SPACE_MAXADDR, /* lowaddr */ 2065 BUS_SPACE_MAXADDR, /* highaddr */ 2066 NULL, NULL, /* filter, filterarg */ 2067 ALC_CMB_SZ, /* maxsize */ 2068 1, /* nsegments */ 2069 ALC_CMB_SZ, /* maxsegsize */ 2070 0, /* flags */ 2071 NULL, NULL, /* lockfunc, lockarg */ 2072 &sc->alc_cdata.alc_cmb_tag); 2073 if (error != 0) { 2074 device_printf(sc->alc_dev, 2075 "could not create CMB DMA tag.\n"); 2076 goto fail; 2077 } 2078 /* Create DMA tag for status message block. */ 2079 error = bus_dma_tag_create( 2080 sc->alc_cdata.alc_parent_tag, /* parent */ 2081 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 2082 BUS_SPACE_MAXADDR, /* lowaddr */ 2083 BUS_SPACE_MAXADDR, /* highaddr */ 2084 NULL, NULL, /* filter, filterarg */ 2085 ALC_SMB_SZ, /* maxsize */ 2086 1, /* nsegments */ 2087 ALC_SMB_SZ, /* maxsegsize */ 2088 0, /* flags */ 2089 NULL, NULL, /* lockfunc, lockarg */ 2090 &sc->alc_cdata.alc_smb_tag); 2091 if (error != 0) { 2092 device_printf(sc->alc_dev, 2093 "could not create SMB DMA tag.\n"); 2094 goto fail; 2095 } 2096 2097 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2098 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 2099 (void **)&sc->alc_rdata.alc_tx_ring, 2100 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2101 &sc->alc_cdata.alc_tx_ring_map); 2102 if (error != 0) { 2103 device_printf(sc->alc_dev, 2104 "could not allocate DMA'able memory for Tx ring.\n"); 2105 goto fail; 2106 } 2107 ctx.alc_busaddr = 0; 2108 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 2109 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 2110 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2111 if (error != 0 || ctx.alc_busaddr == 0) { 2112 device_printf(sc->alc_dev, 2113 "could not load DMA'able memory for Tx ring.\n"); 2114 goto fail; 2115 } 2116 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 2117 2118 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2119 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 2120 (void **)&sc->alc_rdata.alc_rx_ring, 2121 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2122 &sc->alc_cdata.alc_rx_ring_map); 2123 if (error != 0) { 2124 device_printf(sc->alc_dev, 2125 "could not allocate DMA'able memory for Rx ring.\n"); 2126 goto fail; 2127 } 2128 ctx.alc_busaddr = 0; 2129 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 2130 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 2131 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2132 if (error != 0 || ctx.alc_busaddr == 0) { 2133 device_printf(sc->alc_dev, 2134 "could not load DMA'able memory for Rx ring.\n"); 2135 goto fail; 2136 } 2137 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 2138 2139 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 2140 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 2141 (void **)&sc->alc_rdata.alc_rr_ring, 2142 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2143 &sc->alc_cdata.alc_rr_ring_map); 2144 if (error != 0) { 2145 device_printf(sc->alc_dev, 2146 "could not allocate DMA'able memory for Rx return ring.\n"); 2147 goto fail; 2148 } 2149 ctx.alc_busaddr = 0; 2150 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 2151 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 2152 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 2153 if (error != 0 || ctx.alc_busaddr == 0) { 2154 device_printf(sc->alc_dev, 2155 "could not load DMA'able memory for Tx ring.\n"); 2156 goto fail; 2157 } 2158 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 2159 2160 /* Allocate DMA'able memory and load the DMA map for CMB. */ 2161 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 2162 (void **)&sc->alc_rdata.alc_cmb, 2163 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2164 &sc->alc_cdata.alc_cmb_map); 2165 if (error != 0) { 2166 device_printf(sc->alc_dev, 2167 "could not allocate DMA'able memory for CMB.\n"); 2168 goto fail; 2169 } 2170 ctx.alc_busaddr = 0; 2171 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 2172 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 2173 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 2174 if (error != 0 || ctx.alc_busaddr == 0) { 2175 device_printf(sc->alc_dev, 2176 "could not load DMA'able memory for CMB.\n"); 2177 goto fail; 2178 } 2179 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 2180 2181 /* Allocate DMA'able memory and load the DMA map for SMB. */ 2182 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 2183 (void **)&sc->alc_rdata.alc_smb, 2184 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2185 &sc->alc_cdata.alc_smb_map); 2186 if (error != 0) { 2187 device_printf(sc->alc_dev, 2188 "could not allocate DMA'able memory for SMB.\n"); 2189 goto fail; 2190 } 2191 ctx.alc_busaddr = 0; 2192 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 2193 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 2194 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 2195 if (error != 0 || ctx.alc_busaddr == 0) { 2196 device_printf(sc->alc_dev, 2197 "could not load DMA'able memory for CMB.\n"); 2198 goto fail; 2199 } 2200 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 2201 2202 /* Make sure we've not crossed 4GB boundary. */ 2203 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 2204 (error = alc_check_boundary(sc)) != 0) { 2205 device_printf(sc->alc_dev, "4GB boundary crossed, " 2206 "switching to 32bit DMA addressing mode.\n"); 2207 alc_dma_free(sc); 2208 /* 2209 * Limit max allowable DMA address space to 32bit 2210 * and try again. 2211 */ 2212 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2213 goto again; 2214 } 2215 2216 /* 2217 * Create Tx buffer parent tag. 2218 * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers 2219 * so it needs separate parent DMA tag as parent DMA address 2220 * space could be restricted to be within 32bit address space 2221 * by 4GB boundary crossing. 2222 */ 2223 error = bus_dma_tag_create( 2224 bus_get_dma_tag(sc->alc_dev), /* parent */ 2225 1, 0, /* alignment, boundary */ 2226 lowaddr, /* lowaddr */ 2227 BUS_SPACE_MAXADDR, /* highaddr */ 2228 NULL, NULL, /* filter, filterarg */ 2229 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2230 0, /* nsegments */ 2231 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2232 0, /* flags */ 2233 NULL, NULL, /* lockfunc, lockarg */ 2234 &sc->alc_cdata.alc_buffer_tag); 2235 if (error != 0) { 2236 device_printf(sc->alc_dev, 2237 "could not create parent buffer DMA tag.\n"); 2238 goto fail; 2239 } 2240 2241 /* Create DMA tag for Tx buffers. */ 2242 error = bus_dma_tag_create( 2243 sc->alc_cdata.alc_buffer_tag, /* parent */ 2244 1, 0, /* alignment, boundary */ 2245 BUS_SPACE_MAXADDR, /* lowaddr */ 2246 BUS_SPACE_MAXADDR, /* highaddr */ 2247 NULL, NULL, /* filter, filterarg */ 2248 ALC_TSO_MAXSIZE, /* maxsize */ 2249 ALC_MAXTXSEGS, /* nsegments */ 2250 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 2251 0, /* flags */ 2252 NULL, NULL, /* lockfunc, lockarg */ 2253 &sc->alc_cdata.alc_tx_tag); 2254 if (error != 0) { 2255 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 2256 goto fail; 2257 } 2258 2259 /* Create DMA tag for Rx buffers. */ 2260 error = bus_dma_tag_create( 2261 sc->alc_cdata.alc_buffer_tag, /* parent */ 2262 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 2263 BUS_SPACE_MAXADDR, /* lowaddr */ 2264 BUS_SPACE_MAXADDR, /* highaddr */ 2265 NULL, NULL, /* filter, filterarg */ 2266 MCLBYTES, /* maxsize */ 2267 1, /* nsegments */ 2268 MCLBYTES, /* maxsegsize */ 2269 0, /* flags */ 2270 NULL, NULL, /* lockfunc, lockarg */ 2271 &sc->alc_cdata.alc_rx_tag); 2272 if (error != 0) { 2273 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 2274 goto fail; 2275 } 2276 /* Create DMA maps for Tx buffers. */ 2277 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2278 txd = &sc->alc_cdata.alc_txdesc[i]; 2279 txd->tx_m = NULL; 2280 txd->tx_dmamap = NULL; 2281 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 2282 &txd->tx_dmamap); 2283 if (error != 0) { 2284 device_printf(sc->alc_dev, 2285 "could not create Tx dmamap.\n"); 2286 goto fail; 2287 } 2288 } 2289 /* Create DMA maps for Rx buffers. */ 2290 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2291 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 2292 device_printf(sc->alc_dev, 2293 "could not create spare Rx dmamap.\n"); 2294 goto fail; 2295 } 2296 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2297 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2298 rxd->rx_m = NULL; 2299 rxd->rx_dmamap = NULL; 2300 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2301 &rxd->rx_dmamap); 2302 if (error != 0) { 2303 device_printf(sc->alc_dev, 2304 "could not create Rx dmamap.\n"); 2305 goto fail; 2306 } 2307 } 2308 2309fail: 2310 return (error); 2311} 2312 2313static void 2314alc_dma_free(struct alc_softc *sc) 2315{ 2316 struct alc_txdesc *txd; 2317 struct alc_rxdesc *rxd; 2318 int i; 2319 2320 /* Tx buffers. */ 2321 if (sc->alc_cdata.alc_tx_tag != NULL) { 2322 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2323 txd = &sc->alc_cdata.alc_txdesc[i]; 2324 if (txd->tx_dmamap != NULL) { 2325 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 2326 txd->tx_dmamap); 2327 txd->tx_dmamap = NULL; 2328 } 2329 } 2330 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 2331 sc->alc_cdata.alc_tx_tag = NULL; 2332 } 2333 /* Rx buffers */ 2334 if (sc->alc_cdata.alc_rx_tag != NULL) { 2335 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2336 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2337 if (rxd->rx_dmamap != NULL) { 2338 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2339 rxd->rx_dmamap); 2340 rxd->rx_dmamap = NULL; 2341 } 2342 } 2343 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 2344 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2345 sc->alc_cdata.alc_rx_sparemap); 2346 sc->alc_cdata.alc_rx_sparemap = NULL; 2347 } 2348 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 2349 sc->alc_cdata.alc_rx_tag = NULL; 2350 } 2351 /* Tx descriptor ring. */ 2352 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 2353 if (sc->alc_rdata.alc_tx_ring_paddr != 0) 2354 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 2355 sc->alc_cdata.alc_tx_ring_map); 2356 if (sc->alc_rdata.alc_tx_ring != NULL) 2357 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 2358 sc->alc_rdata.alc_tx_ring, 2359 sc->alc_cdata.alc_tx_ring_map); 2360 sc->alc_rdata.alc_tx_ring_paddr = 0; 2361 sc->alc_rdata.alc_tx_ring = NULL; 2362 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 2363 sc->alc_cdata.alc_tx_ring_tag = NULL; 2364 } 2365 /* Rx ring. */ 2366 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 2367 if (sc->alc_rdata.alc_rx_ring_paddr != 0) 2368 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 2369 sc->alc_cdata.alc_rx_ring_map); 2370 if (sc->alc_rdata.alc_rx_ring != NULL) 2371 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 2372 sc->alc_rdata.alc_rx_ring, 2373 sc->alc_cdata.alc_rx_ring_map); 2374 sc->alc_rdata.alc_rx_ring_paddr = 0; 2375 sc->alc_rdata.alc_rx_ring = NULL; 2376 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 2377 sc->alc_cdata.alc_rx_ring_tag = NULL; 2378 } 2379 /* Rx return ring. */ 2380 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 2381 if (sc->alc_rdata.alc_rr_ring_paddr != 0) 2382 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 2383 sc->alc_cdata.alc_rr_ring_map); 2384 if (sc->alc_rdata.alc_rr_ring != NULL) 2385 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 2386 sc->alc_rdata.alc_rr_ring, 2387 sc->alc_cdata.alc_rr_ring_map); 2388 sc->alc_rdata.alc_rr_ring_paddr = 0; 2389 sc->alc_rdata.alc_rr_ring = NULL; 2390 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 2391 sc->alc_cdata.alc_rr_ring_tag = NULL; 2392 } 2393 /* CMB block */ 2394 if (sc->alc_cdata.alc_cmb_tag != NULL) { 2395 if (sc->alc_rdata.alc_cmb_paddr != 0) 2396 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 2397 sc->alc_cdata.alc_cmb_map); 2398 if (sc->alc_rdata.alc_cmb != NULL) 2399 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 2400 sc->alc_rdata.alc_cmb, 2401 sc->alc_cdata.alc_cmb_map); 2402 sc->alc_rdata.alc_cmb_paddr = 0; 2403 sc->alc_rdata.alc_cmb = NULL; 2404 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 2405 sc->alc_cdata.alc_cmb_tag = NULL; 2406 } 2407 /* SMB block */ 2408 if (sc->alc_cdata.alc_smb_tag != NULL) { 2409 if (sc->alc_rdata.alc_smb_paddr != 0) 2410 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 2411 sc->alc_cdata.alc_smb_map); 2412 if (sc->alc_rdata.alc_smb != NULL) 2413 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 2414 sc->alc_rdata.alc_smb, 2415 sc->alc_cdata.alc_smb_map); 2416 sc->alc_rdata.alc_smb_paddr = 0; 2417 sc->alc_rdata.alc_smb = NULL; 2418 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 2419 sc->alc_cdata.alc_smb_tag = NULL; 2420 } 2421 if (sc->alc_cdata.alc_buffer_tag != NULL) { 2422 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 2423 sc->alc_cdata.alc_buffer_tag = NULL; 2424 } 2425 if (sc->alc_cdata.alc_parent_tag != NULL) { 2426 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 2427 sc->alc_cdata.alc_parent_tag = NULL; 2428 } 2429} 2430 2431static int 2432alc_shutdown(device_t dev) 2433{ 2434 2435 return (alc_suspend(dev)); 2436} 2437 2438/* 2439 * Note, this driver resets the link speed to 10/100Mbps by 2440 * restarting auto-negotiation in suspend/shutdown phase but we 2441 * don't know whether that auto-negotiation would succeed or not 2442 * as driver has no control after powering off/suspend operation. 2443 * If the renegotiation fail WOL may not work. Running at 1Gbps 2444 * will draw more power than 375mA at 3.3V which is specified in 2445 * PCI specification and that would result in complete 2446 * shutdowning power to ethernet controller. 2447 * 2448 * TODO 2449 * Save current negotiated media speed/duplex/flow-control to 2450 * softc and restore the same link again after resuming. PHY 2451 * handling such as power down/resetting to 100Mbps may be better 2452 * handled in suspend method in phy driver. 2453 */ 2454static void 2455alc_setlinkspeed(struct alc_softc *sc) 2456{ 2457 struct mii_data *mii; 2458 int aneg, i; 2459 2460 mii = device_get_softc(sc->alc_miibus); 2461 mii_pollstat(mii); 2462 aneg = 0; 2463 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2464 (IFM_ACTIVE | IFM_AVALID)) { 2465 switch IFM_SUBTYPE(mii->mii_media_active) { 2466 case IFM_10_T: 2467 case IFM_100_TX: 2468 return; 2469 case IFM_1000_T: 2470 aneg++; 2471 break; 2472 default: 2473 break; 2474 } 2475 } 2476 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 2477 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2478 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 2479 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2480 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 2481 DELAY(1000); 2482 if (aneg != 0) { 2483 /* 2484 * Poll link state until alc(4) get a 10/100Mbps link. 2485 */ 2486 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 2487 mii_pollstat(mii); 2488 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 2489 == (IFM_ACTIVE | IFM_AVALID)) { 2490 switch (IFM_SUBTYPE( 2491 mii->mii_media_active)) { 2492 case IFM_10_T: 2493 case IFM_100_TX: 2494 alc_mac_config(sc); 2495 return; 2496 default: 2497 break; 2498 } 2499 } 2500 ALC_UNLOCK(sc); 2501 pause("alclnk", hz); 2502 ALC_LOCK(sc); 2503 } 2504 if (i == MII_ANEGTICKS_GIGE) 2505 device_printf(sc->alc_dev, 2506 "establishing a link failed, WOL may not work!"); 2507 } 2508 /* 2509 * No link, force MAC to have 100Mbps, full-duplex link. 2510 * This is the last resort and may/may not work. 2511 */ 2512 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 2513 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 2514 alc_mac_config(sc); 2515} 2516 2517static void 2518alc_setwol(struct alc_softc *sc) 2519{ 2520 2521 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2522 alc_setwol_816x(sc); 2523 else 2524 alc_setwol_813x(sc); 2525} 2526 2527static void 2528alc_setwol_813x(struct alc_softc *sc) 2529{ 2530 struct ifnet *ifp; 2531 uint32_t reg, pmcs; 2532 uint16_t pmstat; 2533 2534 ALC_LOCK_ASSERT(sc); 2535 2536 alc_disable_l0s_l1(sc); 2537 ifp = sc->alc_ifp; 2538 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2539 /* Disable WOL. */ 2540 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2541 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2542 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2543 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2544 /* Force PHY power down. */ 2545 alc_phy_down(sc); 2546 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2547 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2548 return; 2549 } 2550 2551 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2552 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2553 alc_setlinkspeed(sc); 2554 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2555 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 2556 } 2557 2558 pmcs = 0; 2559 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2560 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2561 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2562 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2563 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2564 MAC_CFG_BCAST); 2565 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2566 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2567 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2568 reg |= MAC_CFG_RX_ENB; 2569 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2570 2571 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2572 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2573 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2574 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 2575 /* WOL disabled, PHY power down. */ 2576 alc_phy_down(sc); 2577 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2578 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2579 } 2580 /* Request PME. */ 2581 pmstat = pci_read_config(sc->alc_dev, 2582 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2583 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2584 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2585 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2586 pci_write_config(sc->alc_dev, 2587 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2588} 2589 2590static void 2591alc_setwol_816x(struct alc_softc *sc) 2592{ 2593 struct ifnet *ifp; 2594 uint32_t gphy, mac, master, pmcs, reg; 2595 uint16_t pmstat; 2596 2597 ALC_LOCK_ASSERT(sc); 2598 2599 ifp = sc->alc_ifp; 2600 master = CSR_READ_4(sc, ALC_MASTER_CFG); 2601 master &= ~MASTER_CLK_SEL_DIS; 2602 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 2603 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB | 2604 GPHY_CFG_PHY_PLL_ON); 2605 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET; 2606 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2607 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2608 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 2609 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2610 } else { 2611 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2612 gphy |= GPHY_CFG_EXT_RESET; 2613 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2614 alc_setlinkspeed(sc); 2615 } 2616 pmcs = 0; 2617 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2618 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2619 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2620 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2621 mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2622 MAC_CFG_BCAST); 2623 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2624 mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2625 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2626 mac |= MAC_CFG_RX_ENB; 2627 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 2628 ANEG_S3DIG10_SL); 2629 } 2630 2631 /* Enable OSC. */ 2632 reg = CSR_READ_4(sc, ALC_MISC); 2633 reg &= ~MISC_INTNLOSC_OPEN; 2634 CSR_WRITE_4(sc, ALC_MISC, reg); 2635 reg |= MISC_INTNLOSC_OPEN; 2636 CSR_WRITE_4(sc, ALC_MISC, reg); 2637 CSR_WRITE_4(sc, ALC_MASTER_CFG, master); 2638 CSR_WRITE_4(sc, ALC_MAC_CFG, mac); 2639 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 2640 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1); 2641 reg |= PDLL_TRNS1_D3PLLOFF_ENB; 2642 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg); 2643 2644 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2645 /* Request PME. */ 2646 pmstat = pci_read_config(sc->alc_dev, 2647 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2648 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2649 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2650 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2651 pci_write_config(sc->alc_dev, 2652 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2653 } 2654} 2655 2656static int 2657alc_suspend(device_t dev) 2658{ 2659 struct alc_softc *sc; 2660 2661 sc = device_get_softc(dev); 2662 2663 ALC_LOCK(sc); 2664 alc_stop(sc); 2665 alc_setwol(sc); 2666 ALC_UNLOCK(sc); 2667 2668 return (0); 2669} 2670 2671static int 2672alc_resume(device_t dev) 2673{ 2674 struct alc_softc *sc; 2675 struct ifnet *ifp; 2676 uint16_t pmstat; 2677 2678 sc = device_get_softc(dev); 2679 2680 ALC_LOCK(sc); 2681 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2682 /* Disable PME and clear PME status. */ 2683 pmstat = pci_read_config(sc->alc_dev, 2684 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2685 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2686 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2687 pci_write_config(sc->alc_dev, 2688 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2689 } 2690 } 2691 /* Reset PHY. */ 2692 alc_phy_reset(sc); 2693 ifp = sc->alc_ifp; 2694 if ((ifp->if_flags & IFF_UP) != 0) { 2695 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2696 alc_init_locked(sc); 2697 } 2698 ALC_UNLOCK(sc); 2699 2700 return (0); 2701} 2702 2703static int 2704alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2705{ 2706 struct alc_txdesc *txd, *txd_last; 2707 struct tx_desc *desc; 2708 struct mbuf *m; 2709 struct ip *ip; 2710 struct tcphdr *tcp; 2711 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2712 bus_dmamap_t map; 2713 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2714 int error, idx, nsegs, prod; 2715 2716 ALC_LOCK_ASSERT(sc); 2717 2718 M_ASSERTPKTHDR((*m_head)); 2719 2720 m = *m_head; 2721 ip = NULL; 2722 tcp = NULL; 2723 ip_off = poff = 0; 2724 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2725 /* 2726 * AR81[3567]x requires offset of TCP/UDP header in its 2727 * Tx descriptor to perform Tx checksum offloading. TSO 2728 * also requires TCP header offset and modification of 2729 * IP/TCP header. This kind of operation takes many CPU 2730 * cycles on FreeBSD so fast host CPU is required to get 2731 * smooth TSO performance. 2732 */ 2733 struct ether_header *eh; 2734 2735 if (M_WRITABLE(m) == 0) { 2736 /* Get a writable copy. */ 2737 m = m_dup(*m_head, M_NOWAIT); 2738 /* Release original mbufs. */ 2739 m_freem(*m_head); 2740 if (m == NULL) { 2741 *m_head = NULL; 2742 return (ENOBUFS); 2743 } 2744 *m_head = m; 2745 } 2746 2747 ip_off = sizeof(struct ether_header); 2748 m = m_pullup(m, ip_off); 2749 if (m == NULL) { 2750 *m_head = NULL; 2751 return (ENOBUFS); 2752 } 2753 eh = mtod(m, struct ether_header *); 2754 /* 2755 * Check if hardware VLAN insertion is off. 2756 * Additional check for LLC/SNAP frame? 2757 */ 2758 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2759 ip_off = sizeof(struct ether_vlan_header); 2760 m = m_pullup(m, ip_off); 2761 if (m == NULL) { 2762 *m_head = NULL; 2763 return (ENOBUFS); 2764 } 2765 } 2766 m = m_pullup(m, ip_off + sizeof(struct ip)); 2767 if (m == NULL) { 2768 *m_head = NULL; 2769 return (ENOBUFS); 2770 } 2771 ip = (struct ip *)(mtod(m, char *) + ip_off); 2772 poff = ip_off + (ip->ip_hl << 2); 2773 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2774 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2775 if (m == NULL) { 2776 *m_head = NULL; 2777 return (ENOBUFS); 2778 } 2779 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2780 m = m_pullup(m, poff + (tcp->th_off << 2)); 2781 if (m == NULL) { 2782 *m_head = NULL; 2783 return (ENOBUFS); 2784 } 2785 /* 2786 * Due to strict adherence of Microsoft NDIS 2787 * Large Send specification, hardware expects 2788 * a pseudo TCP checksum inserted by upper 2789 * stack. Unfortunately the pseudo TCP 2790 * checksum that NDIS refers to does not include 2791 * TCP payload length so driver should recompute 2792 * the pseudo checksum here. Hopefully this 2793 * wouldn't be much burden on modern CPUs. 2794 * 2795 * Reset IP checksum and recompute TCP pseudo 2796 * checksum as NDIS specification said. 2797 */ 2798 ip = (struct ip *)(mtod(m, char *) + ip_off); 2799 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2800 ip->ip_sum = 0; 2801 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2802 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2803 } 2804 *m_head = m; 2805 } 2806 2807 prod = sc->alc_cdata.alc_tx_prod; 2808 txd = &sc->alc_cdata.alc_txdesc[prod]; 2809 txd_last = txd; 2810 map = txd->tx_dmamap; 2811 2812 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2813 *m_head, txsegs, &nsegs, 0); 2814 if (error == EFBIG) { 2815 m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS); 2816 if (m == NULL) { 2817 m_freem(*m_head); 2818 *m_head = NULL; 2819 return (ENOMEM); 2820 } 2821 *m_head = m; 2822 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2823 *m_head, txsegs, &nsegs, 0); 2824 if (error != 0) { 2825 m_freem(*m_head); 2826 *m_head = NULL; 2827 return (error); 2828 } 2829 } else if (error != 0) 2830 return (error); 2831 if (nsegs == 0) { 2832 m_freem(*m_head); 2833 *m_head = NULL; 2834 return (EIO); 2835 } 2836 2837 /* Check descriptor overrun. */ 2838 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2839 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2840 return (ENOBUFS); 2841 } 2842 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2843 2844 m = *m_head; 2845 cflags = TD_ETHERNET; 2846 vtag = 0; 2847 desc = NULL; 2848 idx = 0; 2849 /* Configure VLAN hardware tag insertion. */ 2850 if ((m->m_flags & M_VLANTAG) != 0) { 2851 vtag = htons(m->m_pkthdr.ether_vtag); 2852 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2853 cflags |= TD_INS_VLAN_TAG; 2854 } 2855 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2856 /* Request TSO and set MSS. */ 2857 cflags |= TD_TSO | TD_TSO_DESCV1; 2858 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2859 TD_MSS_MASK; 2860 /* Set TCP header offset. */ 2861 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2862 TD_TCPHDR_OFFSET_MASK; 2863 /* 2864 * AR81[3567]x requires the first buffer should 2865 * only hold IP/TCP header data. Payload should 2866 * be handled in other descriptors. 2867 */ 2868 hdrlen = poff + (tcp->th_off << 2); 2869 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2870 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2871 desc->flags = htole32(cflags); 2872 desc->addr = htole64(txsegs[0].ds_addr); 2873 sc->alc_cdata.alc_tx_cnt++; 2874 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2875 if (m->m_len - hdrlen > 0) { 2876 /* Handle remaining payload of the first fragment. */ 2877 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2878 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2879 vtag)); 2880 desc->flags = htole32(cflags); 2881 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2882 sc->alc_cdata.alc_tx_cnt++; 2883 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2884 } 2885 /* Handle remaining fragments. */ 2886 idx = 1; 2887 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2888 /* Configure Tx checksum offload. */ 2889#ifdef ALC_USE_CUSTOM_CSUM 2890 cflags |= TD_CUSTOM_CSUM; 2891 /* Set checksum start offset. */ 2892 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2893 TD_PLOAD_OFFSET_MASK; 2894 /* Set checksum insertion position of TCP/UDP. */ 2895 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2896 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2897#else 2898 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2899 cflags |= TD_IPCSUM; 2900 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2901 cflags |= TD_TCPCSUM; 2902 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2903 cflags |= TD_UDPCSUM; 2904 /* Set TCP/UDP header offset. */ 2905 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2906 TD_L4HDR_OFFSET_MASK; 2907#endif 2908 } 2909 for (; idx < nsegs; idx++) { 2910 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2911 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2912 desc->flags = htole32(cflags); 2913 desc->addr = htole64(txsegs[idx].ds_addr); 2914 sc->alc_cdata.alc_tx_cnt++; 2915 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2916 } 2917 /* Update producer index. */ 2918 sc->alc_cdata.alc_tx_prod = prod; 2919 2920 /* Finally set EOP on the last descriptor. */ 2921 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2922 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2923 desc->flags |= htole32(TD_EOP); 2924 2925 /* Swap dmamap of the first and the last. */ 2926 txd = &sc->alc_cdata.alc_txdesc[prod]; 2927 map = txd_last->tx_dmamap; 2928 txd_last->tx_dmamap = txd->tx_dmamap; 2929 txd->tx_dmamap = map; 2930 txd->tx_m = m; 2931 2932 return (0); 2933} 2934 2935static void 2936alc_start(struct ifnet *ifp) 2937{ 2938 struct alc_softc *sc; 2939 2940 sc = ifp->if_softc; 2941 ALC_LOCK(sc); 2942 alc_start_locked(ifp); 2943 ALC_UNLOCK(sc); 2944} 2945 2946static void 2947alc_start_locked(struct ifnet *ifp) 2948{ 2949 struct alc_softc *sc; 2950 struct mbuf *m_head; 2951 int enq; 2952 2953 sc = ifp->if_softc; 2954 2955 ALC_LOCK_ASSERT(sc); 2956 2957 /* Reclaim transmitted frames. */ 2958 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2959 alc_txeof(sc); 2960 2961 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2962 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) 2963 return; 2964 2965 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 2966 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2967 if (m_head == NULL) 2968 break; 2969 /* 2970 * Pack the data into the transmit ring. If we 2971 * don't have room, set the OACTIVE flag and wait 2972 * for the NIC to drain the ring. 2973 */ 2974 if (alc_encap(sc, &m_head)) { 2975 if (m_head == NULL) 2976 break; 2977 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2978 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2979 break; 2980 } 2981 2982 enq++; 2983 /* 2984 * If there's a BPF listener, bounce a copy of this frame 2985 * to him. 2986 */ 2987 ETHER_BPF_MTAP(ifp, m_head); 2988 } 2989 2990 if (enq > 0) 2991 alc_start_tx(sc); 2992} 2993 2994static void 2995alc_start_tx(struct alc_softc *sc) 2996{ 2997 2998 /* Sync descriptors. */ 2999 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3000 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 3001 /* Kick. Assume we're using normal Tx priority queue. */ 3002 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3003 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, 3004 (uint16_t)sc->alc_cdata.alc_tx_prod); 3005 else 3006 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 3007 (sc->alc_cdata.alc_tx_prod << 3008 MBOX_TD_PROD_LO_IDX_SHIFT) & 3009 MBOX_TD_PROD_LO_IDX_MASK); 3010 /* Set a timeout in case the chip goes out to lunch. */ 3011 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 3012} 3013 3014static void 3015alc_watchdog(struct alc_softc *sc) 3016{ 3017 struct ifnet *ifp; 3018 3019 ALC_LOCK_ASSERT(sc); 3020 3021 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 3022 return; 3023 3024 ifp = sc->alc_ifp; 3025 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 3026 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 3027 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3028 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3029 alc_init_locked(sc); 3030 return; 3031 } 3032 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 3033 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3034 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3035 alc_init_locked(sc); 3036 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3037 alc_start_locked(ifp); 3038} 3039 3040static int 3041alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3042{ 3043 struct alc_softc *sc; 3044 struct ifreq *ifr; 3045 struct mii_data *mii; 3046 int error, mask; 3047 3048 sc = ifp->if_softc; 3049 ifr = (struct ifreq *)data; 3050 error = 0; 3051 switch (cmd) { 3052 case SIOCSIFMTU: 3053 if (ifr->ifr_mtu < ETHERMIN || 3054 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 3055 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 3056 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 3057 ifr->ifr_mtu > ETHERMTU)) 3058 error = EINVAL; 3059 else if (ifp->if_mtu != ifr->ifr_mtu) { 3060 ALC_LOCK(sc); 3061 ifp->if_mtu = ifr->ifr_mtu; 3062 /* AR81[3567]x has 13 bits MSS field. */ 3063 if (ifp->if_mtu > ALC_TSO_MTU && 3064 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3065 ifp->if_capenable &= ~IFCAP_TSO4; 3066 ifp->if_hwassist &= ~CSUM_TSO; 3067 VLAN_CAPABILITIES(ifp); 3068 } 3069 ALC_UNLOCK(sc); 3070 } 3071 break; 3072 case SIOCSIFFLAGS: 3073 ALC_LOCK(sc); 3074 if ((ifp->if_flags & IFF_UP) != 0) { 3075 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3076 ((ifp->if_flags ^ sc->alc_if_flags) & 3077 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3078 alc_rxfilter(sc); 3079 else 3080 alc_init_locked(sc); 3081 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3082 alc_stop(sc); 3083 sc->alc_if_flags = ifp->if_flags; 3084 ALC_UNLOCK(sc); 3085 break; 3086 case SIOCADDMULTI: 3087 case SIOCDELMULTI: 3088 ALC_LOCK(sc); 3089 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3090 alc_rxfilter(sc); 3091 ALC_UNLOCK(sc); 3092 break; 3093 case SIOCSIFMEDIA: 3094 case SIOCGIFMEDIA: 3095 mii = device_get_softc(sc->alc_miibus); 3096 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 3097 break; 3098 case SIOCSIFCAP: 3099 ALC_LOCK(sc); 3100 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3101 if ((mask & IFCAP_TXCSUM) != 0 && 3102 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3103 ifp->if_capenable ^= IFCAP_TXCSUM; 3104 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3105 ifp->if_hwassist |= ALC_CSUM_FEATURES; 3106 else 3107 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 3108 } 3109 if ((mask & IFCAP_TSO4) != 0 && 3110 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 3111 ifp->if_capenable ^= IFCAP_TSO4; 3112 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 3113 /* AR81[3567]x has 13 bits MSS field. */ 3114 if (ifp->if_mtu > ALC_TSO_MTU) { 3115 ifp->if_capenable &= ~IFCAP_TSO4; 3116 ifp->if_hwassist &= ~CSUM_TSO; 3117 } else 3118 ifp->if_hwassist |= CSUM_TSO; 3119 } else 3120 ifp->if_hwassist &= ~CSUM_TSO; 3121 } 3122 if ((mask & IFCAP_WOL_MCAST) != 0 && 3123 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 3124 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3125 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3126 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 3127 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3128 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3129 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3130 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3131 alc_rxvlan(sc); 3132 } 3133 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3134 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 3135 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 3136 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3137 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3138 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3139 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3140 ifp->if_capenable &= 3141 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 3142 ALC_UNLOCK(sc); 3143 VLAN_CAPABILITIES(ifp); 3144 break; 3145 default: 3146 error = ether_ioctl(ifp, cmd, data); 3147 break; 3148 } 3149 3150 return (error); 3151} 3152 3153static void 3154alc_mac_config(struct alc_softc *sc) 3155{ 3156 struct mii_data *mii; 3157 uint32_t reg; 3158 3159 ALC_LOCK_ASSERT(sc); 3160 3161 mii = device_get_softc(sc->alc_miibus); 3162 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3163 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 3164 MAC_CFG_SPEED_MASK); 3165 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3166 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3167 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3168 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3169 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3170 /* Reprogram MAC with resolved speed/duplex. */ 3171 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3172 case IFM_10_T: 3173 case IFM_100_TX: 3174 reg |= MAC_CFG_SPEED_10_100; 3175 break; 3176 case IFM_1000_T: 3177 reg |= MAC_CFG_SPEED_1000; 3178 break; 3179 } 3180 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 3181 reg |= MAC_CFG_FULL_DUPLEX; 3182 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 3183 reg |= MAC_CFG_TX_FC; 3184 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 3185 reg |= MAC_CFG_RX_FC; 3186 } 3187 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3188} 3189 3190static void 3191alc_stats_clear(struct alc_softc *sc) 3192{ 3193 struct smb sb, *smb; 3194 uint32_t *reg; 3195 int i; 3196 3197 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3198 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3199 sc->alc_cdata.alc_smb_map, 3200 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3201 smb = sc->alc_rdata.alc_smb; 3202 /* Update done, clear. */ 3203 smb->updated = 0; 3204 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3205 sc->alc_cdata.alc_smb_map, 3206 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3207 } else { 3208 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3209 reg++) { 3210 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3211 i += sizeof(uint32_t); 3212 } 3213 /* Read Tx statistics. */ 3214 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3215 reg++) { 3216 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3217 i += sizeof(uint32_t); 3218 } 3219 } 3220} 3221 3222static void 3223alc_stats_update(struct alc_softc *sc) 3224{ 3225 struct alc_hw_stats *stat; 3226 struct smb sb, *smb; 3227 struct ifnet *ifp; 3228 uint32_t *reg; 3229 int i; 3230 3231 ALC_LOCK_ASSERT(sc); 3232 3233 ifp = sc->alc_ifp; 3234 stat = &sc->alc_stats; 3235 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3236 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3237 sc->alc_cdata.alc_smb_map, 3238 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3239 smb = sc->alc_rdata.alc_smb; 3240 if (smb->updated == 0) 3241 return; 3242 } else { 3243 smb = &sb; 3244 /* Read Rx statistics. */ 3245 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3246 reg++) { 3247 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3248 i += sizeof(uint32_t); 3249 } 3250 /* Read Tx statistics. */ 3251 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3252 reg++) { 3253 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3254 i += sizeof(uint32_t); 3255 } 3256 } 3257 3258 /* Rx stats. */ 3259 stat->rx_frames += smb->rx_frames; 3260 stat->rx_bcast_frames += smb->rx_bcast_frames; 3261 stat->rx_mcast_frames += smb->rx_mcast_frames; 3262 stat->rx_pause_frames += smb->rx_pause_frames; 3263 stat->rx_control_frames += smb->rx_control_frames; 3264 stat->rx_crcerrs += smb->rx_crcerrs; 3265 stat->rx_lenerrs += smb->rx_lenerrs; 3266 stat->rx_bytes += smb->rx_bytes; 3267 stat->rx_runts += smb->rx_runts; 3268 stat->rx_fragments += smb->rx_fragments; 3269 stat->rx_pkts_64 += smb->rx_pkts_64; 3270 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 3271 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 3272 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 3273 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 3274 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 3275 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 3276 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 3277 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 3278 stat->rx_rrs_errs += smb->rx_rrs_errs; 3279 stat->rx_alignerrs += smb->rx_alignerrs; 3280 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 3281 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 3282 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 3283 3284 /* Tx stats. */ 3285 stat->tx_frames += smb->tx_frames; 3286 stat->tx_bcast_frames += smb->tx_bcast_frames; 3287 stat->tx_mcast_frames += smb->tx_mcast_frames; 3288 stat->tx_pause_frames += smb->tx_pause_frames; 3289 stat->tx_excess_defer += smb->tx_excess_defer; 3290 stat->tx_control_frames += smb->tx_control_frames; 3291 stat->tx_deferred += smb->tx_deferred; 3292 stat->tx_bytes += smb->tx_bytes; 3293 stat->tx_pkts_64 += smb->tx_pkts_64; 3294 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 3295 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 3296 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 3297 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 3298 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 3299 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 3300 stat->tx_single_colls += smb->tx_single_colls; 3301 stat->tx_multi_colls += smb->tx_multi_colls; 3302 stat->tx_late_colls += smb->tx_late_colls; 3303 stat->tx_excess_colls += smb->tx_excess_colls; 3304 stat->tx_underrun += smb->tx_underrun; 3305 stat->tx_desc_underrun += smb->tx_desc_underrun; 3306 stat->tx_lenerrs += smb->tx_lenerrs; 3307 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 3308 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 3309 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 3310 3311 /* Update counters in ifnet. */ 3312 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 3313 3314 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 3315 smb->tx_multi_colls * 2 + smb->tx_late_colls + 3316 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 3317 3318 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 3319 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 3320 3321 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 3322 3323 if_inc_counter(ifp, IFCOUNTER_IERRORS, 3324 smb->rx_crcerrs + smb->rx_lenerrs + 3325 smb->rx_runts + smb->rx_pkts_truncated + 3326 smb->rx_fifo_oflows + smb->rx_rrs_errs + 3327 smb->rx_alignerrs); 3328 3329 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3330 /* Update done, clear. */ 3331 smb->updated = 0; 3332 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3333 sc->alc_cdata.alc_smb_map, 3334 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3335 } 3336} 3337 3338static int 3339alc_intr(void *arg) 3340{ 3341 struct alc_softc *sc; 3342 uint32_t status; 3343 3344 sc = (struct alc_softc *)arg; 3345 3346 if (sc->alc_flags & ALC_FLAG_MT) { 3347 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3348 return (FILTER_HANDLED); 3349 } 3350 3351 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3352 if ((status & ALC_INTRS) == 0) 3353 return (FILTER_STRAY); 3354 /* Disable interrupts. */ 3355 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 3356 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3357 3358 return (FILTER_HANDLED); 3359} 3360 3361static void 3362alc_int_task(void *arg, int pending) 3363{ 3364 struct alc_softc *sc; 3365 struct ifnet *ifp; 3366 uint32_t status; 3367 int more; 3368 3369 sc = (struct alc_softc *)arg; 3370 ifp = sc->alc_ifp; 3371 3372 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3373 ALC_LOCK(sc); 3374 if (sc->alc_morework != 0) { 3375 sc->alc_morework = 0; 3376 status |= INTR_RX_PKT; 3377 } 3378 if ((status & ALC_INTRS) == 0) 3379 goto done; 3380 3381 /* Acknowledge interrupts but still disable interrupts. */ 3382 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 3383 3384 more = 0; 3385 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3386 if ((status & INTR_RX_PKT) != 0) { 3387 more = alc_rxintr(sc, sc->alc_process_limit); 3388 if (more == EAGAIN) 3389 sc->alc_morework = 1; 3390 else if (more == EIO) { 3391 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3392 alc_init_locked(sc); 3393 ALC_UNLOCK(sc); 3394 return; 3395 } 3396 } 3397 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 3398 INTR_TXQ_TO_RST)) != 0) { 3399 if ((status & INTR_DMA_RD_TO_RST) != 0) 3400 device_printf(sc->alc_dev, 3401 "DMA read error! -- resetting\n"); 3402 if ((status & INTR_DMA_WR_TO_RST) != 0) 3403 device_printf(sc->alc_dev, 3404 "DMA write error! -- resetting\n"); 3405 if ((status & INTR_TXQ_TO_RST) != 0) 3406 device_printf(sc->alc_dev, 3407 "TxQ reset! -- resetting\n"); 3408 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3409 alc_init_locked(sc); 3410 ALC_UNLOCK(sc); 3411 return; 3412 } 3413 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3414 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3415 alc_start_locked(ifp); 3416 } 3417 3418 if (more == EAGAIN || 3419 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 3420 ALC_UNLOCK(sc); 3421 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3422 return; 3423 } 3424 3425done: 3426 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3427 /* Re-enable interrupts if we're running. */ 3428 if (sc->alc_flags & ALC_FLAG_MT) 3429 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3430 else 3431 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 3432 } 3433 ALC_UNLOCK(sc); 3434} 3435 3436static void 3437alc_txeof(struct alc_softc *sc) 3438{ 3439 struct ifnet *ifp; 3440 struct alc_txdesc *txd; 3441 uint32_t cons, prod; 3442 int prog; 3443 3444 ALC_LOCK_ASSERT(sc); 3445 3446 ifp = sc->alc_ifp; 3447 3448 if (sc->alc_cdata.alc_tx_cnt == 0) 3449 return; 3450 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3451 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3452 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3453 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3454 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 3455 prod = sc->alc_rdata.alc_cmb->cons; 3456 } else { 3457 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3458 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); 3459 else { 3460 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 3461 /* Assume we're using normal Tx priority queue. */ 3462 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 3463 MBOX_TD_CONS_LO_IDX_SHIFT; 3464 } 3465 } 3466 cons = sc->alc_cdata.alc_tx_cons; 3467 /* 3468 * Go through our Tx list and free mbufs for those 3469 * frames which have been transmitted. 3470 */ 3471 for (prog = 0; cons != prod; prog++, 3472 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 3473 if (sc->alc_cdata.alc_tx_cnt <= 0) 3474 break; 3475 prog++; 3476 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3477 sc->alc_cdata.alc_tx_cnt--; 3478 txd = &sc->alc_cdata.alc_txdesc[cons]; 3479 if (txd->tx_m != NULL) { 3480 /* Reclaim transmitted mbufs. */ 3481 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3482 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3483 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3484 txd->tx_dmamap); 3485 m_freem(txd->tx_m); 3486 txd->tx_m = NULL; 3487 } 3488 } 3489 3490 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3491 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3492 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 3493 sc->alc_cdata.alc_tx_cons = cons; 3494 /* 3495 * Unarm watchdog timer only when there is no pending 3496 * frames in Tx queue. 3497 */ 3498 if (sc->alc_cdata.alc_tx_cnt == 0) 3499 sc->alc_watchdog_timer = 0; 3500} 3501 3502static int 3503alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 3504{ 3505 struct mbuf *m; 3506 bus_dma_segment_t segs[1]; 3507 bus_dmamap_t map; 3508 int nsegs; 3509 3510 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3511 if (m == NULL) 3512 return (ENOBUFS); 3513 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 3514#ifndef __NO_STRICT_ALIGNMENT 3515 m_adj(m, sizeof(uint64_t)); 3516#endif 3517 3518 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 3519 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3520 m_freem(m); 3521 return (ENOBUFS); 3522 } 3523 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3524 3525 if (rxd->rx_m != NULL) { 3526 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3527 BUS_DMASYNC_POSTREAD); 3528 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 3529 } 3530 map = rxd->rx_dmamap; 3531 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 3532 sc->alc_cdata.alc_rx_sparemap = map; 3533 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3534 BUS_DMASYNC_PREREAD); 3535 rxd->rx_m = m; 3536 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 3537 return (0); 3538} 3539 3540static int 3541alc_rxintr(struct alc_softc *sc, int count) 3542{ 3543 struct ifnet *ifp; 3544 struct rx_rdesc *rrd; 3545 uint32_t nsegs, status; 3546 int rr_cons, prog; 3547 3548 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3549 sc->alc_cdata.alc_rr_ring_map, 3550 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3551 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3552 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 3553 rr_cons = sc->alc_cdata.alc_rr_cons; 3554 ifp = sc->alc_ifp; 3555 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) { 3556 if (count-- <= 0) 3557 break; 3558 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 3559 status = le32toh(rrd->status); 3560 if ((status & RRD_VALID) == 0) 3561 break; 3562 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 3563 if (nsegs == 0) { 3564 /* This should not happen! */ 3565 device_printf(sc->alc_dev, 3566 "unexpected segment count -- resetting\n"); 3567 return (EIO); 3568 } 3569 alc_rxeof(sc, rrd); 3570 /* Clear Rx return status. */ 3571 rrd->status = 0; 3572 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 3573 sc->alc_cdata.alc_rx_cons += nsegs; 3574 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 3575 prog += nsegs; 3576 } 3577 3578 if (prog > 0) { 3579 /* Update the consumer index. */ 3580 sc->alc_cdata.alc_rr_cons = rr_cons; 3581 /* Sync Rx return descriptors. */ 3582 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3583 sc->alc_cdata.alc_rr_ring_map, 3584 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3585 /* 3586 * Sync updated Rx descriptors such that controller see 3587 * modified buffer addresses. 3588 */ 3589 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3590 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3591 /* 3592 * Let controller know availability of new Rx buffers. 3593 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 3594 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 3595 * only when Rx buffer pre-fetching is required. In 3596 * addition we already set ALC_RX_RD_FREE_THRESH to 3597 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 3598 * it still seems that pre-fetching needs more 3599 * experimentation. 3600 */ 3601 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3602 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, 3603 (uint16_t)sc->alc_cdata.alc_rx_cons); 3604 else 3605 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 3606 sc->alc_cdata.alc_rx_cons); 3607 } 3608 3609 return (count > 0 ? 0 : EAGAIN); 3610} 3611 3612#ifndef __NO_STRICT_ALIGNMENT 3613static struct mbuf * 3614alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 3615{ 3616 struct mbuf *n; 3617 int i; 3618 uint16_t *src, *dst; 3619 3620 src = mtod(m, uint16_t *); 3621 dst = src - 3; 3622 3623 if (m->m_next == NULL) { 3624 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3625 *dst++ = *src++; 3626 m->m_data -= 6; 3627 return (m); 3628 } 3629 /* 3630 * Append a new mbuf to received mbuf chain and copy ethernet 3631 * header from the mbuf chain. This can save lots of CPU 3632 * cycles for jumbo frame. 3633 */ 3634 MGETHDR(n, M_NOWAIT, MT_DATA); 3635 if (n == NULL) { 3636 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3637 m_freem(m); 3638 return (NULL); 3639 } 3640 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3641 m->m_data += ETHER_HDR_LEN; 3642 m->m_len -= ETHER_HDR_LEN; 3643 n->m_len = ETHER_HDR_LEN; 3644 M_MOVE_PKTHDR(n, m); 3645 n->m_next = m; 3646 return (n); 3647} 3648#endif 3649 3650/* Receive a frame. */ 3651static void 3652alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 3653{ 3654 struct alc_rxdesc *rxd; 3655 struct ifnet *ifp; 3656 struct mbuf *mp, *m; 3657 uint32_t rdinfo, status, vtag; 3658 int count, nsegs, rx_cons; 3659 3660 ifp = sc->alc_ifp; 3661 status = le32toh(rrd->status); 3662 rdinfo = le32toh(rrd->rdinfo); 3663 rx_cons = RRD_RD_IDX(rdinfo); 3664 nsegs = RRD_RD_CNT(rdinfo); 3665 3666 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 3667 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 3668 /* 3669 * We want to pass the following frames to upper 3670 * layer regardless of error status of Rx return 3671 * ring. 3672 * 3673 * o IP/TCP/UDP checksum is bad. 3674 * o frame length and protocol specific length 3675 * does not match. 3676 * 3677 * Force network stack compute checksum for 3678 * errored frames. 3679 */ 3680 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 3681 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 3682 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 3683 return; 3684 } 3685 3686 for (count = 0; count < nsegs; count++, 3687 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 3688 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 3689 mp = rxd->rx_m; 3690 /* Add a new receive buffer to the ring. */ 3691 if (alc_newbuf(sc, rxd) != 0) { 3692 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3693 /* Reuse Rx buffers. */ 3694 if (sc->alc_cdata.alc_rxhead != NULL) 3695 m_freem(sc->alc_cdata.alc_rxhead); 3696 break; 3697 } 3698 3699 /* 3700 * Assume we've received a full sized frame. 3701 * Actual size is fixed when we encounter the end of 3702 * multi-segmented frame. 3703 */ 3704 mp->m_len = sc->alc_buf_size; 3705 3706 /* Chain received mbufs. */ 3707 if (sc->alc_cdata.alc_rxhead == NULL) { 3708 sc->alc_cdata.alc_rxhead = mp; 3709 sc->alc_cdata.alc_rxtail = mp; 3710 } else { 3711 mp->m_flags &= ~M_PKTHDR; 3712 sc->alc_cdata.alc_rxprev_tail = 3713 sc->alc_cdata.alc_rxtail; 3714 sc->alc_cdata.alc_rxtail->m_next = mp; 3715 sc->alc_cdata.alc_rxtail = mp; 3716 } 3717 3718 if (count == nsegs - 1) { 3719 /* Last desc. for this frame. */ 3720 m = sc->alc_cdata.alc_rxhead; 3721 m->m_flags |= M_PKTHDR; 3722 /* 3723 * It seems that L1C/L2C controller has no way 3724 * to tell hardware to strip CRC bytes. 3725 */ 3726 m->m_pkthdr.len = 3727 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3728 if (nsegs > 1) { 3729 /* Set last mbuf size. */ 3730 mp->m_len = sc->alc_cdata.alc_rxlen - 3731 (nsegs - 1) * sc->alc_buf_size; 3732 /* Remove the CRC bytes in chained mbufs. */ 3733 if (mp->m_len <= ETHER_CRC_LEN) { 3734 sc->alc_cdata.alc_rxtail = 3735 sc->alc_cdata.alc_rxprev_tail; 3736 sc->alc_cdata.alc_rxtail->m_len -= 3737 (ETHER_CRC_LEN - mp->m_len); 3738 sc->alc_cdata.alc_rxtail->m_next = NULL; 3739 m_freem(mp); 3740 } else { 3741 mp->m_len -= ETHER_CRC_LEN; 3742 } 3743 } else 3744 m->m_len = m->m_pkthdr.len; 3745 m->m_pkthdr.rcvif = ifp; 3746 /* 3747 * Due to hardware bugs, Rx checksum offloading 3748 * was intentionally disabled. 3749 */ 3750 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 3751 (status & RRD_VLAN_TAG) != 0) { 3752 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3753 m->m_pkthdr.ether_vtag = ntohs(vtag); 3754 m->m_flags |= M_VLANTAG; 3755 } 3756#ifndef __NO_STRICT_ALIGNMENT 3757 m = alc_fixup_rx(ifp, m); 3758 if (m != NULL) 3759#endif 3760 { 3761 /* Pass it on. */ 3762 ALC_UNLOCK(sc); 3763 (*ifp->if_input)(ifp, m); 3764 ALC_LOCK(sc); 3765 } 3766 } 3767 } 3768 /* Reset mbuf chains. */ 3769 ALC_RXCHAIN_RESET(sc); 3770} 3771 3772static void 3773alc_tick(void *arg) 3774{ 3775 struct alc_softc *sc; 3776 struct mii_data *mii; 3777 3778 sc = (struct alc_softc *)arg; 3779 3780 ALC_LOCK_ASSERT(sc); 3781 3782 mii = device_get_softc(sc->alc_miibus); 3783 mii_tick(mii); 3784 alc_stats_update(sc); 3785 /* 3786 * alc(4) does not rely on Tx completion interrupts to reclaim 3787 * transferred buffers. Instead Tx completion interrupts are 3788 * used to hint for scheduling Tx task. So it's necessary to 3789 * release transmitted buffers by kicking Tx completion 3790 * handler. This limits the maximum reclamation delay to a hz. 3791 */ 3792 alc_txeof(sc); 3793 alc_watchdog(sc); 3794 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3795} 3796 3797static void 3798alc_osc_reset(struct alc_softc *sc) 3799{ 3800 uint32_t reg; 3801 3802 reg = CSR_READ_4(sc, ALC_MISC3); 3803 reg &= ~MISC3_25M_BY_SW; 3804 reg |= MISC3_25M_NOTO_INTNL; 3805 CSR_WRITE_4(sc, ALC_MISC3, reg); 3806 3807 reg = CSR_READ_4(sc, ALC_MISC); 3808 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 3809 /* 3810 * Restore over-current protection default value. 3811 * This value could be reset by MAC reset. 3812 */ 3813 reg &= ~MISC_PSW_OCP_MASK; 3814 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 3815 reg &= ~MISC_INTNLOSC_OPEN; 3816 CSR_WRITE_4(sc, ALC_MISC, reg); 3817 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3818 reg = CSR_READ_4(sc, ALC_MISC2); 3819 reg &= ~MISC2_CALB_START; 3820 CSR_WRITE_4(sc, ALC_MISC2, reg); 3821 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 3822 3823 } else { 3824 reg &= ~MISC_INTNLOSC_OPEN; 3825 /* Disable isolate for revision A devices. */ 3826 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3827 reg &= ~MISC_ISO_ENB; 3828 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3829 CSR_WRITE_4(sc, ALC_MISC, reg); 3830 } 3831 3832 DELAY(20); 3833} 3834 3835static void 3836alc_reset(struct alc_softc *sc) 3837{ 3838 uint32_t pmcfg, reg; 3839 int i; 3840 3841 pmcfg = 0; 3842 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3843 /* Reset workaround. */ 3844 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 3845 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3846 (sc->alc_rev & 0x01) != 0) { 3847 /* Disable L0s/L1s before reset. */ 3848 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 3849 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3850 != 0) { 3851 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 3852 PM_CFG_ASPM_L1_ENB); 3853 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3854 } 3855 } 3856 } 3857 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3858 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3859 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3860 3861 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3862 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3863 DELAY(10); 3864 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 3865 break; 3866 } 3867 if (i == 0) 3868 device_printf(sc->alc_dev, "MAC reset timeout!\n"); 3869 } 3870 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3871 DELAY(10); 3872 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3873 break; 3874 } 3875 if (i == 0) 3876 device_printf(sc->alc_dev, "master reset timeout!\n"); 3877 3878 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3879 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3880 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 3881 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3882 break; 3883 DELAY(10); 3884 } 3885 if (i == 0) 3886 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3887 3888 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3889 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3890 (sc->alc_rev & 0x01) != 0) { 3891 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3892 reg |= MASTER_CLK_SEL_DIS; 3893 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3894 /* Restore L0s/L1s config. */ 3895 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3896 != 0) 3897 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3898 } 3899 3900 alc_osc_reset(sc); 3901 reg = CSR_READ_4(sc, ALC_MISC3); 3902 reg &= ~MISC3_25M_BY_SW; 3903 reg |= MISC3_25M_NOTO_INTNL; 3904 CSR_WRITE_4(sc, ALC_MISC3, reg); 3905 reg = CSR_READ_4(sc, ALC_MISC); 3906 reg &= ~MISC_INTNLOSC_OPEN; 3907 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3908 reg &= ~MISC_ISO_ENB; 3909 CSR_WRITE_4(sc, ALC_MISC, reg); 3910 DELAY(20); 3911 } 3912 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3913 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3914 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3915 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3916 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3917 SERDES_PHY_CLK_SLOWDOWN); 3918} 3919 3920static void 3921alc_init(void *xsc) 3922{ 3923 struct alc_softc *sc; 3924 3925 sc = (struct alc_softc *)xsc; 3926 ALC_LOCK(sc); 3927 alc_init_locked(sc); 3928 ALC_UNLOCK(sc); 3929} 3930 3931static void 3932alc_init_locked(struct alc_softc *sc) 3933{ 3934 struct ifnet *ifp; 3935 struct mii_data *mii; 3936 uint8_t eaddr[ETHER_ADDR_LEN]; 3937 bus_addr_t paddr; 3938 uint32_t reg, rxf_hi, rxf_lo; 3939 3940 ALC_LOCK_ASSERT(sc); 3941 3942 ifp = sc->alc_ifp; 3943 mii = device_get_softc(sc->alc_miibus); 3944 3945 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3946 return; 3947 /* 3948 * Cancel any pending I/O. 3949 */ 3950 alc_stop(sc); 3951 /* 3952 * Reset the chip to a known state. 3953 */ 3954 alc_reset(sc); 3955 3956 /* Initialize Rx descriptors. */ 3957 if (alc_init_rx_ring(sc) != 0) { 3958 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3959 alc_stop(sc); 3960 return; 3961 } 3962 alc_init_rr_ring(sc); 3963 alc_init_tx_ring(sc); 3964 alc_init_cmb(sc); 3965 alc_init_smb(sc); 3966 3967 /* Enable all clocks. */ 3968 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3969 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 3970 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 3971 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 3972 CLK_GATING_RXMAC_ENB); 3973 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 3974 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 3975 IDLE_DECISN_TIMER_DEFAULT_1MS); 3976 } else 3977 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 3978 3979 /* Reprogram the station address. */ 3980 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3981 CSR_WRITE_4(sc, ALC_PAR0, 3982 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3983 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3984 /* 3985 * Clear WOL status and disable all WOL feature as WOL 3986 * would interfere Rx operation under normal environments. 3987 */ 3988 CSR_READ_4(sc, ALC_WOL_CFG); 3989 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3990 /* Set Tx descriptor base addresses. */ 3991 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3992 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3993 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3994 /* We don't use high priority ring. */ 3995 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3996 /* Set Tx descriptor counter. */ 3997 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3998 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3999 /* Set Rx descriptor base addresses. */ 4000 paddr = sc->alc_rdata.alc_rx_ring_paddr; 4001 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 4002 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 4003 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4004 /* We use one Rx ring. */ 4005 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 4006 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 4007 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 4008 } 4009 /* Set Rx descriptor counter. */ 4010 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 4011 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 4012 4013 /* 4014 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 4015 * if it do not fit the buffer size. Rx return descriptor holds 4016 * a counter that indicates how many fragments were made by the 4017 * hardware. The buffer size should be multiple of 8 bytes. 4018 * Since hardware has limit on the size of buffer size, always 4019 * use the maximum value. 4020 * For strict-alignment architectures make sure to reduce buffer 4021 * size by 8 bytes to make room for alignment fixup. 4022 */ 4023#ifndef __NO_STRICT_ALIGNMENT 4024 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 4025#else 4026 sc->alc_buf_size = RX_BUF_SIZE_MAX; 4027#endif 4028 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 4029 4030 paddr = sc->alc_rdata.alc_rr_ring_paddr; 4031 /* Set Rx return descriptor base addresses. */ 4032 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 4033 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4034 /* We use one Rx return ring. */ 4035 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 4036 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 4037 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 4038 } 4039 /* Set Rx return descriptor counter. */ 4040 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 4041 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 4042 paddr = sc->alc_rdata.alc_cmb_paddr; 4043 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4044 paddr = sc->alc_rdata.alc_smb_paddr; 4045 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 4046 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4047 4048 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 4049 /* Reconfigure SRAM - Vendor magic. */ 4050 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 4051 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 4052 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 4053 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 4054 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 4055 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 4056 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 4057 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 4058 } 4059 4060 /* Tell hardware that we're ready to load DMA blocks. */ 4061 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 4062 4063 /* Configure interrupt moderation timer. */ 4064 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 4065 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 4066 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 4067 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 4068 /* 4069 * We don't want to automatic interrupt clear as task queue 4070 * for the interrupt should know interrupt status. 4071 */ 4072 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 4073 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 4074 reg |= MASTER_SA_TIMER_ENB; 4075 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 4076 reg |= MASTER_IM_RX_TIMER_ENB; 4077 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 4078 ALC_USECS(sc->alc_int_tx_mod) != 0) 4079 reg |= MASTER_IM_TX_TIMER_ENB; 4080 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 4081 /* 4082 * Disable interrupt re-trigger timer. We don't want automatic 4083 * re-triggering of un-ACKed interrupts. 4084 */ 4085 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 4086 /* Configure CMB. */ 4087 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4088 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 4089 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 4090 ALC_USECS(sc->alc_int_tx_mod)); 4091 } else { 4092 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 4093 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 4094 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 4095 } else 4096 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 4097 } 4098 /* 4099 * Hardware can be configured to issue SMB interrupt based 4100 * on programmed interval. Since there is a callout that is 4101 * invoked for every hz in driver we use that instead of 4102 * relying on periodic SMB interrupt. 4103 */ 4104 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 4105 /* Clear MAC statistics. */ 4106 alc_stats_clear(sc); 4107 4108 /* 4109 * Always use maximum frame size that controller can support. 4110 * Otherwise received frames that has larger frame length 4111 * than alc(4) MTU would be silently dropped in hardware. This 4112 * would make path-MTU discovery hard as sender wouldn't get 4113 * any responses from receiver. alc(4) supports 4114 * multi-fragmented frames on Rx path so it has no issue on 4115 * assembling fragmented frames. Using maximum frame size also 4116 * removes the need to reinitialize hardware when interface 4117 * MTU configuration was changed. 4118 * 4119 * Be conservative in what you do, be liberal in what you 4120 * accept from others - RFC 793. 4121 */ 4122 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 4123 4124 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4125 /* Disable header split(?) */ 4126 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 4127 4128 /* Configure IPG/IFG parameters. */ 4129 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 4130 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 4131 IPG_IFG_IPGT_MASK) | 4132 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 4133 IPG_IFG_MIFG_MASK) | 4134 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 4135 IPG_IFG_IPG1_MASK) | 4136 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 4137 IPG_IFG_IPG2_MASK)); 4138 /* Set parameters for half-duplex media. */ 4139 CSR_WRITE_4(sc, ALC_HDPX_CFG, 4140 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 4141 HDPX_CFG_LCOL_MASK) | 4142 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 4143 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 4144 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 4145 HDPX_CFG_ABEBT_MASK) | 4146 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 4147 HDPX_CFG_JAMIPG_MASK)); 4148 } 4149 4150 /* 4151 * Set TSO/checksum offload threshold. For frames that is 4152 * larger than this threshold, hardware wouldn't do 4153 * TSO/checksum offloading. 4154 */ 4155 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 4156 TSO_OFFLOAD_THRESH_MASK; 4157 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 4158 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 4159 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 4160 /* Configure TxQ. */ 4161 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 4162 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 4163 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 4164 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4165 reg >>= 1; 4166 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 4167 TXQ_CFG_TD_BURST_MASK; 4168 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 4169 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 4170 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4171 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 4172 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 4173 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 4174 HQTD_CFG_BURST_ENB); 4175 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 4176 reg = WRR_PRI_RESTRICT_NONE; 4177 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 4178 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 4179 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 4180 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 4181 CSR_WRITE_4(sc, ALC_WRR, reg); 4182 } else { 4183 /* Configure Rx free descriptor pre-fetching. */ 4184 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 4185 ((RX_RD_FREE_THRESH_HI_DEFAULT << 4186 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 4187 ((RX_RD_FREE_THRESH_LO_DEFAULT << 4188 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 4189 } 4190 4191 /* 4192 * Configure flow control parameters. 4193 * XON : 80% of Rx FIFO 4194 * XOFF : 30% of Rx FIFO 4195 */ 4196 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4197 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4198 reg &= SRAM_RX_FIFO_LEN_MASK; 4199 reg *= 8; 4200 if (reg > 8 * 1024) 4201 reg -= RX_FIFO_PAUSE_816X_RSVD; 4202 else 4203 reg -= RX_BUF_SIZE_MAX; 4204 reg /= 8; 4205 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4206 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4207 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4208 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 4209 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4210 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4211 } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 4212 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 4213 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4214 rxf_hi = (reg * 8) / 10; 4215 rxf_lo = (reg * 3) / 10; 4216 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4217 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4218 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4219 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4220 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4221 } 4222 4223 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4224 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 4225 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 4226 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 4227 } 4228 4229 /* Configure RxQ. */ 4230 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 4231 RXQ_CFG_RD_BURST_MASK; 4232 reg |= RXQ_CFG_RSS_MODE_DIS; 4233 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4234 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 4235 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 4236 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 4237 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 4238 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4239 } else { 4240 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 4241 sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2) 4242 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4243 } 4244 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4245 4246 /* Configure DMA parameters. */ 4247 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 4248 reg |= sc->alc_rcb; 4249 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 4250 reg |= DMA_CFG_CMB_ENB; 4251 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 4252 reg |= DMA_CFG_SMB_ENB; 4253 else 4254 reg |= DMA_CFG_SMB_DIS; 4255 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 4256 DMA_CFG_RD_BURST_SHIFT; 4257 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 4258 DMA_CFG_WR_BURST_SHIFT; 4259 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 4260 DMA_CFG_RD_DELAY_CNT_MASK; 4261 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 4262 DMA_CFG_WR_DELAY_CNT_MASK; 4263 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4264 switch (AR816X_REV(sc->alc_rev)) { 4265 case AR816X_REV_A0: 4266 case AR816X_REV_A1: 4267 reg |= DMA_CFG_RD_CHNL_SEL_2; 4268 break; 4269 case AR816X_REV_B0: 4270 /* FALLTHROUGH */ 4271 default: 4272 reg |= DMA_CFG_RD_CHNL_SEL_4; 4273 break; 4274 } 4275 } 4276 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4277 4278 /* 4279 * Configure Tx/Rx MACs. 4280 * - Auto-padding for short frames. 4281 * - Enable CRC generation. 4282 * Actual reconfiguration of MAC for resolved speed/duplex 4283 * is followed after detection of link establishment. 4284 * AR813x/AR815x always does checksum computation regardless 4285 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 4286 * have bug in protocol field in Rx return structure so 4287 * these controllers can't handle fragmented frames. Disable 4288 * Rx checksum offloading until there is a newer controller 4289 * that has sane implementation. 4290 */ 4291 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 4292 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 4293 MAC_CFG_PREAMBLE_MASK); 4294 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 4295 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 4296 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 4297 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4298 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 4299 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 4300 reg |= MAC_CFG_SPEED_10_100; 4301 else 4302 reg |= MAC_CFG_SPEED_1000; 4303 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4304 4305 /* Set up the receive filter. */ 4306 alc_rxfilter(sc); 4307 alc_rxvlan(sc); 4308 4309 /* Acknowledge all pending interrupts and clear it. */ 4310 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 4311 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4312 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 4313 4314 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4315 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4316 4317 sc->alc_flags &= ~ALC_FLAG_LINK; 4318 /* Switch to the current media. */ 4319 alc_mediachange_locked(sc); 4320 4321 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 4322} 4323 4324static void 4325alc_stop(struct alc_softc *sc) 4326{ 4327 struct ifnet *ifp; 4328 struct alc_txdesc *txd; 4329 struct alc_rxdesc *rxd; 4330 uint32_t reg; 4331 int i; 4332 4333 ALC_LOCK_ASSERT(sc); 4334 /* 4335 * Mark the interface down and cancel the watchdog timer. 4336 */ 4337 ifp = sc->alc_ifp; 4338 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4339 sc->alc_flags &= ~ALC_FLAG_LINK; 4340 callout_stop(&sc->alc_tick_ch); 4341 sc->alc_watchdog_timer = 0; 4342 alc_stats_update(sc); 4343 /* Disable interrupts. */ 4344 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 4345 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4346 /* Disable DMA. */ 4347 reg = CSR_READ_4(sc, ALC_DMA_CFG); 4348 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 4349 reg |= DMA_CFG_SMB_DIS; 4350 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4351 DELAY(1000); 4352 /* Stop Rx/Tx MACs. */ 4353 alc_stop_mac(sc); 4354 /* Disable interrupts which might be touched in taskq handler. */ 4355 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4356 /* Disable L0s/L1s */ 4357 alc_aspm(sc, 0, IFM_UNKNOWN); 4358 /* Reclaim Rx buffers that have been processed. */ 4359 if (sc->alc_cdata.alc_rxhead != NULL) 4360 m_freem(sc->alc_cdata.alc_rxhead); 4361 ALC_RXCHAIN_RESET(sc); 4362 /* 4363 * Free Tx/Rx mbufs still in the queues. 4364 */ 4365 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4366 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4367 if (rxd->rx_m != NULL) { 4368 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 4369 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4370 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 4371 rxd->rx_dmamap); 4372 m_freem(rxd->rx_m); 4373 rxd->rx_m = NULL; 4374 } 4375 } 4376 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4377 txd = &sc->alc_cdata.alc_txdesc[i]; 4378 if (txd->tx_m != NULL) { 4379 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 4380 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4381 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 4382 txd->tx_dmamap); 4383 m_freem(txd->tx_m); 4384 txd->tx_m = NULL; 4385 } 4386 } 4387} 4388 4389static void 4390alc_stop_mac(struct alc_softc *sc) 4391{ 4392 uint32_t reg; 4393 int i; 4394 4395 alc_stop_queue(sc); 4396 /* Disable Rx/Tx MAC. */ 4397 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4398 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 4399 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 4400 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4401 } 4402 for (i = ALC_TIMEOUT; i > 0; i--) { 4403 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4404 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 4405 break; 4406 DELAY(10); 4407 } 4408 if (i == 0) 4409 device_printf(sc->alc_dev, 4410 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 4411} 4412 4413static void 4414alc_start_queue(struct alc_softc *sc) 4415{ 4416 uint32_t qcfg[] = { 4417 0, 4418 RXQ_CFG_QUEUE0_ENB, 4419 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 4420 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 4421 RXQ_CFG_ENB 4422 }; 4423 uint32_t cfg; 4424 4425 ALC_LOCK_ASSERT(sc); 4426 4427 /* Enable RxQ. */ 4428 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 4429 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4430 cfg &= ~RXQ_CFG_ENB; 4431 cfg |= qcfg[1]; 4432 } else 4433 cfg |= RXQ_CFG_QUEUE0_ENB; 4434 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 4435 /* Enable TxQ. */ 4436 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 4437 cfg |= TXQ_CFG_ENB; 4438 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 4439} 4440 4441static void 4442alc_stop_queue(struct alc_softc *sc) 4443{ 4444 uint32_t reg; 4445 int i; 4446 4447 /* Disable RxQ. */ 4448 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 4449 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4450 if ((reg & RXQ_CFG_ENB) != 0) { 4451 reg &= ~RXQ_CFG_ENB; 4452 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4453 } 4454 } else { 4455 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 4456 reg &= ~RXQ_CFG_QUEUE0_ENB; 4457 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4458 } 4459 } 4460 /* Disable TxQ. */ 4461 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 4462 if ((reg & TXQ_CFG_ENB) != 0) { 4463 reg &= ~TXQ_CFG_ENB; 4464 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 4465 } 4466 DELAY(40); 4467 for (i = ALC_TIMEOUT; i > 0; i--) { 4468 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4469 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 4470 break; 4471 DELAY(10); 4472 } 4473 if (i == 0) 4474 device_printf(sc->alc_dev, 4475 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 4476} 4477 4478static void 4479alc_init_tx_ring(struct alc_softc *sc) 4480{ 4481 struct alc_ring_data *rd; 4482 struct alc_txdesc *txd; 4483 int i; 4484 4485 ALC_LOCK_ASSERT(sc); 4486 4487 sc->alc_cdata.alc_tx_prod = 0; 4488 sc->alc_cdata.alc_tx_cons = 0; 4489 sc->alc_cdata.alc_tx_cnt = 0; 4490 4491 rd = &sc->alc_rdata; 4492 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 4493 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4494 txd = &sc->alc_cdata.alc_txdesc[i]; 4495 txd->tx_m = NULL; 4496 } 4497 4498 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 4499 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 4500} 4501 4502static int 4503alc_init_rx_ring(struct alc_softc *sc) 4504{ 4505 struct alc_ring_data *rd; 4506 struct alc_rxdesc *rxd; 4507 int i; 4508 4509 ALC_LOCK_ASSERT(sc); 4510 4511 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 4512 sc->alc_morework = 0; 4513 rd = &sc->alc_rdata; 4514 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 4515 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4516 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4517 rxd->rx_m = NULL; 4518 rxd->rx_desc = &rd->alc_rx_ring[i]; 4519 if (alc_newbuf(sc, rxd) != 0) 4520 return (ENOBUFS); 4521 } 4522 4523 /* 4524 * Since controller does not update Rx descriptors, driver 4525 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 4526 * is enough to ensure coherence. 4527 */ 4528 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 4529 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 4530 /* Let controller know availability of new Rx buffers. */ 4531 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 4532 4533 return (0); 4534} 4535 4536static void 4537alc_init_rr_ring(struct alc_softc *sc) 4538{ 4539 struct alc_ring_data *rd; 4540 4541 ALC_LOCK_ASSERT(sc); 4542 4543 sc->alc_cdata.alc_rr_cons = 0; 4544 ALC_RXCHAIN_RESET(sc); 4545 4546 rd = &sc->alc_rdata; 4547 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 4548 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 4549 sc->alc_cdata.alc_rr_ring_map, 4550 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4551} 4552 4553static void 4554alc_init_cmb(struct alc_softc *sc) 4555{ 4556 struct alc_ring_data *rd; 4557 4558 ALC_LOCK_ASSERT(sc); 4559 4560 rd = &sc->alc_rdata; 4561 bzero(rd->alc_cmb, ALC_CMB_SZ); 4562 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 4563 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4564} 4565 4566static void 4567alc_init_smb(struct alc_softc *sc) 4568{ 4569 struct alc_ring_data *rd; 4570 4571 ALC_LOCK_ASSERT(sc); 4572 4573 rd = &sc->alc_rdata; 4574 bzero(rd->alc_smb, ALC_SMB_SZ); 4575 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 4576 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4577} 4578 4579static void 4580alc_rxvlan(struct alc_softc *sc) 4581{ 4582 struct ifnet *ifp; 4583 uint32_t reg; 4584 4585 ALC_LOCK_ASSERT(sc); 4586 4587 ifp = sc->alc_ifp; 4588 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4589 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 4590 reg |= MAC_CFG_VLAN_TAG_STRIP; 4591 else 4592 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 4593 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4594} 4595 4596static void 4597alc_rxfilter(struct alc_softc *sc) 4598{ 4599 struct ifnet *ifp; 4600 struct ifmultiaddr *ifma; 4601 uint32_t crc; 4602 uint32_t mchash[2]; 4603 uint32_t rxcfg; 4604 4605 ALC_LOCK_ASSERT(sc); 4606 4607 ifp = sc->alc_ifp; 4608 4609 bzero(mchash, sizeof(mchash)); 4610 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 4611 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 4612 if ((ifp->if_flags & IFF_BROADCAST) != 0) 4613 rxcfg |= MAC_CFG_BCAST; 4614 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 4615 if ((ifp->if_flags & IFF_PROMISC) != 0) 4616 rxcfg |= MAC_CFG_PROMISC; 4617 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 4618 rxcfg |= MAC_CFG_ALLMULTI; 4619 mchash[0] = 0xFFFFFFFF; 4620 mchash[1] = 0xFFFFFFFF; 4621 goto chipit; 4622 } 4623 4624 if_maddr_rlock(ifp); 4625 CK_STAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 4626 if (ifma->ifma_addr->sa_family != AF_LINK) 4627 continue; 4628 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 4629 ifma->ifma_addr), ETHER_ADDR_LEN); 4630 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 4631 } 4632 if_maddr_runlock(ifp); 4633 4634chipit: 4635 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 4636 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 4637 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 4638} 4639 4640static int 4641sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4642{ 4643 int error, value; 4644 4645 if (arg1 == NULL) 4646 return (EINVAL); 4647 value = *(int *)arg1; 4648 error = sysctl_handle_int(oidp, &value, 0, req); 4649 if (error || req->newptr == NULL) 4650 return (error); 4651 if (value < low || value > high) 4652 return (EINVAL); 4653 *(int *)arg1 = value; 4654 4655 return (0); 4656} 4657 4658static int 4659sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 4660{ 4661 return (sysctl_int_range(oidp, arg1, arg2, req, 4662 ALC_PROC_MIN, ALC_PROC_MAX)); 4663} 4664 4665static int 4666sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 4667{ 4668 4669 return (sysctl_int_range(oidp, arg1, arg2, req, 4670 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 4671} 4672 4673#ifdef NETDUMP 4674static void 4675alc_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 4676{ 4677 struct alc_softc *sc; 4678 4679 sc = if_getsoftc(ifp); 4680 KASSERT(sc->alc_buf_size <= MCLBYTES, ("incorrect cluster size")); 4681 4682 *nrxr = ALC_RX_RING_CNT; 4683 *ncl = NETDUMP_MAX_IN_FLIGHT; 4684 *clsize = MCLBYTES; 4685} 4686 4687static void 4688alc_netdump_event(struct ifnet *ifp __unused, enum netdump_ev event __unused) 4689{ 4690} 4691 4692static int 4693alc_netdump_transmit(struct ifnet *ifp, struct mbuf *m) 4694{ 4695 struct alc_softc *sc; 4696 int error; 4697 4698 sc = if_getsoftc(ifp); 4699 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4700 IFF_DRV_RUNNING) 4701 return (EBUSY); 4702 4703 error = alc_encap(sc, &m); 4704 if (error == 0) 4705 alc_start_tx(sc); 4706 return (error); 4707} 4708 4709static int 4710alc_netdump_poll(struct ifnet *ifp, int count) 4711{ 4712 struct alc_softc *sc; 4713 4714 sc = if_getsoftc(ifp); 4715 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4716 IFF_DRV_RUNNING) 4717 return (EBUSY); 4718 4719 alc_txeof(sc); 4720 return (alc_rxintr(sc, count)); 4721} 4722#endif /* NETDUMP */ 4723