1/*- 2 * Core routines and tables shareable across OS platforms. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * Copyright (c) 1994-2002 Justin T. Gibbs. 7 * Copyright (c) 2000-2002 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $ 43 */ 44 45#ifdef __linux__ 46#include "aic7xxx_osm.h" 47#include "aic7xxx_inline.h" 48#include "aicasm/aicasm_insformat.h" 49#else 50#include <sys/cdefs.h> 51__FBSDID("$FreeBSD$"); 52#include <dev/aic7xxx/aic7xxx_osm.h> 53#include <dev/aic7xxx/aic7xxx_inline.h> 54#include <dev/aic7xxx/aicasm/aicasm_insformat.h> 55#endif 56 57/****************************** Softc Data ************************************/ 58struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq); 59 60/***************************** Lookup Tables **********************************/ 61char *ahc_chip_names[] = 62{ 63 "NONE", 64 "aic7770", 65 "aic7850", 66 "aic7855", 67 "aic7859", 68 "aic7860", 69 "aic7870", 70 "aic7880", 71 "aic7895", 72 "aic7895C", 73 "aic7890/91", 74 "aic7896/97", 75 "aic7892", 76 "aic7899" 77}; 78 79/* 80 * Hardware error codes. 81 */ 82struct ahc_hard_error_entry { 83 uint8_t errno; 84 char *errmesg; 85}; 86 87static struct ahc_hard_error_entry ahc_hard_errors[] = { 88 { ILLHADDR, "Illegal Host Access" }, 89 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 90 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 91 { SQPARERR, "Sequencer Parity Error" }, 92 { DPARERR, "Data-path Parity Error" }, 93 { MPARERR, "Scratch or SCB Memory Parity Error" }, 94 { PCIERRSTAT, "PCI Error detected" }, 95 { CIOPARERR, "CIOBUS Parity Error" }, 96}; 97static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors); 98 99static struct ahc_phase_table_entry ahc_phase_table[] = 100{ 101 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 102 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 103 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 104 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 105 { P_COMMAND, MSG_NOOP, "in Command phase" }, 106 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 107 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 108 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 109 { P_BUSFREE, MSG_NOOP, "while idle" }, 110 { 0, MSG_NOOP, "in unknown phase" } 111}; 112 113/* 114 * In most cases we only wish to itterate over real phases, so 115 * exclude the last element from the count. 116 */ 117static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1; 118 119/* 120 * Valid SCSIRATE values. (p. 3-17) 121 * Provides a mapping of transfer periods in ns to the proper value to 122 * stick in the scsixfer reg. 123 */ 124static struct ahc_syncrate ahc_syncrates[] = 125{ 126 /* ultra2 fast/ultra period rate */ 127 { 0x42, 0x000, 9, "80.0" }, 128 { 0x03, 0x000, 10, "40.0" }, 129 { 0x04, 0x000, 11, "33.0" }, 130 { 0x05, 0x100, 12, "20.0" }, 131 { 0x06, 0x110, 15, "16.0" }, 132 { 0x07, 0x120, 18, "13.4" }, 133 { 0x08, 0x000, 25, "10.0" }, 134 { 0x19, 0x010, 31, "8.0" }, 135 { 0x1a, 0x020, 37, "6.67" }, 136 { 0x1b, 0x030, 43, "5.7" }, 137 { 0x1c, 0x040, 50, "5.0" }, 138 { 0x00, 0x050, 56, "4.4" }, 139 { 0x00, 0x060, 62, "4.0" }, 140 { 0x00, 0x070, 68, "3.6" }, 141 { 0x00, 0x000, 0, NULL } 142}; 143 144/* Our Sequencer Program */ 145#include "aic7xxx_seq.h" 146 147/**************************** Function Declarations ***************************/ 148static void ahc_force_renegotiation(struct ahc_softc *ahc, 149 struct ahc_devinfo *devinfo); 150static struct ahc_tmode_tstate* 151 ahc_alloc_tstate(struct ahc_softc *ahc, 152 u_int scsi_id, char channel); 153#ifdef AHC_TARGET_MODE 154static void ahc_free_tstate(struct ahc_softc *ahc, 155 u_int scsi_id, char channel, int force); 156#endif 157static struct ahc_syncrate* 158 ahc_devlimited_syncrate(struct ahc_softc *ahc, 159 struct ahc_initiator_tinfo *, 160 u_int *period, 161 u_int *ppr_options, 162 role_t role); 163static void ahc_update_pending_scbs(struct ahc_softc *ahc); 164static void ahc_fetch_devinfo(struct ahc_softc *ahc, 165 struct ahc_devinfo *devinfo); 166static void ahc_scb_devinfo(struct ahc_softc *ahc, 167 struct ahc_devinfo *devinfo, 168 struct scb *scb); 169static void ahc_assert_atn(struct ahc_softc *ahc); 170static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, 171 struct ahc_devinfo *devinfo, 172 struct scb *scb); 173static void ahc_build_transfer_msg(struct ahc_softc *ahc, 174 struct ahc_devinfo *devinfo); 175static void ahc_construct_sdtr(struct ahc_softc *ahc, 176 struct ahc_devinfo *devinfo, 177 u_int period, u_int offset); 178static void ahc_construct_wdtr(struct ahc_softc *ahc, 179 struct ahc_devinfo *devinfo, 180 u_int bus_width); 181static void ahc_construct_ppr(struct ahc_softc *ahc, 182 struct ahc_devinfo *devinfo, 183 u_int period, u_int offset, 184 u_int bus_width, u_int ppr_options); 185static void ahc_clear_msg_state(struct ahc_softc *ahc); 186static void ahc_handle_proto_violation(struct ahc_softc *ahc); 187static void ahc_handle_message_phase(struct ahc_softc *ahc); 188typedef enum { 189 AHCMSG_1B, 190 AHCMSG_2B, 191 AHCMSG_EXT 192} ahc_msgtype; 193static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, 194 u_int msgval, int full); 195static int ahc_parse_msg(struct ahc_softc *ahc, 196 struct ahc_devinfo *devinfo); 197static int ahc_handle_msg_reject(struct ahc_softc *ahc, 198 struct ahc_devinfo *devinfo); 199static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc, 200 struct ahc_devinfo *devinfo); 201static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc); 202static void ahc_handle_devreset(struct ahc_softc *ahc, 203 struct ahc_devinfo *devinfo, 204 cam_status status, char *message, 205 int verbose_level); 206#ifdef AHC_TARGET_MODE 207static void ahc_setup_target_msgin(struct ahc_softc *ahc, 208 struct ahc_devinfo *devinfo, 209 struct scb *scb); 210#endif 211 212static bus_dmamap_callback_t ahc_dmamap_cb; 213static void ahc_build_free_scb_list(struct ahc_softc *ahc); 214static int ahc_init_scbdata(struct ahc_softc *ahc); 215static void ahc_fini_scbdata(struct ahc_softc *ahc); 216static void ahc_qinfifo_requeue(struct ahc_softc *ahc, 217 struct scb *prev_scb, 218 struct scb *scb); 219static int ahc_qinfifo_count(struct ahc_softc *ahc); 220static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, 221 u_int prev, u_int scbptr); 222static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); 223static u_int ahc_rem_wscb(struct ahc_softc *ahc, 224 u_int scbpos, u_int prev); 225static void ahc_reset_current_bus(struct ahc_softc *ahc); 226#ifdef AHC_DUMP_SEQ 227static void ahc_dumpseq(struct ahc_softc *ahc); 228#endif 229static int ahc_loadseq(struct ahc_softc *ahc); 230static int ahc_check_patch(struct ahc_softc *ahc, 231 struct patch **start_patch, 232 u_int start_instr, u_int *skip_addr); 233static void ahc_download_instr(struct ahc_softc *ahc, 234 u_int instrptr, uint8_t *dconsts); 235static int ahc_other_scb_timeout(struct ahc_softc *ahc, 236 struct scb *scb, 237 struct scb *other_scb); 238#ifdef AHC_TARGET_MODE 239static void ahc_queue_lstate_event(struct ahc_softc *ahc, 240 struct ahc_tmode_lstate *lstate, 241 u_int initiator_id, 242 u_int event_type, 243 u_int event_arg); 244static void ahc_update_scsiid(struct ahc_softc *ahc, 245 u_int targid_mask); 246static int ahc_handle_target_cmd(struct ahc_softc *ahc, 247 struct target_cmd *cmd); 248#endif 249/************************* Sequencer Execution Control ************************/ 250/* 251 * Restart the sequencer program from address zero 252 */ 253void 254ahc_restart(struct ahc_softc *ahc) 255{ 256 257 ahc_pause(ahc); 258 259 /* No more pending messages. */ 260 ahc_clear_msg_state(ahc); 261 262 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */ 263 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */ 264 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 265 ahc_outb(ahc, LASTPHASE, P_BUSFREE); 266 ahc_outb(ahc, SAVED_SCSIID, 0xFF); 267 ahc_outb(ahc, SAVED_LUN, 0xFF); 268 269 /* 270 * Ensure that the sequencer's idea of TQINPOS 271 * matches our own. The sequencer increments TQINPOS 272 * only after it sees a DMA complete and a reset could 273 * occur before the increment leaving the kernel to believe 274 * the command arrived but the sequencer to not. 275 */ 276 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 277 278 /* Always allow reselection */ 279 ahc_outb(ahc, SCSISEQ, 280 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 281 if ((ahc->features & AHC_CMD_CHAN) != 0) { 282 /* Ensure that no DMA operations are in progress */ 283 ahc_outb(ahc, CCSCBCNT, 0); 284 ahc_outb(ahc, CCSGCTL, 0); 285 ahc_outb(ahc, CCSCBCTL, 0); 286 } 287 /* 288 * If we were in the process of DMA'ing SCB data into 289 * an SCB, replace that SCB on the free list. This prevents 290 * an SCB leak. 291 */ 292 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) { 293 ahc_add_curscb_to_free_list(ahc); 294 ahc_outb(ahc, SEQ_FLAGS2, 295 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA); 296 } 297 298 /* 299 * Clear any pending sequencer interrupt. It is no 300 * longer relevant since we're resetting the Program 301 * Counter. 302 */ 303 ahc_outb(ahc, CLRINT, CLRSEQINT); 304 305 ahc_outb(ahc, MWI_RESIDUAL, 0); 306 ahc_outb(ahc, SEQCTL, ahc->seqctl); 307 ahc_outb(ahc, SEQADDR0, 0); 308 ahc_outb(ahc, SEQADDR1, 0); 309 310 ahc_unpause(ahc); 311} 312 313/************************* Input/Output Queues ********************************/ 314void 315ahc_run_qoutfifo(struct ahc_softc *ahc) 316{ 317 struct scb *scb; 318 u_int scb_index; 319 320 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 321 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 322 323 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 324 if ((ahc->qoutfifonext & 0x03) == 0x03) { 325 u_int modnext; 326 327 /* 328 * Clear 32bits of QOUTFIFO at a time 329 * so that we don't clobber an incoming 330 * byte DMA to the array on architectures 331 * that only support 32bit load and store 332 * operations. 333 */ 334 modnext = ahc->qoutfifonext & ~0x3; 335 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL; 336 aic_dmamap_sync(ahc, ahc->shared_data_dmat, 337 ahc->shared_data_dmamap, 338 /*offset*/modnext, /*len*/4, 339 BUS_DMASYNC_PREREAD); 340 } 341 ahc->qoutfifonext++; 342 343 scb = ahc_lookup_scb(ahc, scb_index); 344 if (scb == NULL) { 345 printf("%s: WARNING no command for scb %d " 346 "(cmdcmplt)\nQOUTPOS = %d\n", 347 ahc_name(ahc), scb_index, 348 (ahc->qoutfifonext - 1) & 0xFF); 349 continue; 350 } 351 352 /* 353 * Save off the residual 354 * if there is one. 355 */ 356 ahc_update_residual(ahc, scb); 357 ahc_done(ahc, scb); 358 } 359} 360 361void 362ahc_run_untagged_queues(struct ahc_softc *ahc) 363{ 364 int i; 365 366 for (i = 0; i < 16; i++) 367 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]); 368} 369 370void 371ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue) 372{ 373 struct scb *scb; 374 375 if (ahc->untagged_queue_lock != 0) 376 return; 377 378 if ((scb = TAILQ_FIRST(queue)) != NULL 379 && (scb->flags & SCB_ACTIVE) == 0) { 380 scb->flags |= SCB_ACTIVE; 381 /* 382 * Timers are disabled while recovery is in progress. 383 */ 384 aic_scb_timer_start(scb); 385 ahc_queue_scb(ahc, scb); 386 } 387} 388 389/************************* Interrupt Handling *********************************/ 390void 391ahc_handle_brkadrint(struct ahc_softc *ahc) 392{ 393 /* 394 * We upset the sequencer :-( 395 * Lookup the error message 396 */ 397 int i; 398 int error; 399 400 error = ahc_inb(ahc, ERROR); 401 for (i = 0; error != 1 && i < num_errors; i++) 402 error >>= 1; 403 printf("%s: brkadrint, %s at seqaddr = 0x%x\n", 404 ahc_name(ahc), ahc_hard_errors[i].errmesg, 405 ahc_inb(ahc, SEQADDR0) | 406 (ahc_inb(ahc, SEQADDR1) << 8)); 407 408 ahc_dump_card_state(ahc); 409 410 /* Tell everyone that this HBA is no longer available */ 411 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS, 412 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 413 CAM_NO_HBA); 414 415 /* Disable all interrupt sources by resetting the controller */ 416 ahc_shutdown(ahc); 417} 418 419void 420ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 421{ 422 struct scb *scb; 423 struct ahc_devinfo devinfo; 424 425 ahc_fetch_devinfo(ahc, &devinfo); 426 427 /* 428 * Clear the upper byte that holds SEQINT status 429 * codes and clear the SEQINT bit. We will unpause 430 * the sequencer, if appropriate, after servicing 431 * the request. 432 */ 433 ahc_outb(ahc, CLRINT, CLRSEQINT); 434 switch (intstat & SEQINT_MASK) { 435 case BAD_STATUS: 436 { 437 u_int scb_index; 438 struct hardware_scb *hscb; 439 440 /* 441 * Set the default return value to 0 (don't 442 * send sense). The sense code will change 443 * this if needed. 444 */ 445 ahc_outb(ahc, RETURN_1, 0); 446 447 /* 448 * The sequencer will notify us when a command 449 * has an error that would be of interest to 450 * the kernel. This allows us to leave the sequencer 451 * running in the common case of command completes 452 * without error. The sequencer will already have 453 * dma'd the SCB back up to us, so we can reference 454 * the in kernel copy directly. 455 */ 456 scb_index = ahc_inb(ahc, SCB_TAG); 457 scb = ahc_lookup_scb(ahc, scb_index); 458 if (scb == NULL) { 459 ahc_print_devinfo(ahc, &devinfo); 460 printf("ahc_intr - referenced scb " 461 "not valid during seqint 0x%x scb(%d)\n", 462 intstat, scb_index); 463 ahc_dump_card_state(ahc); 464 panic("for safety"); 465 goto unpause; 466 } 467 468 hscb = scb->hscb; 469 470 /* Don't want to clobber the original sense code */ 471 if ((scb->flags & SCB_SENSE) != 0) { 472 /* 473 * Clear the SCB_SENSE Flag and have 474 * the sequencer do a normal command 475 * complete. 476 */ 477 scb->flags &= ~SCB_SENSE; 478 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 479 break; 480 } 481 aic_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR); 482 /* Freeze the queue until the client sees the error. */ 483 ahc_freeze_devq(ahc, scb); 484 aic_freeze_scb(scb); 485 aic_set_scsi_status(scb, hscb->shared_data.status.scsi_status); 486 switch (hscb->shared_data.status.scsi_status) { 487 case SCSI_STATUS_OK: 488 printf("%s: Interrupted for staus of 0???\n", 489 ahc_name(ahc)); 490 break; 491 case SCSI_STATUS_CMD_TERMINATED: 492 case SCSI_STATUS_CHECK_COND: 493 { 494 struct ahc_dma_seg *sg; 495 struct scsi_sense *sc; 496 struct ahc_initiator_tinfo *targ_info; 497 struct ahc_tmode_tstate *tstate; 498 struct ahc_transinfo *tinfo; 499#ifdef AHC_DEBUG 500 if (ahc_debug & AHC_SHOW_SENSE) { 501 ahc_print_path(ahc, scb); 502 printf("SCB %d: requests Check Status\n", 503 scb->hscb->tag); 504 } 505#endif 506 507 if (aic_perform_autosense(scb) == 0) 508 break; 509 510 targ_info = ahc_fetch_transinfo(ahc, 511 devinfo.channel, 512 devinfo.our_scsiid, 513 devinfo.target, 514 &tstate); 515 tinfo = &targ_info->curr; 516 sg = scb->sg_list; 517 sc = (struct scsi_sense *)(&hscb->shared_data.cdb); 518 /* 519 * Save off the residual if there is one. 520 */ 521 ahc_update_residual(ahc, scb); 522#ifdef AHC_DEBUG 523 if (ahc_debug & AHC_SHOW_SENSE) { 524 ahc_print_path(ahc, scb); 525 printf("Sending Sense\n"); 526 } 527#endif 528 sg->addr = ahc_get_sense_bufaddr(ahc, scb); 529 sg->len = aic_get_sense_bufsize(ahc, scb); 530 sg->len |= AHC_DMA_LAST_SEG; 531 532 /* Fixup byte order */ 533 sg->addr = aic_htole32(sg->addr); 534 sg->len = aic_htole32(sg->len); 535 536 sc->opcode = REQUEST_SENSE; 537 sc->byte2 = 0; 538 if (tinfo->protocol_version <= SCSI_REV_2 539 && SCB_GET_LUN(scb) < 8) 540 sc->byte2 = SCB_GET_LUN(scb) << 5; 541 sc->unused[0] = 0; 542 sc->unused[1] = 0; 543 sc->length = sg->len; 544 sc->control = 0; 545 546 /* 547 * We can't allow the target to disconnect. 548 * This will be an untagged transaction and 549 * having the target disconnect will make this 550 * transaction indestinguishable from outstanding 551 * tagged transactions. 552 */ 553 hscb->control = 0; 554 555 /* 556 * This request sense could be because the 557 * the device lost power or in some other 558 * way has lost our transfer negotiations. 559 * Renegotiate if appropriate. Unit attention 560 * errors will be reported before any data 561 * phases occur. 562 */ 563 if (aic_get_residual(scb) 564 == aic_get_transfer_length(scb)) { 565 ahc_update_neg_request(ahc, &devinfo, 566 tstate, targ_info, 567 AHC_NEG_IF_NON_ASYNC); 568 } 569 if (tstate->auto_negotiate & devinfo.target_mask) { 570 hscb->control |= MK_MESSAGE; 571 scb->flags &= ~SCB_NEGOTIATE; 572 scb->flags |= SCB_AUTO_NEGOTIATE; 573 } 574 hscb->cdb_len = sizeof(*sc); 575 hscb->dataptr = sg->addr; 576 hscb->datacnt = sg->len; 577 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID; 578 hscb->sgptr = aic_htole32(hscb->sgptr); 579 scb->sg_count = 1; 580 scb->flags |= SCB_SENSE; 581 ahc_qinfifo_requeue_tail(ahc, scb); 582 ahc_outb(ahc, RETURN_1, SEND_SENSE); 583 /* 584 * Ensure we have enough time to actually 585 * retrieve the sense, but only schedule 586 * the timer if we are not in recovery or 587 * this is a recovery SCB that is allowed 588 * to have an active timer. 589 */ 590 if (ahc->scb_data->recovery_scbs == 0 591 || (scb->flags & SCB_RECOVERY_SCB) != 0) 592 aic_scb_timer_reset(scb, 5 * 1000); 593 break; 594 } 595 default: 596 break; 597 } 598 break; 599 } 600 case NO_MATCH: 601 { 602 /* Ensure we don't leave the selection hardware on */ 603 ahc_outb(ahc, SCSISEQ, 604 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 605 606 printf("%s:%c:%d: no active SCB for reconnecting " 607 "target - issuing BUS DEVICE RESET\n", 608 ahc_name(ahc), devinfo.channel, devinfo.target); 609 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 610 "ARG_1 == 0x%x ACCUM = 0x%x\n", 611 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 612 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 613 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 614 "SINDEX == 0x%x\n", 615 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 616 ahc_index_busy_tcl(ahc, 617 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 618 ahc_inb(ahc, SAVED_LUN))), 619 ahc_inb(ahc, SINDEX)); 620 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 621 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 622 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 623 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 624 ahc_inb(ahc, SCB_CONTROL)); 625 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 626 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 627 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0)); 628 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL)); 629 ahc_dump_card_state(ahc); 630 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 631 ahc->msgout_len = 1; 632 ahc->msgout_index = 0; 633 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 634 ahc_outb(ahc, MSG_OUT, HOST_MSG); 635 ahc_assert_atn(ahc); 636 break; 637 } 638 case SEND_REJECT: 639 { 640 u_int rejbyte = ahc_inb(ahc, ACCUM); 641 printf("%s:%c:%d: Warning - unknown message received from " 642 "target (0x%x). Rejecting\n", 643 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 644 break; 645 } 646 case PROTO_VIOLATION: 647 { 648 ahc_handle_proto_violation(ahc); 649 break; 650 } 651 case IGN_WIDE_RES: 652 ahc_handle_ign_wide_residue(ahc, &devinfo); 653 break; 654 case PDATA_REINIT: 655 ahc_reinitialize_dataptrs(ahc); 656 break; 657 case BAD_PHASE: 658 { 659 u_int lastphase; 660 661 lastphase = ahc_inb(ahc, LASTPHASE); 662 printf("%s:%c:%d: unknown scsi bus phase %x, " 663 "lastphase = 0x%x. Attempting to continue\n", 664 ahc_name(ahc), devinfo.channel, devinfo.target, 665 lastphase, ahc_inb(ahc, SCSISIGI)); 666 break; 667 } 668 case MISSED_BUSFREE: 669 { 670 u_int lastphase; 671 672 lastphase = ahc_inb(ahc, LASTPHASE); 673 printf("%s:%c:%d: Missed busfree. " 674 "Lastphase = 0x%x, Curphase = 0x%x\n", 675 ahc_name(ahc), devinfo.channel, devinfo.target, 676 lastphase, ahc_inb(ahc, SCSISIGI)); 677 ahc_restart(ahc); 678 return; 679 } 680 case HOST_MSG_LOOP: 681 { 682 /* 683 * The sequencer has encountered a message phase 684 * that requires host assistance for completion. 685 * While handling the message phase(s), we will be 686 * notified by the sequencer after each byte is 687 * transferred so we can track bus phase changes. 688 * 689 * If this is the first time we've seen a HOST_MSG_LOOP 690 * interrupt, initialize the state of the host message 691 * loop. 692 */ 693 if (ahc->msg_type == MSG_TYPE_NONE) { 694 struct scb *scb; 695 u_int scb_index; 696 u_int bus_phase; 697 698 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 699 if (bus_phase != P_MESGIN 700 && bus_phase != P_MESGOUT) { 701 printf("ahc_intr: HOST_MSG_LOOP bad " 702 "phase 0x%x\n", 703 bus_phase); 704 /* 705 * Probably transitioned to bus free before 706 * we got here. Just punt the message. 707 */ 708 ahc_clear_intstat(ahc); 709 ahc_restart(ahc); 710 return; 711 } 712 713 scb_index = ahc_inb(ahc, SCB_TAG); 714 scb = ahc_lookup_scb(ahc, scb_index); 715 if (devinfo.role == ROLE_INITIATOR) { 716 if (scb == NULL) 717 panic("HOST_MSG_LOOP with " 718 "invalid SCB %x\n", scb_index); 719 720 if (bus_phase == P_MESGOUT) 721 ahc_setup_initiator_msgout(ahc, 722 &devinfo, 723 scb); 724 else { 725 ahc->msg_type = 726 MSG_TYPE_INITIATOR_MSGIN; 727 ahc->msgin_index = 0; 728 } 729 } 730#ifdef AHC_TARGET_MODE 731 else { 732 if (bus_phase == P_MESGOUT) { 733 ahc->msg_type = 734 MSG_TYPE_TARGET_MSGOUT; 735 ahc->msgin_index = 0; 736 } 737 else 738 ahc_setup_target_msgin(ahc, 739 &devinfo, 740 scb); 741 } 742#endif 743 } 744 745 ahc_handle_message_phase(ahc); 746 break; 747 } 748 case PERR_DETECTED: 749 { 750 /* 751 * If we've cleared the parity error interrupt 752 * but the sequencer still believes that SCSIPERR 753 * is true, it must be that the parity error is 754 * for the currently presented byte on the bus, 755 * and we are not in a phase (data-in) where we will 756 * eventually ack this byte. Ack the byte and 757 * throw it away in the hope that the target will 758 * take us to message out to deliver the appropriate 759 * error message. 760 */ 761 if ((intstat & SCSIINT) == 0 762 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 763 764 if ((ahc->features & AHC_DT) == 0) { 765 u_int curphase; 766 767 /* 768 * The hardware will only let you ack bytes 769 * if the expected phase in SCSISIGO matches 770 * the current phase. Make sure this is 771 * currently the case. 772 */ 773 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 774 ahc_outb(ahc, LASTPHASE, curphase); 775 ahc_outb(ahc, SCSISIGO, curphase); 776 } 777 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) { 778 int wait; 779 780 /* 781 * In a data phase. Faster to bitbucket 782 * the data than to individually ack each 783 * byte. This is also the only strategy 784 * that will work with AUTOACK enabled. 785 */ 786 ahc_outb(ahc, SXFRCTL1, 787 ahc_inb(ahc, SXFRCTL1) | BITBUCKET); 788 wait = 5000; 789 while (--wait != 0) { 790 if ((ahc_inb(ahc, SCSISIGI) 791 & (CDI|MSGI)) != 0) 792 break; 793 aic_delay(100); 794 } 795 ahc_outb(ahc, SXFRCTL1, 796 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 797 if (wait == 0) { 798 struct scb *scb; 799 u_int scb_index; 800 801 ahc_print_devinfo(ahc, &devinfo); 802 printf("Unable to clear parity error. " 803 "Resetting bus.\n"); 804 scb_index = ahc_inb(ahc, SCB_TAG); 805 scb = ahc_lookup_scb(ahc, scb_index); 806 if (scb != NULL) 807 aic_set_transaction_status(scb, 808 CAM_UNCOR_PARITY); 809 ahc_reset_channel(ahc, devinfo.channel, 810 /*init reset*/TRUE); 811 } 812 } else { 813 ahc_inb(ahc, SCSIDATL); 814 } 815 } 816 break; 817 } 818 case DATA_OVERRUN: 819 { 820 /* 821 * When the sequencer detects an overrun, it 822 * places the controller in "BITBUCKET" mode 823 * and allows the target to complete its transfer. 824 * Unfortunately, none of the counters get updated 825 * when the controller is in this mode, so we have 826 * no way of knowing how large the overrun was. 827 */ 828 u_int scbindex = ahc_inb(ahc, SCB_TAG); 829 u_int lastphase = ahc_inb(ahc, LASTPHASE); 830 u_int i; 831 832 scb = ahc_lookup_scb(ahc, scbindex); 833 for (i = 0; i < num_phases; i++) { 834 if (lastphase == ahc_phase_table[i].phase) 835 break; 836 } 837 ahc_print_path(ahc, scb); 838 printf("data overrun detected %s." 839 " Tag == 0x%x.\n", 840 ahc_phase_table[i].phasemsg, 841 scb->hscb->tag); 842 ahc_print_path(ahc, scb); 843 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n", 844 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 845 aic_get_transfer_length(scb), scb->sg_count); 846 if (scb->sg_count > 0) { 847 for (i = 0; i < scb->sg_count; i++) { 848 849 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 850 i, 851 (aic_le32toh(scb->sg_list[i].len) >> 24 852 & SG_HIGH_ADDR_BITS), 853 aic_le32toh(scb->sg_list[i].addr), 854 aic_le32toh(scb->sg_list[i].len) 855 & AHC_SG_LEN_MASK); 856 } 857 } 858 /* 859 * Set this and it will take effect when the 860 * target does a command complete. 861 */ 862 ahc_freeze_devq(ahc, scb); 863 if ((scb->flags & SCB_SENSE) == 0) { 864 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR); 865 } else { 866 scb->flags &= ~SCB_SENSE; 867 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 868 } 869 aic_freeze_scb(scb); 870 871 if ((ahc->features & AHC_ULTRA2) != 0) { 872 /* 873 * Clear the channel in case we return 874 * to data phase later. 875 */ 876 ahc_outb(ahc, SXFRCTL0, 877 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 878 ahc_outb(ahc, SXFRCTL0, 879 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 880 } 881 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 882 u_int dscommand1; 883 884 /* Ensure HHADDR is 0 for future DMA operations. */ 885 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 886 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 887 ahc_outb(ahc, HADDR, 0); 888 ahc_outb(ahc, DSCOMMAND1, dscommand1); 889 } 890 break; 891 } 892 case MKMSG_FAILED: 893 { 894 u_int scbindex; 895 896 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 897 ahc_name(ahc), devinfo.channel, devinfo.target, 898 devinfo.lun); 899 scbindex = ahc_inb(ahc, SCB_TAG); 900 scb = ahc_lookup_scb(ahc, scbindex); 901 if (scb != NULL 902 && (scb->flags & SCB_RECOVERY_SCB) != 0) 903 /* 904 * Ensure that we didn't put a second instance of this 905 * SCB into the QINFIFO. 906 */ 907 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 908 SCB_GET_CHANNEL(ahc, scb), 909 SCB_GET_LUN(scb), scb->hscb->tag, 910 ROLE_INITIATOR, /*status*/0, 911 SEARCH_REMOVE); 912 break; 913 } 914 case NO_FREE_SCB: 915 { 916 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc)); 917 ahc_dump_card_state(ahc); 918 panic("for safety"); 919 break; 920 } 921 case SCB_MISMATCH: 922 { 923 u_int scbptr; 924 925 scbptr = ahc_inb(ahc, SCBPTR); 926 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n", 927 scbptr, ahc_inb(ahc, ARG_1), 928 ahc->scb_data->hscbs[scbptr].tag); 929 ahc_dump_card_state(ahc); 930 panic("for safety"); 931 break; 932 } 933 case OUT_OF_RANGE: 934 { 935 printf("%s: BTT calculation out of range\n", ahc_name(ahc)); 936 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 937 "ARG_1 == 0x%x ACCUM = 0x%x\n", 938 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 939 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 940 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 941 "SINDEX == 0x%x\n, A == 0x%x\n", 942 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 943 ahc_index_busy_tcl(ahc, 944 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 945 ahc_inb(ahc, SAVED_LUN))), 946 ahc_inb(ahc, SINDEX), 947 ahc_inb(ahc, ACCUM)); 948 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 949 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 950 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 951 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 952 ahc_inb(ahc, SCB_CONTROL)); 953 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 954 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 955 ahc_dump_card_state(ahc); 956 panic("for safety"); 957 break; 958 } 959 default: 960 printf("ahc_intr: seqint, " 961 "intstat == 0x%x, scsisigi = 0x%x\n", 962 intstat, ahc_inb(ahc, SCSISIGI)); 963 break; 964 } 965unpause: 966 /* 967 * The sequencer is paused immediately on 968 * a SEQINT, so we should restart it when 969 * we're done. 970 */ 971 ahc_unpause(ahc); 972} 973 974void 975ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 976{ 977 u_int scb_index; 978 u_int status0; 979 u_int status; 980 struct scb *scb; 981 char cur_channel; 982 char intr_channel; 983 984 if ((ahc->features & AHC_TWIN) != 0 985 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 986 cur_channel = 'B'; 987 else 988 cur_channel = 'A'; 989 intr_channel = cur_channel; 990 991 if ((ahc->features & AHC_ULTRA2) != 0) 992 status0 = ahc_inb(ahc, SSTAT0) & IOERR; 993 else 994 status0 = 0; 995 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 996 if (status == 0 && status0 == 0) { 997 if ((ahc->features & AHC_TWIN) != 0) { 998 /* Try the other channel */ 999 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 1000 status = ahc_inb(ahc, SSTAT1) 1001 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 1002 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 1003 } 1004 if (status == 0) { 1005 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 1006 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1007 ahc_unpause(ahc); 1008 return; 1009 } 1010 } 1011 1012 /* Make sure the sequencer is in a safe location. */ 1013 ahc_clear_critical_section(ahc); 1014 1015 scb_index = ahc_inb(ahc, SCB_TAG); 1016 scb = ahc_lookup_scb(ahc, scb_index); 1017 if (scb != NULL 1018 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1019 scb = NULL; 1020 1021 if ((ahc->features & AHC_ULTRA2) != 0 1022 && (status0 & IOERR) != 0) { 1023 int now_lvd; 1024 1025 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40; 1026 printf("%s: Transceiver State Has Changed to %s mode\n", 1027 ahc_name(ahc), now_lvd ? "LVD" : "SE"); 1028 ahc_outb(ahc, CLRSINT0, CLRIOERR); 1029 /* 1030 * When transitioning to SE mode, the reset line 1031 * glitches, triggering an arbitration bug in some 1032 * Ultra2 controllers. This bug is cleared when we 1033 * assert the reset line. Since a reset glitch has 1034 * already occurred with this transition and a 1035 * transceiver state change is handled just like 1036 * a bus reset anyway, asserting the reset line 1037 * ourselves is safe. 1038 */ 1039 ahc_reset_channel(ahc, intr_channel, 1040 /*Initiate Reset*/now_lvd == 0); 1041 } else if ((status & SCSIRSTI) != 0) { 1042 printf("%s: Someone reset channel %c\n", 1043 ahc_name(ahc), intr_channel); 1044 if (intr_channel != cur_channel) 1045 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 1046 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE); 1047 } else if ((status & SCSIPERR) != 0) { 1048 /* 1049 * Determine the bus phase and queue an appropriate message. 1050 * SCSIPERR is latched true as soon as a parity error 1051 * occurs. If the sequencer acked the transfer that 1052 * caused the parity error and the currently presented 1053 * transfer on the bus has correct parity, SCSIPERR will 1054 * be cleared by CLRSCSIPERR. Use this to determine if 1055 * we should look at the last phase the sequencer recorded, 1056 * or the current phase presented on the bus. 1057 */ 1058 struct ahc_devinfo devinfo; 1059 u_int mesg_out; 1060 u_int curphase; 1061 u_int errorphase; 1062 u_int lastphase; 1063 u_int scsirate; 1064 u_int i; 1065 u_int sstat2; 1066 int silent; 1067 1068 lastphase = ahc_inb(ahc, LASTPHASE); 1069 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1070 sstat2 = ahc_inb(ahc, SSTAT2); 1071 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 1072 /* 1073 * For all phases save DATA, the sequencer won't 1074 * automatically ack a byte that has a parity error 1075 * in it. So the only way that the current phase 1076 * could be 'data-in' is if the parity error is for 1077 * an already acked byte in the data phase. During 1078 * synchronous data-in transfers, we may actually 1079 * ack bytes before latching the current phase in 1080 * LASTPHASE, leading to the discrepancy between 1081 * curphase and lastphase. 1082 */ 1083 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 1084 || curphase == P_DATAIN || curphase == P_DATAIN_DT) 1085 errorphase = curphase; 1086 else 1087 errorphase = lastphase; 1088 1089 for (i = 0; i < num_phases; i++) { 1090 if (errorphase == ahc_phase_table[i].phase) 1091 break; 1092 } 1093 mesg_out = ahc_phase_table[i].mesg_out; 1094 silent = FALSE; 1095 if (scb != NULL) { 1096 if (SCB_IS_SILENT(scb)) 1097 silent = TRUE; 1098 else 1099 ahc_print_path(ahc, scb); 1100 scb->flags |= SCB_TRANSMISSION_ERROR; 1101 } else 1102 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel, 1103 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID))); 1104 scsirate = ahc_inb(ahc, SCSIRATE); 1105 if (silent == FALSE) { 1106 printf("parity error detected %s. " 1107 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 1108 ahc_phase_table[i].phasemsg, 1109 ahc_inw(ahc, SEQADDR0), 1110 scsirate); 1111 if ((ahc->features & AHC_DT) != 0) { 1112 if ((sstat2 & CRCVALERR) != 0) 1113 printf("\tCRC Value Mismatch\n"); 1114 if ((sstat2 & CRCENDERR) != 0) 1115 printf("\tNo terminal CRC packet " 1116 "recevied\n"); 1117 if ((sstat2 & CRCREQERR) != 0) 1118 printf("\tIllegal CRC packet " 1119 "request\n"); 1120 if ((sstat2 & DUAL_EDGE_ERR) != 0) 1121 printf("\tUnexpected %sDT Data Phase\n", 1122 (scsirate & SINGLE_EDGE) 1123 ? "" : "non-"); 1124 } 1125 } 1126 1127 if ((ahc->features & AHC_DT) != 0 1128 && (sstat2 & DUAL_EDGE_ERR) != 0) { 1129 /* 1130 * This error applies regardless of 1131 * data direction, so ignore the value 1132 * in the phase table. 1133 */ 1134 mesg_out = MSG_INITIATOR_DET_ERR; 1135 } 1136 1137 /* 1138 * We've set the hardware to assert ATN if we 1139 * get a parity error on "in" phases, so all we 1140 * need to do is stuff the message buffer with 1141 * the appropriate message. "In" phases have set 1142 * mesg_out to something other than MSG_NOP. 1143 */ 1144 if (mesg_out != MSG_NOOP) { 1145 if (ahc->msg_type != MSG_TYPE_NONE) 1146 ahc->send_msg_perror = TRUE; 1147 else 1148 ahc_outb(ahc, MSG_OUT, mesg_out); 1149 } 1150 /* 1151 * Force a renegotiation with this target just in 1152 * case we are out of sync for some external reason 1153 * unknown (or unreported) by the target. 1154 */ 1155 ahc_fetch_devinfo(ahc, &devinfo); 1156 ahc_force_renegotiation(ahc, &devinfo); 1157 1158 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1159 ahc_unpause(ahc); 1160 } else if ((status & SELTO) != 0) { 1161 u_int scbptr; 1162 1163 /* Stop the selection */ 1164 ahc_outb(ahc, SCSISEQ, 0); 1165 1166 /* No more pending messages */ 1167 ahc_clear_msg_state(ahc); 1168 1169 /* Clear interrupt state */ 1170 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1171 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1172 1173 /* 1174 * Although the driver does not care about the 1175 * 'Selection in Progress' status bit, the busy 1176 * LED does. SELINGO is only cleared by a successful 1177 * selection, so we must manually clear it to insure 1178 * the LED turns off just incase no future successful 1179 * selections occur (e.g. no devices on the bus). 1180 */ 1181 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 1182 1183 scbptr = ahc_inb(ahc, WAITING_SCBH); 1184 ahc_outb(ahc, SCBPTR, scbptr); 1185 scb_index = ahc_inb(ahc, SCB_TAG); 1186 1187 scb = ahc_lookup_scb(ahc, scb_index); 1188 if (scb == NULL) { 1189 printf("%s: ahc_intr - referenced scb not " 1190 "valid during SELTO scb(%d, %d)\n", 1191 ahc_name(ahc), scbptr, scb_index); 1192 ahc_dump_card_state(ahc); 1193 } else { 1194 struct ahc_devinfo devinfo; 1195#ifdef AHC_DEBUG 1196 if ((ahc_debug & AHC_SHOW_SELTO) != 0) { 1197 ahc_print_path(ahc, scb); 1198 printf("Saw Selection Timeout for SCB 0x%x\n", 1199 scb_index); 1200 } 1201#endif 1202 ahc_scb_devinfo(ahc, &devinfo, scb); 1203 aic_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1204 ahc_freeze_devq(ahc, scb); 1205 1206 /* 1207 * Cancel any pending transactions on the device 1208 * now that it seems to be missing. This will 1209 * also revert us to async/narrow transfers until 1210 * we can renegotiate with the device. 1211 */ 1212 ahc_handle_devreset(ahc, &devinfo, 1213 CAM_SEL_TIMEOUT, 1214 "Selection Timeout", 1215 /*verbose_level*/1); 1216 } 1217 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1218 ahc_restart(ahc); 1219 } else if ((status & BUSFREE) != 0 1220 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 1221 struct ahc_devinfo devinfo; 1222 u_int lastphase; 1223 u_int saved_scsiid; 1224 u_int saved_lun; 1225 u_int target; 1226 u_int initiator_role_id; 1227 char channel; 1228 int printerror; 1229 1230 /* 1231 * Clear our selection hardware as soon as possible. 1232 * We may have an entry in the waiting Q for this target, 1233 * that is affected by this busfree and we don't want to 1234 * go about selecting the target while we handle the event. 1235 */ 1236 ahc_outb(ahc, SCSISEQ, 1237 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1238 1239 /* 1240 * Disable busfree interrupts and clear the busfree 1241 * interrupt status. We do this here so that several 1242 * bus transactions occur prior to clearing the SCSIINT 1243 * latch. It can take a bit for the clearing to take effect. 1244 */ 1245 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1246 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 1247 1248 /* 1249 * Look at what phase we were last in. 1250 * If its message out, chances are pretty good 1251 * that the busfree was in response to one of 1252 * our abort requests. 1253 */ 1254 lastphase = ahc_inb(ahc, LASTPHASE); 1255 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 1256 saved_lun = ahc_inb(ahc, SAVED_LUN); 1257 target = SCSIID_TARGET(ahc, saved_scsiid); 1258 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 1259 channel = SCSIID_CHANNEL(ahc, saved_scsiid); 1260 ahc_compile_devinfo(&devinfo, initiator_role_id, 1261 target, saved_lun, channel, ROLE_INITIATOR); 1262 printerror = 1; 1263 1264 if (lastphase == P_MESGOUT) { 1265 u_int tag; 1266 1267 tag = SCB_LIST_NULL; 1268 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE) 1269 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) { 1270 if (ahc->msgout_buf[ahc->msgout_index - 1] 1271 == MSG_ABORT_TAG) 1272 tag = scb->hscb->tag; 1273 ahc_print_path(ahc, scb); 1274 printf("SCB %d - Abort%s Completed.\n", 1275 scb->hscb->tag, tag == SCB_LIST_NULL ? 1276 "" : " Tag"); 1277 ahc_abort_scbs(ahc, target, channel, 1278 saved_lun, tag, 1279 ROLE_INITIATOR, 1280 CAM_REQ_ABORTED); 1281 printerror = 0; 1282 } else if (ahc_sent_msg(ahc, AHCMSG_1B, 1283 MSG_BUS_DEV_RESET, TRUE)) { 1284#ifdef __FreeBSD__ 1285 /* 1286 * Don't mark the user's request for this BDR 1287 * as completing with CAM_BDR_SENT. CAM3 1288 * specifies CAM_REQ_CMP. 1289 */ 1290 if (scb != NULL 1291 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 1292 && ahc_match_scb(ahc, scb, target, channel, 1293 CAM_LUN_WILDCARD, 1294 SCB_LIST_NULL, 1295 ROLE_INITIATOR)) { 1296 aic_set_transaction_status(scb, CAM_REQ_CMP); 1297 } 1298#endif 1299 ahc_compile_devinfo(&devinfo, 1300 initiator_role_id, 1301 target, 1302 CAM_LUN_WILDCARD, 1303 channel, 1304 ROLE_INITIATOR); 1305 ahc_handle_devreset(ahc, &devinfo, 1306 CAM_BDR_SENT, 1307 "Bus Device Reset", 1308 /*verbose_level*/0); 1309 printerror = 0; 1310 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1311 MSG_EXT_PPR, FALSE)) { 1312 struct ahc_initiator_tinfo *tinfo; 1313 struct ahc_tmode_tstate *tstate; 1314 1315 /* 1316 * PPR Rejected. Try non-ppr negotiation 1317 * and retry command. 1318 */ 1319 tinfo = ahc_fetch_transinfo(ahc, 1320 devinfo.channel, 1321 devinfo.our_scsiid, 1322 devinfo.target, 1323 &tstate); 1324 tinfo->curr.transport_version = 2; 1325 tinfo->goal.transport_version = 2; 1326 tinfo->goal.ppr_options = 0; 1327 ahc_qinfifo_requeue_tail(ahc, scb); 1328 printerror = 0; 1329 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1330 MSG_EXT_WDTR, FALSE)) { 1331 /* 1332 * Negotiation Rejected. Go-narrow and 1333 * retry command. 1334 */ 1335 ahc_set_width(ahc, &devinfo, 1336 MSG_EXT_WDTR_BUS_8_BIT, 1337 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1338 /*paused*/TRUE); 1339 ahc_qinfifo_requeue_tail(ahc, scb); 1340 printerror = 0; 1341 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1342 MSG_EXT_SDTR, FALSE)) { 1343 /* 1344 * Negotiation Rejected. Go-async and 1345 * retry command. 1346 */ 1347 ahc_set_syncrate(ahc, &devinfo, 1348 /*syncrate*/NULL, 1349 /*period*/0, /*offset*/0, 1350 /*ppr_options*/0, 1351 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1352 /*paused*/TRUE); 1353 ahc_qinfifo_requeue_tail(ahc, scb); 1354 printerror = 0; 1355 } 1356 } 1357 if (printerror != 0) { 1358 u_int i; 1359 1360 if (scb != NULL) { 1361 u_int tag; 1362 1363 if ((scb->hscb->control & TAG_ENB) != 0) 1364 tag = scb->hscb->tag; 1365 else 1366 tag = SCB_LIST_NULL; 1367 ahc_print_path(ahc, scb); 1368 ahc_abort_scbs(ahc, target, channel, 1369 SCB_GET_LUN(scb), tag, 1370 ROLE_INITIATOR, 1371 CAM_UNEXP_BUSFREE); 1372 } else { 1373 /* 1374 * We had not fully identified this connection, 1375 * so we cannot abort anything. 1376 */ 1377 printf("%s: ", ahc_name(ahc)); 1378 } 1379 for (i = 0; i < num_phases; i++) { 1380 if (lastphase == ahc_phase_table[i].phase) 1381 break; 1382 } 1383 if (lastphase != P_BUSFREE) { 1384 /* 1385 * Renegotiate with this device at the 1386 * next opportunity just in case this busfree 1387 * is due to a negotiation mismatch with the 1388 * device. 1389 */ 1390 ahc_force_renegotiation(ahc, &devinfo); 1391 } 1392 printf("Unexpected busfree %s\n" 1393 "SEQADDR == 0x%x\n", 1394 ahc_phase_table[i].phasemsg, 1395 ahc_inb(ahc, SEQADDR0) 1396 | (ahc_inb(ahc, SEQADDR1) << 8)); 1397 } 1398 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1399 ahc_restart(ahc); 1400 } else { 1401 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n", 1402 ahc_name(ahc), status); 1403 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1404 } 1405} 1406 1407/* 1408 * Force renegotiation to occur the next time we initiate 1409 * a command to the current device. 1410 */ 1411static void 1412ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1413{ 1414 struct ahc_initiator_tinfo *targ_info; 1415 struct ahc_tmode_tstate *tstate; 1416 1417 targ_info = ahc_fetch_transinfo(ahc, 1418 devinfo->channel, 1419 devinfo->our_scsiid, 1420 devinfo->target, 1421 &tstate); 1422 ahc_update_neg_request(ahc, devinfo, tstate, 1423 targ_info, AHC_NEG_IF_NON_ASYNC); 1424} 1425 1426#define AHC_MAX_STEPS 2000 1427void 1428ahc_clear_critical_section(struct ahc_softc *ahc) 1429{ 1430 int stepping; 1431 int steps; 1432 u_int simode0; 1433 u_int simode1; 1434 1435 if (ahc->num_critical_sections == 0) 1436 return; 1437 1438 stepping = FALSE; 1439 steps = 0; 1440 simode0 = 0; 1441 simode1 = 0; 1442 for (;;) { 1443 struct cs *cs; 1444 u_int seqaddr; 1445 u_int i; 1446 1447 seqaddr = ahc_inb(ahc, SEQADDR0) 1448 | (ahc_inb(ahc, SEQADDR1) << 8); 1449 1450 /* 1451 * Seqaddr represents the next instruction to execute, 1452 * so we are really executing the instruction just 1453 * before it. 1454 */ 1455 cs = ahc->critical_sections; 1456 for (i = 0; i < ahc->num_critical_sections; i++, cs++) { 1457 1458 if (cs->begin < seqaddr && cs->end >= seqaddr) 1459 break; 1460 } 1461 1462 if (i == ahc->num_critical_sections) 1463 break; 1464 1465 if (steps > AHC_MAX_STEPS) { 1466 printf("%s: Infinite loop in critical section\n", 1467 ahc_name(ahc)); 1468 ahc_dump_card_state(ahc); 1469 panic("critical section loop"); 1470 } 1471 1472 steps++; 1473 if (stepping == FALSE) { 1474 1475 /* 1476 * Disable all interrupt sources so that the 1477 * sequencer will not be stuck by a pausing 1478 * interrupt condition while we attempt to 1479 * leave a critical section. 1480 */ 1481 simode0 = ahc_inb(ahc, SIMODE0); 1482 ahc_outb(ahc, SIMODE0, 0); 1483 simode1 = ahc_inb(ahc, SIMODE1); 1484 if ((ahc->features & AHC_DT) != 0) 1485 /* 1486 * On DT class controllers, we 1487 * use the enhanced busfree logic. 1488 * Unfortunately we cannot re-enable 1489 * busfree detection within the 1490 * current connection, so we must 1491 * leave it on while single stepping. 1492 */ 1493 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE); 1494 else 1495 ahc_outb(ahc, SIMODE1, 0); 1496 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1497 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP); 1498 stepping = TRUE; 1499 } 1500 if ((ahc->features & AHC_DT) != 0) { 1501 ahc_outb(ahc, CLRSINT1, CLRBUSFREE); 1502 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1503 } 1504 ahc_outb(ahc, HCNTRL, ahc->unpause); 1505 while (!ahc_is_paused(ahc)) 1506 aic_delay(200); 1507 } 1508 if (stepping) { 1509 ahc_outb(ahc, SIMODE0, simode0); 1510 ahc_outb(ahc, SIMODE1, simode1); 1511 ahc_outb(ahc, SEQCTL, ahc->seqctl); 1512 } 1513} 1514 1515/* 1516 * Clear any pending interrupt status. 1517 */ 1518void 1519ahc_clear_intstat(struct ahc_softc *ahc) 1520{ 1521 /* Clear any interrupt conditions this may have caused */ 1522 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 1523 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 1524 CLRREQINIT); 1525 ahc_flush_device_writes(ahc); 1526 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 1527 ahc_flush_device_writes(ahc); 1528 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1529 ahc_flush_device_writes(ahc); 1530} 1531 1532/**************************** Debugging Routines ******************************/ 1533#ifdef AHC_DEBUG 1534uint32_t ahc_debug = AHC_DEBUG_OPTS; 1535#endif 1536 1537void 1538ahc_print_scb(struct scb *scb) 1539{ 1540 int i; 1541 1542 struct hardware_scb *hscb = scb->hscb; 1543 1544 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 1545 (void *)scb, 1546 hscb->control, 1547 hscb->scsiid, 1548 hscb->lun, 1549 hscb->cdb_len); 1550 printf("Shared Data: "); 1551 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++) 1552 printf("%#02x", hscb->shared_data.cdb[i]); 1553 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n", 1554 aic_le32toh(hscb->dataptr), 1555 aic_le32toh(hscb->datacnt), 1556 aic_le32toh(hscb->sgptr), 1557 hscb->tag); 1558 if (scb->sg_count > 0) { 1559 for (i = 0; i < scb->sg_count; i++) { 1560 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 1561 i, 1562 (aic_le32toh(scb->sg_list[i].len) >> 24 1563 & SG_HIGH_ADDR_BITS), 1564 aic_le32toh(scb->sg_list[i].addr), 1565 aic_le32toh(scb->sg_list[i].len)); 1566 } 1567 } 1568} 1569 1570/************************* Transfer Negotiation *******************************/ 1571/* 1572 * Allocate per target mode instance (ID we respond to as a target) 1573 * transfer negotiation data structures. 1574 */ 1575static struct ahc_tmode_tstate * 1576ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1577{ 1578 struct ahc_tmode_tstate *master_tstate; 1579 struct ahc_tmode_tstate *tstate; 1580 int i; 1581 1582 master_tstate = ahc->enabled_targets[ahc->our_id]; 1583 if (channel == 'B') { 1584 scsi_id += 8; 1585 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1586 } 1587 if (ahc->enabled_targets[scsi_id] != NULL 1588 && ahc->enabled_targets[scsi_id] != master_tstate) 1589 panic("%s: ahc_alloc_tstate - Target already allocated", 1590 ahc_name(ahc)); 1591 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate), 1592 M_DEVBUF, M_NOWAIT); 1593 if (tstate == NULL) 1594 return (NULL); 1595 1596 /* 1597 * If we have allocated a master tstate, copy user settings from 1598 * the master tstate (taken from SRAM or the EEPROM) for this 1599 * channel, but reset our current and goal settings to async/narrow 1600 * until an initiator talks to us. 1601 */ 1602 if (master_tstate != NULL) { 1603 memcpy(tstate, master_tstate, sizeof(*tstate)); 1604 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 1605 tstate->ultraenb = 0; 1606 for (i = 0; i < AHC_NUM_TARGETS; i++) { 1607 memset(&tstate->transinfo[i].curr, 0, 1608 sizeof(tstate->transinfo[i].curr)); 1609 memset(&tstate->transinfo[i].goal, 0, 1610 sizeof(tstate->transinfo[i].goal)); 1611 } 1612 } else 1613 memset(tstate, 0, sizeof(*tstate)); 1614 ahc->enabled_targets[scsi_id] = tstate; 1615 return (tstate); 1616} 1617 1618#ifdef AHC_TARGET_MODE 1619/* 1620 * Free per target mode instance (ID we respond to as a target) 1621 * transfer negotiation data structures. 1622 */ 1623static void 1624ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1625{ 1626 struct ahc_tmode_tstate *tstate; 1627 1628 /* 1629 * Don't clean up our "master" tstate. 1630 * It has our default user settings. 1631 */ 1632 if (((channel == 'B' && scsi_id == ahc->our_id_b) 1633 || (channel == 'A' && scsi_id == ahc->our_id)) 1634 && force == FALSE) 1635 return; 1636 1637 if (channel == 'B') 1638 scsi_id += 8; 1639 tstate = ahc->enabled_targets[scsi_id]; 1640 if (tstate != NULL) 1641 free(tstate, M_DEVBUF); 1642 ahc->enabled_targets[scsi_id] = NULL; 1643} 1644#endif 1645 1646/* 1647 * Called when we have an active connection to a target on the bus, 1648 * this function finds the nearest syncrate to the input period limited 1649 * by the capabilities of the bus connectivity of and sync settings for 1650 * the target. 1651 */ 1652struct ahc_syncrate * 1653ahc_devlimited_syncrate(struct ahc_softc *ahc, 1654 struct ahc_initiator_tinfo *tinfo, 1655 u_int *period, u_int *ppr_options, role_t role) 1656{ 1657 struct ahc_transinfo *transinfo; 1658 u_int maxsync; 1659 1660 if ((ahc->features & AHC_ULTRA2) != 0) { 1661 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1662 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1663 maxsync = AHC_SYNCRATE_DT; 1664 } else { 1665 maxsync = AHC_SYNCRATE_ULTRA; 1666 /* Can't do DT on an SE bus */ 1667 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1668 } 1669 } else if ((ahc->features & AHC_ULTRA) != 0) { 1670 maxsync = AHC_SYNCRATE_ULTRA; 1671 } else { 1672 maxsync = AHC_SYNCRATE_FAST; 1673 } 1674 /* 1675 * Never allow a value higher than our current goal 1676 * period otherwise we may allow a target initiated 1677 * negotiation to go above the limit as set by the 1678 * user. In the case of an initiator initiated 1679 * sync negotiation, we limit based on the user 1680 * setting. This allows the system to still accept 1681 * incoming negotiations even if target initiated 1682 * negotiation is not performed. 1683 */ 1684 if (role == ROLE_TARGET) 1685 transinfo = &tinfo->user; 1686 else 1687 transinfo = &tinfo->goal; 1688 *ppr_options &= transinfo->ppr_options; 1689 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 1690 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2); 1691 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1692 } 1693 if (transinfo->period == 0) { 1694 *period = 0; 1695 *ppr_options = 0; 1696 return (NULL); 1697 } 1698 *period = MAX(*period, transinfo->period); 1699 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync)); 1700} 1701 1702/* 1703 * Look up the valid period to SCSIRATE conversion in our table. 1704 * Return the period and offset that should be sent to the target 1705 * if this was the beginning of an SDTR. 1706 */ 1707struct ahc_syncrate * 1708ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1709 u_int *ppr_options, u_int maxsync) 1710{ 1711 struct ahc_syncrate *syncrate; 1712 1713 if ((ahc->features & AHC_DT) == 0) 1714 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1715 1716 /* Skip all DT only entries if DT is not available */ 1717 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 1718 && maxsync < AHC_SYNCRATE_ULTRA2) 1719 maxsync = AHC_SYNCRATE_ULTRA2; 1720 1721 for (syncrate = &ahc_syncrates[maxsync]; 1722 syncrate->rate != NULL; 1723 syncrate++) { 1724 1725 /* 1726 * The Ultra2 table doesn't go as low 1727 * as for the Fast/Ultra cards. 1728 */ 1729 if ((ahc->features & AHC_ULTRA2) != 0 1730 && (syncrate->sxfr_u2 == 0)) 1731 break; 1732 1733 if (*period <= syncrate->period) { 1734 /* 1735 * When responding to a target that requests 1736 * sync, the requested rate may fall between 1737 * two rates that we can output, but still be 1738 * a rate that we can receive. Because of this, 1739 * we want to respond to the target with 1740 * the same rate that it sent to us even 1741 * if the period we use to send data to it 1742 * is lower. Only lower the response period 1743 * if we must. 1744 */ 1745 if (syncrate == &ahc_syncrates[maxsync]) 1746 *period = syncrate->period; 1747 1748 /* 1749 * At some speeds, we only support 1750 * ST transfers. 1751 */ 1752 if ((syncrate->sxfr_u2 & ST_SXFR) != 0) 1753 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1754 break; 1755 } 1756 } 1757 1758 if ((*period == 0) 1759 || (syncrate->rate == NULL) 1760 || ((ahc->features & AHC_ULTRA2) != 0 1761 && (syncrate->sxfr_u2 == 0))) { 1762 /* Use asynchronous transfers. */ 1763 *period = 0; 1764 syncrate = NULL; 1765 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1766 } 1767 return (syncrate); 1768} 1769 1770/* 1771 * Convert from an entry in our syncrate table to the SCSI equivalent 1772 * sync "period" factor. 1773 */ 1774u_int 1775ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1776{ 1777 struct ahc_syncrate *syncrate; 1778 1779 if ((ahc->features & AHC_ULTRA2) != 0) 1780 scsirate &= SXFR_ULTRA2; 1781 else 1782 scsirate &= SXFR; 1783 1784 syncrate = &ahc_syncrates[maxsync]; 1785 while (syncrate->rate != NULL) { 1786 1787 if ((ahc->features & AHC_ULTRA2) != 0) { 1788 if (syncrate->sxfr_u2 == 0) 1789 break; 1790 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1791 return (syncrate->period); 1792 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1793 return (syncrate->period); 1794 } 1795 syncrate++; 1796 } 1797 return (0); /* async */ 1798} 1799 1800/* 1801 * Truncate the given synchronous offset to a value the 1802 * current adapter type and syncrate are capable of. 1803 */ 1804void 1805ahc_validate_offset(struct ahc_softc *ahc, 1806 struct ahc_initiator_tinfo *tinfo, 1807 struct ahc_syncrate *syncrate, 1808 u_int *offset, int wide, role_t role) 1809{ 1810 u_int maxoffset; 1811 1812 /* Limit offset to what we can do */ 1813 if (syncrate == NULL) { 1814 maxoffset = 0; 1815 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1816 maxoffset = MAX_OFFSET_ULTRA2; 1817 } else { 1818 if (wide) 1819 maxoffset = MAX_OFFSET_16BIT; 1820 else 1821 maxoffset = MAX_OFFSET_8BIT; 1822 } 1823 *offset = MIN(*offset, maxoffset); 1824 if (tinfo != NULL) { 1825 if (role == ROLE_TARGET) 1826 *offset = MIN(*offset, tinfo->user.offset); 1827 else 1828 *offset = MIN(*offset, tinfo->goal.offset); 1829 } 1830} 1831 1832/* 1833 * Truncate the given transfer width parameter to a value the 1834 * current adapter type is capable of. 1835 */ 1836void 1837ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo, 1838 u_int *bus_width, role_t role) 1839{ 1840 switch (*bus_width) { 1841 default: 1842 if (ahc->features & AHC_WIDE) { 1843 /* Respond Wide */ 1844 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 1845 break; 1846 } 1847 /* FALLTHROUGH */ 1848 case MSG_EXT_WDTR_BUS_8_BIT: 1849 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 1850 break; 1851 } 1852 if (tinfo != NULL) { 1853 if (role == ROLE_TARGET) 1854 *bus_width = MIN(tinfo->user.width, *bus_width); 1855 else 1856 *bus_width = MIN(tinfo->goal.width, *bus_width); 1857 } 1858} 1859 1860/* 1861 * Update the bitmask of targets for which the controller should 1862 * negotiate with at the next convenient opportunity. This currently 1863 * means the next time we send the initial identify messages for 1864 * a new transaction. 1865 */ 1866int 1867ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1868 struct ahc_tmode_tstate *tstate, 1869 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type) 1870{ 1871 u_int auto_negotiate_orig; 1872 1873 auto_negotiate_orig = tstate->auto_negotiate; 1874 if (neg_type == AHC_NEG_ALWAYS) { 1875 /* 1876 * Force our "current" settings to be 1877 * unknown so that unless a bus reset 1878 * occurs the need to renegotiate is 1879 * recorded persistently. 1880 */ 1881 if ((ahc->features & AHC_WIDE) != 0) 1882 tinfo->curr.width = AHC_WIDTH_UNKNOWN; 1883 tinfo->curr.period = AHC_PERIOD_UNKNOWN; 1884 tinfo->curr.offset = AHC_OFFSET_UNKNOWN; 1885 } 1886 if (tinfo->curr.period != tinfo->goal.period 1887 || tinfo->curr.width != tinfo->goal.width 1888 || tinfo->curr.offset != tinfo->goal.offset 1889 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 1890 || (neg_type == AHC_NEG_IF_NON_ASYNC 1891 && (tinfo->goal.offset != 0 1892 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 1893 || tinfo->goal.ppr_options != 0))) 1894 tstate->auto_negotiate |= devinfo->target_mask; 1895 else 1896 tstate->auto_negotiate &= ~devinfo->target_mask; 1897 1898 return (auto_negotiate_orig != tstate->auto_negotiate); 1899} 1900 1901/* 1902 * Update the user/goal/curr tables of synchronous negotiation 1903 * parameters as well as, in the case of a current or active update, 1904 * any data structures on the host controller. In the case of an 1905 * active update, the specified target is currently talking to us on 1906 * the bus, so the transfer parameter update must take effect 1907 * immediately. 1908 */ 1909void 1910ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1911 struct ahc_syncrate *syncrate, u_int period, 1912 u_int offset, u_int ppr_options, u_int type, int paused) 1913{ 1914 struct ahc_initiator_tinfo *tinfo; 1915 struct ahc_tmode_tstate *tstate; 1916 u_int old_period; 1917 u_int old_offset; 1918 u_int old_ppr; 1919 int active; 1920 int update_needed; 1921 1922 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1923 update_needed = 0; 1924 1925 if (syncrate == NULL) { 1926 period = 0; 1927 offset = 0; 1928 } 1929 1930 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1931 devinfo->target, &tstate); 1932 1933 if ((type & AHC_TRANS_USER) != 0) { 1934 tinfo->user.period = period; 1935 tinfo->user.offset = offset; 1936 tinfo->user.ppr_options = ppr_options; 1937 } 1938 1939 if ((type & AHC_TRANS_GOAL) != 0) { 1940 tinfo->goal.period = period; 1941 tinfo->goal.offset = offset; 1942 tinfo->goal.ppr_options = ppr_options; 1943 } 1944 1945 old_period = tinfo->curr.period; 1946 old_offset = tinfo->curr.offset; 1947 old_ppr = tinfo->curr.ppr_options; 1948 1949 if ((type & AHC_TRANS_CUR) != 0 1950 && (old_period != period 1951 || old_offset != offset 1952 || old_ppr != ppr_options)) { 1953 u_int scsirate; 1954 1955 update_needed++; 1956 scsirate = tinfo->scsirate; 1957 if ((ahc->features & AHC_ULTRA2) != 0) { 1958 1959 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1960 if (syncrate != NULL) { 1961 scsirate |= syncrate->sxfr_u2; 1962 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) 1963 scsirate |= ENABLE_CRC; 1964 else 1965 scsirate |= SINGLE_EDGE; 1966 } 1967 } else { 1968 1969 scsirate &= ~(SXFR|SOFS); 1970 /* 1971 * Ensure Ultra mode is set properly for 1972 * this target. 1973 */ 1974 tstate->ultraenb &= ~devinfo->target_mask; 1975 if (syncrate != NULL) { 1976 if (syncrate->sxfr & ULTRA_SXFR) { 1977 tstate->ultraenb |= 1978 devinfo->target_mask; 1979 } 1980 scsirate |= syncrate->sxfr & SXFR; 1981 scsirate |= offset & SOFS; 1982 } 1983 if (active) { 1984 u_int sxfrctl0; 1985 1986 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1987 sxfrctl0 &= ~FAST20; 1988 if (tstate->ultraenb & devinfo->target_mask) 1989 sxfrctl0 |= FAST20; 1990 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1991 } 1992 } 1993 if (active) { 1994 ahc_outb(ahc, SCSIRATE, scsirate); 1995 if ((ahc->features & AHC_ULTRA2) != 0) 1996 ahc_outb(ahc, SCSIOFFSET, offset); 1997 } 1998 1999 tinfo->scsirate = scsirate; 2000 tinfo->curr.period = period; 2001 tinfo->curr.offset = offset; 2002 tinfo->curr.ppr_options = ppr_options; 2003 2004 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2005 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2006 if (bootverbose) { 2007 if (offset != 0) { 2008 printf("%s: target %d synchronous at %sMHz%s, " 2009 "offset = 0x%x\n", ahc_name(ahc), 2010 devinfo->target, syncrate->rate, 2011 (ppr_options & MSG_EXT_PPR_DT_REQ) 2012 ? " DT" : "", offset); 2013 } else { 2014 printf("%s: target %d using " 2015 "asynchronous transfers\n", 2016 ahc_name(ahc), devinfo->target); 2017 } 2018 } 2019 } 2020 2021 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2022 tinfo, AHC_NEG_TO_GOAL); 2023 2024 if (update_needed) 2025 ahc_update_pending_scbs(ahc); 2026} 2027 2028/* 2029 * Update the user/goal/curr tables of wide negotiation 2030 * parameters as well as, in the case of a current or active update, 2031 * any data structures on the host controller. In the case of an 2032 * active update, the specified target is currently talking to us on 2033 * the bus, so the transfer parameter update must take effect 2034 * immediately. 2035 */ 2036void 2037ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2038 u_int width, u_int type, int paused) 2039{ 2040 struct ahc_initiator_tinfo *tinfo; 2041 struct ahc_tmode_tstate *tstate; 2042 u_int oldwidth; 2043 int active; 2044 int update_needed; 2045 2046 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 2047 update_needed = 0; 2048 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2049 devinfo->target, &tstate); 2050 2051 if ((type & AHC_TRANS_USER) != 0) 2052 tinfo->user.width = width; 2053 2054 if ((type & AHC_TRANS_GOAL) != 0) 2055 tinfo->goal.width = width; 2056 2057 oldwidth = tinfo->curr.width; 2058 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 2059 u_int scsirate; 2060 2061 update_needed++; 2062 scsirate = tinfo->scsirate; 2063 scsirate &= ~WIDEXFER; 2064 if (width == MSG_EXT_WDTR_BUS_16_BIT) 2065 scsirate |= WIDEXFER; 2066 2067 tinfo->scsirate = scsirate; 2068 2069 if (active) 2070 ahc_outb(ahc, SCSIRATE, scsirate); 2071 2072 tinfo->curr.width = width; 2073 2074 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2075 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2076 if (bootverbose) { 2077 printf("%s: target %d using %dbit transfers\n", 2078 ahc_name(ahc), devinfo->target, 2079 8 * (0x01 << width)); 2080 } 2081 } 2082 2083 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2084 tinfo, AHC_NEG_TO_GOAL); 2085 if (update_needed) 2086 ahc_update_pending_scbs(ahc); 2087} 2088 2089/* 2090 * Update the current state of tagged queuing for a given target. 2091 */ 2092void 2093ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2094 ahc_queue_alg alg) 2095{ 2096 ahc_platform_set_tags(ahc, devinfo, alg); 2097 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2098 devinfo->lun, AC_TRANSFER_NEG, &alg); 2099} 2100 2101/* 2102 * When the transfer settings for a connection change, update any 2103 * in-transit SCBs to contain the new data so the hardware will 2104 * be set correctly during future (re)selections. 2105 */ 2106static void 2107ahc_update_pending_scbs(struct ahc_softc *ahc) 2108{ 2109 struct scb *pending_scb; 2110 int pending_scb_count; 2111 int i; 2112 int paused; 2113 u_int saved_scbptr; 2114 2115 /* 2116 * Traverse the pending SCB list and ensure that all of the 2117 * SCBs there have the proper settings. 2118 */ 2119 pending_scb_count = 0; 2120 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) { 2121 struct ahc_devinfo devinfo; 2122 struct hardware_scb *pending_hscb; 2123 struct ahc_initiator_tinfo *tinfo; 2124 struct ahc_tmode_tstate *tstate; 2125 2126 ahc_scb_devinfo(ahc, &devinfo, pending_scb); 2127 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 2128 devinfo.our_scsiid, 2129 devinfo.target, &tstate); 2130 pending_hscb = pending_scb->hscb; 2131 pending_hscb->control &= ~ULTRAENB; 2132 if ((tstate->ultraenb & devinfo.target_mask) != 0) 2133 pending_hscb->control |= ULTRAENB; 2134 pending_hscb->scsirate = tinfo->scsirate; 2135 pending_hscb->scsioffset = tinfo->curr.offset; 2136 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 2137 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 2138 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 2139 pending_hscb->control &= ~MK_MESSAGE; 2140 } 2141 ahc_sync_scb(ahc, pending_scb, 2142 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2143 pending_scb_count++; 2144 } 2145 2146 if (pending_scb_count == 0) 2147 return; 2148 2149 if (ahc_is_paused(ahc)) { 2150 paused = 1; 2151 } else { 2152 paused = 0; 2153 ahc_pause(ahc); 2154 } 2155 2156 saved_scbptr = ahc_inb(ahc, SCBPTR); 2157 /* Ensure that the hscbs down on the card match the new information */ 2158 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 2159 struct hardware_scb *pending_hscb; 2160 u_int control; 2161 u_int scb_tag; 2162 2163 ahc_outb(ahc, SCBPTR, i); 2164 scb_tag = ahc_inb(ahc, SCB_TAG); 2165 pending_scb = ahc_lookup_scb(ahc, scb_tag); 2166 if (pending_scb == NULL) 2167 continue; 2168 2169 pending_hscb = pending_scb->hscb; 2170 control = ahc_inb(ahc, SCB_CONTROL); 2171 control &= ~(ULTRAENB|MK_MESSAGE); 2172 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE); 2173 ahc_outb(ahc, SCB_CONTROL, control); 2174 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate); 2175 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset); 2176 } 2177 ahc_outb(ahc, SCBPTR, saved_scbptr); 2178 2179 if (paused == 0) 2180 ahc_unpause(ahc); 2181} 2182 2183/**************************** Pathing Information *****************************/ 2184static void 2185ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2186{ 2187 u_int saved_scsiid; 2188 role_t role; 2189 int our_id; 2190 2191 if (ahc_inb(ahc, SSTAT0) & TARGET) 2192 role = ROLE_TARGET; 2193 else 2194 role = ROLE_INITIATOR; 2195 2196 if (role == ROLE_TARGET 2197 && (ahc->features & AHC_MULTI_TID) != 0 2198 && (ahc_inb(ahc, SEQ_FLAGS) 2199 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) { 2200 /* We were selected, so pull our id from TARGIDIN */ 2201 our_id = ahc_inb(ahc, TARGIDIN) & OID; 2202 } else if ((ahc->features & AHC_ULTRA2) != 0) 2203 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 2204 else 2205 our_id = ahc_inb(ahc, SCSIID) & OID; 2206 2207 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 2208 ahc_compile_devinfo(devinfo, 2209 our_id, 2210 SCSIID_TARGET(ahc, saved_scsiid), 2211 ahc_inb(ahc, SAVED_LUN), 2212 SCSIID_CHANNEL(ahc, saved_scsiid), 2213 role); 2214} 2215 2216struct ahc_phase_table_entry* 2217ahc_lookup_phase_entry(int phase) 2218{ 2219 struct ahc_phase_table_entry *entry; 2220 struct ahc_phase_table_entry *last_entry; 2221 2222 /* 2223 * num_phases doesn't include the default entry which 2224 * will be returned if the phase doesn't match. 2225 */ 2226 last_entry = &ahc_phase_table[num_phases]; 2227 for (entry = ahc_phase_table; entry < last_entry; entry++) { 2228 if (phase == entry->phase) 2229 break; 2230 } 2231 return (entry); 2232} 2233 2234void 2235ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 2236 u_int lun, char channel, role_t role) 2237{ 2238 devinfo->our_scsiid = our_id; 2239 devinfo->target = target; 2240 devinfo->lun = lun; 2241 devinfo->target_offset = target; 2242 devinfo->channel = channel; 2243 devinfo->role = role; 2244 if (channel == 'B') 2245 devinfo->target_offset += 8; 2246 devinfo->target_mask = (0x01 << devinfo->target_offset); 2247} 2248 2249void 2250ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2251{ 2252 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel, 2253 devinfo->target, devinfo->lun); 2254} 2255 2256static void 2257ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2258 struct scb *scb) 2259{ 2260 role_t role; 2261 int our_id; 2262 2263 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 2264 role = ROLE_INITIATOR; 2265 if ((scb->flags & SCB_TARGET_SCB) != 0) 2266 role = ROLE_TARGET; 2267 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb), 2268 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role); 2269} 2270 2271 2272/************************ Message Phase Processing ****************************/ 2273static void 2274ahc_assert_atn(struct ahc_softc *ahc) 2275{ 2276 u_int scsisigo; 2277 2278 scsisigo = ATNO; 2279 if ((ahc->features & AHC_DT) == 0) 2280 scsisigo |= ahc_inb(ahc, SCSISIGI); 2281 ahc_outb(ahc, SCSISIGO, scsisigo); 2282} 2283 2284/* 2285 * When an initiator transaction with the MK_MESSAGE flag either reconnects 2286 * or enters the initial message out phase, we are interrupted. Fill our 2287 * outgoing message buffer with the appropriate message and beging handing 2288 * the message phase(s) manually. 2289 */ 2290static void 2291ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2292 struct scb *scb) 2293{ 2294 /* 2295 * To facilitate adding multiple messages together, 2296 * each routine should increment the index and len 2297 * variables instead of setting them explicitly. 2298 */ 2299 ahc->msgout_index = 0; 2300 ahc->msgout_len = 0; 2301 2302 if ((scb->flags & SCB_DEVICE_RESET) == 0 2303 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2304 u_int identify_msg; 2305 2306 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 2307 if ((scb->hscb->control & DISCENB) != 0) 2308 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2309 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2310 ahc->msgout_len++; 2311 2312 if ((scb->hscb->control & TAG_ENB) != 0) { 2313 ahc->msgout_buf[ahc->msgout_index++] = 2314 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 2315 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2316 ahc->msgout_len += 2; 2317 } 2318 } 2319 2320 if (scb->flags & SCB_DEVICE_RESET) { 2321 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2322 ahc->msgout_len++; 2323 ahc_print_path(ahc, scb); 2324 printf("Bus Device Reset Message Sent\n"); 2325 /* 2326 * Clear our selection hardware in advance of 2327 * the busfree. We may have an entry in the waiting 2328 * Q for this target, and we don't want to go about 2329 * selecting while we handle the busfree and blow it 2330 * away. 2331 */ 2332 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2333 } else if ((scb->flags & SCB_ABORT) != 0) { 2334 if ((scb->hscb->control & TAG_ENB) != 0) 2335 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2336 else 2337 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2338 ahc->msgout_len++; 2339 ahc_print_path(ahc, scb); 2340 printf("Abort%s Message Sent\n", 2341 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 2342 /* 2343 * Clear our selection hardware in advance of 2344 * the busfree. We may have an entry in the waiting 2345 * Q for this target, and we don't want to go about 2346 * selecting while we handle the busfree and blow it 2347 * away. 2348 */ 2349 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2350 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 2351 ahc_build_transfer_msg(ahc, devinfo); 2352 } else { 2353 printf("ahc_intr: AWAITING_MSG for an SCB that " 2354 "does not have a waiting message\n"); 2355 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 2356 devinfo->target_mask); 2357 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2358 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2359 ahc_inb(ahc, MSG_OUT), scb->flags); 2360 } 2361 2362 /* 2363 * Clear the MK_MESSAGE flag from the SCB so we aren't 2364 * asked to send this message again. 2365 */ 2366 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2367 scb->hscb->control &= ~MK_MESSAGE; 2368 ahc->msgout_index = 0; 2369 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2370} 2371 2372/* 2373 * Build an appropriate transfer negotiation message for the 2374 * currently active target. 2375 */ 2376static void 2377ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2378{ 2379 /* 2380 * We need to initiate transfer negotiations. 2381 * If our current and goal settings are identical, 2382 * we want to renegotiate due to a check condition. 2383 */ 2384 struct ahc_initiator_tinfo *tinfo; 2385 struct ahc_tmode_tstate *tstate; 2386 struct ahc_syncrate *rate; 2387 int dowide; 2388 int dosync; 2389 int doppr; 2390 u_int period; 2391 u_int ppr_options; 2392 u_int offset; 2393 2394 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2395 devinfo->target, &tstate); 2396 /* 2397 * Filter our period based on the current connection. 2398 * If we can't perform DT transfers on this segment (not in LVD 2399 * mode for instance), then our decision to issue a PPR message 2400 * may change. 2401 */ 2402 period = tinfo->goal.period; 2403 offset = tinfo->goal.offset; 2404 ppr_options = tinfo->goal.ppr_options; 2405 /* Target initiated PPR is not allowed in the SCSI spec */ 2406 if (devinfo->role == ROLE_TARGET) 2407 ppr_options = 0; 2408 rate = ahc_devlimited_syncrate(ahc, tinfo, &period, 2409 &ppr_options, devinfo->role); 2410 dowide = tinfo->curr.width != tinfo->goal.width; 2411 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period; 2412 /* 2413 * Only use PPR if we have options that need it, even if the device 2414 * claims to support it. There might be an expander in the way 2415 * that doesn't. 2416 */ 2417 doppr = ppr_options != 0; 2418 2419 if (!dowide && !dosync && !doppr) { 2420 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2421 dosync = tinfo->goal.offset != 0; 2422 } 2423 2424 if (!dowide && !dosync && !doppr) { 2425 /* 2426 * Force async with a WDTR message if we have a wide bus, 2427 * or just issue an SDTR with a 0 offset. 2428 */ 2429 if ((ahc->features & AHC_WIDE) != 0) 2430 dowide = 1; 2431 else 2432 dosync = 1; 2433 2434 if (bootverbose) { 2435 ahc_print_devinfo(ahc, devinfo); 2436 printf("Ensuring async\n"); 2437 } 2438 } 2439 2440 /* Target initiated PPR is not allowed in the SCSI spec */ 2441 if (devinfo->role == ROLE_TARGET) 2442 doppr = 0; 2443 2444 /* 2445 * Both the PPR message and SDTR message require the 2446 * goal syncrate to be limited to what the target device 2447 * is capable of handling (based on whether an LVD->SE 2448 * expander is on the bus), so combine these two cases. 2449 * Regardless, guarantee that if we are using WDTR and SDTR 2450 * messages that WDTR comes first. 2451 */ 2452 if (doppr || (dosync && !dowide)) { 2453 2454 offset = tinfo->goal.offset; 2455 ahc_validate_offset(ahc, tinfo, rate, &offset, 2456 doppr ? tinfo->goal.width 2457 : tinfo->curr.width, 2458 devinfo->role); 2459 if (doppr) { 2460 ahc_construct_ppr(ahc, devinfo, period, offset, 2461 tinfo->goal.width, ppr_options); 2462 } else { 2463 ahc_construct_sdtr(ahc, devinfo, period, offset); 2464 } 2465 } else { 2466 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width); 2467 } 2468} 2469 2470/* 2471 * Build a synchronous negotiation message in our message 2472 * buffer based on the input parameters. 2473 */ 2474static void 2475ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2476 u_int period, u_int offset) 2477{ 2478 if (offset == 0) 2479 period = AHC_ASYNC_XFER_PERIOD; 2480 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2481 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 2482 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 2483 ahc->msgout_buf[ahc->msgout_index++] = period; 2484 ahc->msgout_buf[ahc->msgout_index++] = offset; 2485 ahc->msgout_len += 5; 2486 if (bootverbose) { 2487 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 2488 ahc_name(ahc), devinfo->channel, devinfo->target, 2489 devinfo->lun, period, offset); 2490 } 2491} 2492 2493/* 2494 * Build a wide negotiation message in our message 2495 * buffer based on the input parameters. 2496 */ 2497static void 2498ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2499 u_int bus_width) 2500{ 2501 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2502 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 2503 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 2504 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2505 ahc->msgout_len += 4; 2506 if (bootverbose) { 2507 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 2508 ahc_name(ahc), devinfo->channel, devinfo->target, 2509 devinfo->lun, bus_width); 2510 } 2511} 2512 2513/* 2514 * Build a parallel protocol request message in our message 2515 * buffer based on the input parameters. 2516 */ 2517static void 2518ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2519 u_int period, u_int offset, u_int bus_width, 2520 u_int ppr_options) 2521{ 2522 if (offset == 0) 2523 period = AHC_ASYNC_XFER_PERIOD; 2524 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2525 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN; 2526 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR; 2527 ahc->msgout_buf[ahc->msgout_index++] = period; 2528 ahc->msgout_buf[ahc->msgout_index++] = 0; 2529 ahc->msgout_buf[ahc->msgout_index++] = offset; 2530 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2531 ahc->msgout_buf[ahc->msgout_index++] = ppr_options; 2532 ahc->msgout_len += 8; 2533 if (bootverbose) { 2534 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " 2535 "offset %x, ppr_options %x\n", ahc_name(ahc), 2536 devinfo->channel, devinfo->target, devinfo->lun, 2537 bus_width, period, offset, ppr_options); 2538 } 2539} 2540 2541/* 2542 * Clear any active message state. 2543 */ 2544static void 2545ahc_clear_msg_state(struct ahc_softc *ahc) 2546{ 2547 ahc->msgout_len = 0; 2548 ahc->msgin_index = 0; 2549 ahc->msg_type = MSG_TYPE_NONE; 2550 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) { 2551 /* 2552 * The target didn't care to respond to our 2553 * message request, so clear ATN. 2554 */ 2555 ahc_outb(ahc, CLRSINT1, CLRATNO); 2556 } 2557 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2558 ahc_outb(ahc, SEQ_FLAGS2, 2559 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 2560} 2561 2562static void 2563ahc_handle_proto_violation(struct ahc_softc *ahc) 2564{ 2565 struct ahc_devinfo devinfo; 2566 struct scb *scb; 2567 u_int scbid; 2568 u_int seq_flags; 2569 u_int curphase; 2570 u_int lastphase; 2571 int found; 2572 2573 ahc_fetch_devinfo(ahc, &devinfo); 2574 scbid = ahc_inb(ahc, SCB_TAG); 2575 scb = ahc_lookup_scb(ahc, scbid); 2576 seq_flags = ahc_inb(ahc, SEQ_FLAGS); 2577 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2578 lastphase = ahc_inb(ahc, LASTPHASE); 2579 if ((seq_flags & NOT_IDENTIFIED) != 0) { 2580 2581 /* 2582 * The reconnecting target either did not send an 2583 * identify message, or did, but we didn't find an SCB 2584 * to match. 2585 */ 2586 ahc_print_devinfo(ahc, &devinfo); 2587 printf("Target did not send an IDENTIFY message. " 2588 "LASTPHASE = 0x%x.\n", lastphase); 2589 scb = NULL; 2590 } else if (scb == NULL) { 2591 /* 2592 * We don't seem to have an SCB active for this 2593 * transaction. Print an error and reset the bus. 2594 */ 2595 ahc_print_devinfo(ahc, &devinfo); 2596 printf("No SCB found during protocol violation\n"); 2597 goto proto_violation_reset; 2598 } else { 2599 aic_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2600 if ((seq_flags & NO_CDB_SENT) != 0) { 2601 ahc_print_path(ahc, scb); 2602 printf("No or incomplete CDB sent to device.\n"); 2603 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) { 2604 /* 2605 * The target never bothered to provide status to 2606 * us prior to completing the command. Since we don't 2607 * know the disposition of this command, we must attempt 2608 * to abort it. Assert ATN and prepare to send an abort 2609 * message. 2610 */ 2611 ahc_print_path(ahc, scb); 2612 printf("Completed command without status.\n"); 2613 } else { 2614 ahc_print_path(ahc, scb); 2615 printf("Unknown protocol violation.\n"); 2616 ahc_dump_card_state(ahc); 2617 } 2618 } 2619 if ((lastphase & ~P_DATAIN_DT) == 0 2620 || lastphase == P_COMMAND) { 2621proto_violation_reset: 2622 /* 2623 * Target either went directly to data/command 2624 * phase or didn't respond to our ATN. 2625 * The only safe thing to do is to blow 2626 * it away with a bus reset. 2627 */ 2628 found = ahc_reset_channel(ahc, 'A', TRUE); 2629 printf("%s: Issued Channel %c Bus Reset. " 2630 "%d SCBs aborted\n", ahc_name(ahc), 'A', found); 2631 } else { 2632 /* 2633 * Leave the selection hardware off in case 2634 * this abort attempt will affect yet to 2635 * be sent commands. 2636 */ 2637 ahc_outb(ahc, SCSISEQ, 2638 ahc_inb(ahc, SCSISEQ) & ~ENSELO); 2639 ahc_assert_atn(ahc); 2640 ahc_outb(ahc, MSG_OUT, HOST_MSG); 2641 if (scb == NULL) { 2642 ahc_print_devinfo(ahc, &devinfo); 2643 ahc->msgout_buf[0] = MSG_ABORT_TASK; 2644 ahc->msgout_len = 1; 2645 ahc->msgout_index = 0; 2646 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2647 } else { 2648 ahc_print_path(ahc, scb); 2649 scb->flags |= SCB_ABORT; 2650 } 2651 printf("Protocol violation %s. Attempting to abort.\n", 2652 ahc_lookup_phase_entry(curphase)->phasemsg); 2653 } 2654} 2655 2656/* 2657 * Manual message loop handler. 2658 */ 2659static void 2660ahc_handle_message_phase(struct ahc_softc *ahc) 2661{ 2662 struct ahc_devinfo devinfo; 2663 u_int bus_phase; 2664 int end_session; 2665 2666 ahc_fetch_devinfo(ahc, &devinfo); 2667 end_session = FALSE; 2668 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2669 2670reswitch: 2671 switch (ahc->msg_type) { 2672 case MSG_TYPE_INITIATOR_MSGOUT: 2673 { 2674 int lastbyte; 2675 int phasemis; 2676 int msgdone; 2677 2678 if (ahc->msgout_len == 0) 2679 panic("HOST_MSG_LOOP interrupt with no active message"); 2680 2681#ifdef AHC_DEBUG 2682 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2683 ahc_print_devinfo(ahc, &devinfo); 2684 printf("INITIATOR_MSG_OUT"); 2685 } 2686#endif 2687 phasemis = bus_phase != P_MESGOUT; 2688 if (phasemis) { 2689#ifdef AHC_DEBUG 2690 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2691 printf(" PHASEMIS %s\n", 2692 ahc_lookup_phase_entry(bus_phase) 2693 ->phasemsg); 2694 } 2695#endif 2696 if (bus_phase == P_MESGIN) { 2697 /* 2698 * Change gears and see if 2699 * this messages is of interest to 2700 * us or should be passed back to 2701 * the sequencer. 2702 */ 2703 ahc_outb(ahc, CLRSINT1, CLRATNO); 2704 ahc->send_msg_perror = FALSE; 2705 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2706 ahc->msgin_index = 0; 2707 goto reswitch; 2708 } 2709 end_session = TRUE; 2710 break; 2711 } 2712 2713 if (ahc->send_msg_perror) { 2714 ahc_outb(ahc, CLRSINT1, CLRATNO); 2715 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2716#ifdef AHC_DEBUG 2717 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2718 printf(" byte 0x%x\n", ahc->send_msg_perror); 2719#endif 2720 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2721 break; 2722 } 2723 2724 msgdone = ahc->msgout_index == ahc->msgout_len; 2725 if (msgdone) { 2726 /* 2727 * The target has requested a retry. 2728 * Re-assert ATN, reset our message index to 2729 * 0, and try again. 2730 */ 2731 ahc->msgout_index = 0; 2732 ahc_assert_atn(ahc); 2733 } 2734 2735 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2736 if (lastbyte) { 2737 /* Last byte is signified by dropping ATN */ 2738 ahc_outb(ahc, CLRSINT1, CLRATNO); 2739 } 2740 2741 /* 2742 * Clear our interrupt status and present 2743 * the next byte on the bus. 2744 */ 2745 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2746#ifdef AHC_DEBUG 2747 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2748 printf(" byte 0x%x\n", 2749 ahc->msgout_buf[ahc->msgout_index]); 2750#endif 2751 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2752 break; 2753 } 2754 case MSG_TYPE_INITIATOR_MSGIN: 2755 { 2756 int phasemis; 2757 int message_done; 2758 2759#ifdef AHC_DEBUG 2760 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2761 ahc_print_devinfo(ahc, &devinfo); 2762 printf("INITIATOR_MSG_IN"); 2763 } 2764#endif 2765 phasemis = bus_phase != P_MESGIN; 2766 if (phasemis) { 2767#ifdef AHC_DEBUG 2768 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2769 printf(" PHASEMIS %s\n", 2770 ahc_lookup_phase_entry(bus_phase) 2771 ->phasemsg); 2772 } 2773#endif 2774 ahc->msgin_index = 0; 2775 if (bus_phase == P_MESGOUT 2776 && (ahc->send_msg_perror == TRUE 2777 || (ahc->msgout_len != 0 2778 && ahc->msgout_index == 0))) { 2779 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2780 goto reswitch; 2781 } 2782 end_session = TRUE; 2783 break; 2784 } 2785 2786 /* Pull the byte in without acking it */ 2787 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2788#ifdef AHC_DEBUG 2789 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2790 printf(" byte 0x%x\n", 2791 ahc->msgin_buf[ahc->msgin_index]); 2792#endif 2793 2794 message_done = ahc_parse_msg(ahc, &devinfo); 2795 2796 if (message_done) { 2797 /* 2798 * Clear our incoming message buffer in case there 2799 * is another message following this one. 2800 */ 2801 ahc->msgin_index = 0; 2802 2803 /* 2804 * If this message illicited a response, 2805 * assert ATN so the target takes us to the 2806 * message out phase. 2807 */ 2808 if (ahc->msgout_len != 0) { 2809#ifdef AHC_DEBUG 2810 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2811 ahc_print_devinfo(ahc, &devinfo); 2812 printf("Asserting ATN for response\n"); 2813 } 2814#endif 2815 ahc_assert_atn(ahc); 2816 } 2817 } else 2818 ahc->msgin_index++; 2819 2820 if (message_done == MSGLOOP_TERMINATED) { 2821 end_session = TRUE; 2822 } else { 2823 /* Ack the byte */ 2824 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2825 ahc_inb(ahc, SCSIDATL); 2826 } 2827 break; 2828 } 2829 case MSG_TYPE_TARGET_MSGIN: 2830 { 2831 int msgdone; 2832 2833 if (ahc->msgout_len == 0) 2834 panic("Target MSGIN with no active message"); 2835 2836#ifdef AHC_DEBUG 2837 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2838 ahc_print_devinfo(ahc, &devinfo); 2839 printf("TARGET_MSG_IN"); 2840 } 2841#endif 2842 2843 /* 2844 * If we interrupted a mesgout session, the initiator 2845 * will not know this until our first REQ. So, we 2846 * only honor mesgout requests after we've sent our 2847 * first byte. 2848 */ 2849 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2850 && ahc->msgout_index > 0) { 2851 2852 /* 2853 * Change gears and see if this messages is 2854 * of interest to us or should be passed back 2855 * to the sequencer. 2856 */ 2857#ifdef AHC_DEBUG 2858 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2859 printf(" Honoring ATN Request.\n"); 2860#endif 2861 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2862 2863 /* 2864 * Disable SCSI Programmed I/O during the 2865 * phase change so as to avoid phantom REQs. 2866 */ 2867 ahc_outb(ahc, SXFRCTL0, 2868 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2869 2870 /* 2871 * Since SPIORDY asserts when ACK is asserted 2872 * for P_MSGOUT, and SPIORDY's assertion triggered 2873 * our entry into this routine, wait for ACK to 2874 * *de-assert* before changing phases. 2875 */ 2876 while ((ahc_inb(ahc, SCSISIGI) & ACKI) != 0) 2877 ; 2878 2879 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2880 2881 /* 2882 * All phase line changes require a bus 2883 * settle delay before REQ is asserted. 2884 * [SCSI SPI4 10.7.1] 2885 */ 2886 ahc_flush_device_writes(ahc); 2887 aic_delay(AHC_BUSSETTLE_DELAY); 2888 2889 ahc->msgin_index = 0; 2890 /* Enable SCSI Programmed I/O to REQ for first byte */ 2891 ahc_outb(ahc, SXFRCTL0, 2892 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2893 break; 2894 } 2895 2896 msgdone = ahc->msgout_index == ahc->msgout_len; 2897 if (msgdone) { 2898 ahc_outb(ahc, SXFRCTL0, 2899 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2900 end_session = TRUE; 2901 break; 2902 } 2903 2904 /* 2905 * Present the next byte on the bus. 2906 */ 2907#ifdef AHC_DEBUG 2908 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2909 printf(" byte 0x%x\n", 2910 ahc->msgout_buf[ahc->msgout_index]); 2911#endif 2912 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2913 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2914 break; 2915 } 2916 case MSG_TYPE_TARGET_MSGOUT: 2917 { 2918 int lastbyte; 2919 int msgdone; 2920 2921#ifdef AHC_DEBUG 2922 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2923 ahc_print_devinfo(ahc, &devinfo); 2924 printf("TARGET_MSG_OUT"); 2925 } 2926#endif 2927 /* 2928 * The initiator signals that this is 2929 * the last byte by dropping ATN. 2930 */ 2931 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2932 2933 /* 2934 * Read the latched byte, but turn off SPIOEN first 2935 * so that we don't inadvertently cause a REQ for the 2936 * next byte. 2937 */ 2938 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2939 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2940 2941#ifdef AHC_DEBUG 2942 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2943 printf(" byte 0x%x\n", 2944 ahc->msgin_buf[ahc->msgin_index]); 2945#endif 2946 2947 msgdone = ahc_parse_msg(ahc, &devinfo); 2948 if (msgdone == MSGLOOP_TERMINATED) { 2949 /* 2950 * The message is *really* done in that it caused 2951 * us to go to bus free. The sequencer has already 2952 * been reset at this point, so pull the ejection 2953 * handle. 2954 */ 2955 return; 2956 } 2957 2958 ahc->msgin_index++; 2959 2960 /* 2961 * XXX Read spec about initiator dropping ATN too soon 2962 * and use msgdone to detect it. 2963 */ 2964 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2965 ahc->msgin_index = 0; 2966 2967 /* 2968 * If this message illicited a response, transition 2969 * to the Message in phase and send it. 2970 */ 2971 if (ahc->msgout_len != 0) { 2972#ifdef AHC_DEBUG 2973 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2974 ahc_print_devinfo(ahc, &devinfo); 2975 printf(" preparing response.\n"); 2976 } 2977#endif 2978 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2979 2980 /* 2981 * All phase line changes require a bus 2982 * settle delay before REQ is asserted. 2983 * [SCSI SPI4 10.7.1] When transitioning 2984 * from an OUT to an IN phase, we must 2985 * also wait a data release delay to allow 2986 * the initiator time to release the data 2987 * lines. [SCSI SPI4 10.12] 2988 */ 2989 ahc_flush_device_writes(ahc); 2990 aic_delay(AHC_BUSSETTLE_DELAY 2991 + AHC_DATARELEASE_DELAY); 2992 2993 /* 2994 * Enable SCSI Programmed I/O. This will 2995 * immediately cause SPIORDY to assert, 2996 * and the sequencer will call our message 2997 * loop again. 2998 */ 2999 ahc_outb(ahc, SXFRCTL0, 3000 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 3001 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 3002 ahc->msgin_index = 0; 3003 break; 3004 } 3005 } 3006 3007 if (lastbyte) 3008 end_session = TRUE; 3009 else { 3010 /* Ask for the next byte. */ 3011 ahc_outb(ahc, SXFRCTL0, 3012 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 3013 } 3014 3015 break; 3016 } 3017 default: 3018 panic("Unknown REQINIT message type"); 3019 } 3020 3021 if (end_session) { 3022 ahc_clear_msg_state(ahc); 3023 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 3024 } else 3025 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 3026} 3027 3028/* 3029 * See if we sent a particular extended message to the target. 3030 * If "full" is true, return true only if the target saw the full 3031 * message. If "full" is false, return true if the target saw at 3032 * least the first byte of the message. 3033 */ 3034static int 3035ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full) 3036{ 3037 int found; 3038 u_int index; 3039 3040 found = FALSE; 3041 index = 0; 3042 3043 while (index < ahc->msgout_len) { 3044 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 3045 u_int end_index; 3046 3047 end_index = index + 1 + ahc->msgout_buf[index + 1]; 3048 if (ahc->msgout_buf[index+2] == msgval 3049 && type == AHCMSG_EXT) { 3050 3051 if (full) { 3052 if (ahc->msgout_index > end_index) 3053 found = TRUE; 3054 } else if (ahc->msgout_index > index) 3055 found = TRUE; 3056 } 3057 index = end_index; 3058 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK 3059 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 3060 3061 /* Skip tag type and tag id or residue param*/ 3062 index += 2; 3063 } else { 3064 /* Single byte message */ 3065 if (type == AHCMSG_1B 3066 && ahc->msgout_buf[index] == msgval 3067 && ahc->msgout_index > index) 3068 found = TRUE; 3069 index++; 3070 } 3071 3072 if (found) 3073 break; 3074 } 3075 return (found); 3076} 3077 3078/* 3079 * Wait for a complete incoming message, parse it, and respond accordingly. 3080 */ 3081static int 3082ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3083{ 3084 struct ahc_initiator_tinfo *tinfo; 3085 struct ahc_tmode_tstate *tstate; 3086 int reject; 3087 int done; 3088 int response; 3089 u_int targ_scsirate; 3090 3091 done = MSGLOOP_IN_PROG; 3092 response = FALSE; 3093 reject = FALSE; 3094 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 3095 devinfo->target, &tstate); 3096 targ_scsirate = tinfo->scsirate; 3097 3098 /* 3099 * Parse as much of the message as is available, 3100 * rejecting it if we don't support it. When 3101 * the entire message is available and has been 3102 * handled, return MSGLOOP_MSGCOMPLETE, indicating 3103 * that we have parsed an entire message. 3104 * 3105 * In the case of extended messages, we accept the length 3106 * byte outright and perform more checking once we know the 3107 * extended message type. 3108 */ 3109 switch (ahc->msgin_buf[0]) { 3110 case MSG_DISCONNECT: 3111 case MSG_SAVEDATAPOINTER: 3112 case MSG_CMDCOMPLETE: 3113 case MSG_RESTOREPOINTERS: 3114 case MSG_IGN_WIDE_RESIDUE: 3115 /* 3116 * End our message loop as these are messages 3117 * the sequencer handles on its own. 3118 */ 3119 done = MSGLOOP_TERMINATED; 3120 break; 3121 case MSG_MESSAGE_REJECT: 3122 response = ahc_handle_msg_reject(ahc, devinfo); 3123 /* FALLTHROUGH */ 3124 case MSG_NOOP: 3125 done = MSGLOOP_MSGCOMPLETE; 3126 break; 3127 case MSG_EXTENDED: 3128 { 3129 /* Wait for enough of the message to begin validation */ 3130 if (ahc->msgin_index < 2) 3131 break; 3132 switch (ahc->msgin_buf[2]) { 3133 case MSG_EXT_SDTR: 3134 { 3135 struct ahc_syncrate *syncrate; 3136 u_int period; 3137 u_int ppr_options; 3138 u_int offset; 3139 u_int saved_offset; 3140 3141 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 3142 reject = TRUE; 3143 break; 3144 } 3145 3146 /* 3147 * Wait until we have both args before validating 3148 * and acting on this message. 3149 * 3150 * Add one to MSG_EXT_SDTR_LEN to account for 3151 * the extended message preamble. 3152 */ 3153 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3154 break; 3155 3156 period = ahc->msgin_buf[3]; 3157 ppr_options = 0; 3158 saved_offset = offset = ahc->msgin_buf[4]; 3159 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3160 &ppr_options, 3161 devinfo->role); 3162 ahc_validate_offset(ahc, tinfo, syncrate, &offset, 3163 targ_scsirate & WIDEXFER, 3164 devinfo->role); 3165 if (bootverbose) { 3166 printf("(%s:%c:%d:%d): Received " 3167 "SDTR period %x, offset %x\n\t" 3168 "Filtered to period %x, offset %x\n", 3169 ahc_name(ahc), devinfo->channel, 3170 devinfo->target, devinfo->lun, 3171 ahc->msgin_buf[3], saved_offset, 3172 period, offset); 3173 } 3174 ahc_set_syncrate(ahc, devinfo, 3175 syncrate, period, 3176 offset, ppr_options, 3177 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3178 /*paused*/TRUE); 3179 3180 /* 3181 * See if we initiated Sync Negotiation 3182 * and didn't have to fall down to async 3183 * transfers. 3184 */ 3185 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) { 3186 /* We started it */ 3187 if (saved_offset != offset) { 3188 /* Went too low - force async */ 3189 reject = TRUE; 3190 } 3191 } else { 3192 /* 3193 * Send our own SDTR in reply 3194 */ 3195 if (bootverbose 3196 && devinfo->role == ROLE_INITIATOR) { 3197 printf("(%s:%c:%d:%d): Target " 3198 "Initiated SDTR\n", 3199 ahc_name(ahc), devinfo->channel, 3200 devinfo->target, devinfo->lun); 3201 } 3202 ahc->msgout_index = 0; 3203 ahc->msgout_len = 0; 3204 ahc_construct_sdtr(ahc, devinfo, 3205 period, offset); 3206 ahc->msgout_index = 0; 3207 response = TRUE; 3208 } 3209 done = MSGLOOP_MSGCOMPLETE; 3210 break; 3211 } 3212 case MSG_EXT_WDTR: 3213 { 3214 u_int bus_width; 3215 u_int saved_width; 3216 u_int sending_reply; 3217 3218 sending_reply = FALSE; 3219 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3220 reject = TRUE; 3221 break; 3222 } 3223 3224 /* 3225 * Wait until we have our arg before validating 3226 * and acting on this message. 3227 * 3228 * Add one to MSG_EXT_WDTR_LEN to account for 3229 * the extended message preamble. 3230 */ 3231 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3232 break; 3233 3234 bus_width = ahc->msgin_buf[3]; 3235 saved_width = bus_width; 3236 ahc_validate_width(ahc, tinfo, &bus_width, 3237 devinfo->role); 3238 if (bootverbose) { 3239 printf("(%s:%c:%d:%d): Received WDTR " 3240 "%x filtered to %x\n", 3241 ahc_name(ahc), devinfo->channel, 3242 devinfo->target, devinfo->lun, 3243 saved_width, bus_width); 3244 } 3245 3246 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) { 3247 /* 3248 * Don't send a WDTR back to the 3249 * target, since we asked first. 3250 * If the width went higher than our 3251 * request, reject it. 3252 */ 3253 if (saved_width > bus_width) { 3254 reject = TRUE; 3255 printf("(%s:%c:%d:%d): requested %dBit " 3256 "transfers. Rejecting...\n", 3257 ahc_name(ahc), devinfo->channel, 3258 devinfo->target, devinfo->lun, 3259 8 * (0x01 << bus_width)); 3260 bus_width = 0; 3261 } 3262 } else { 3263 /* 3264 * Send our own WDTR in reply 3265 */ 3266 if (bootverbose 3267 && devinfo->role == ROLE_INITIATOR) { 3268 printf("(%s:%c:%d:%d): Target " 3269 "Initiated WDTR\n", 3270 ahc_name(ahc), devinfo->channel, 3271 devinfo->target, devinfo->lun); 3272 } 3273 ahc->msgout_index = 0; 3274 ahc->msgout_len = 0; 3275 ahc_construct_wdtr(ahc, devinfo, bus_width); 3276 ahc->msgout_index = 0; 3277 response = TRUE; 3278 sending_reply = TRUE; 3279 } 3280 /* 3281 * After a wide message, we are async, but 3282 * some devices don't seem to honor this portion 3283 * of the spec. Force a renegotiation of the 3284 * sync component of our transfer agreement even 3285 * if our goal is async. By updating our width 3286 * after forcing the negotiation, we avoid 3287 * renegotiating for width. 3288 */ 3289 ahc_update_neg_request(ahc, devinfo, tstate, 3290 tinfo, AHC_NEG_ALWAYS); 3291 ahc_set_width(ahc, devinfo, bus_width, 3292 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3293 /*paused*/TRUE); 3294 if (sending_reply == FALSE && reject == FALSE) { 3295 3296 /* 3297 * We will always have an SDTR to send. 3298 */ 3299 ahc->msgout_index = 0; 3300 ahc->msgout_len = 0; 3301 ahc_build_transfer_msg(ahc, devinfo); 3302 ahc->msgout_index = 0; 3303 response = TRUE; 3304 } 3305 done = MSGLOOP_MSGCOMPLETE; 3306 break; 3307 } 3308 case MSG_EXT_PPR: 3309 { 3310 struct ahc_syncrate *syncrate; 3311 u_int period; 3312 u_int offset; 3313 u_int bus_width; 3314 u_int ppr_options; 3315 u_int saved_width; 3316 u_int saved_offset; 3317 u_int saved_ppr_options; 3318 3319 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) { 3320 reject = TRUE; 3321 break; 3322 } 3323 3324 /* 3325 * Wait until we have all args before validating 3326 * and acting on this message. 3327 * 3328 * Add one to MSG_EXT_PPR_LEN to account for 3329 * the extended message preamble. 3330 */ 3331 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1)) 3332 break; 3333 3334 period = ahc->msgin_buf[3]; 3335 offset = ahc->msgin_buf[5]; 3336 bus_width = ahc->msgin_buf[6]; 3337 saved_width = bus_width; 3338 ppr_options = ahc->msgin_buf[7]; 3339 /* 3340 * According to the spec, a DT only 3341 * period factor with no DT option 3342 * set implies async. 3343 */ 3344 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 3345 && period == 9) 3346 offset = 0; 3347 saved_ppr_options = ppr_options; 3348 saved_offset = offset; 3349 3350 /* 3351 * Mask out any options we don't support 3352 * on any controller. Transfer options are 3353 * only available if we are negotiating wide. 3354 */ 3355 ppr_options &= MSG_EXT_PPR_DT_REQ; 3356 if (bus_width == 0) 3357 ppr_options = 0; 3358 3359 ahc_validate_width(ahc, tinfo, &bus_width, 3360 devinfo->role); 3361 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3362 &ppr_options, 3363 devinfo->role); 3364 ahc_validate_offset(ahc, tinfo, syncrate, 3365 &offset, bus_width, 3366 devinfo->role); 3367 3368 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) { 3369 /* 3370 * If we are unable to do any of the 3371 * requested options (we went too low), 3372 * then we'll have to reject the message. 3373 */ 3374 if (saved_width > bus_width 3375 || saved_offset != offset 3376 || saved_ppr_options != ppr_options) { 3377 reject = TRUE; 3378 period = 0; 3379 offset = 0; 3380 bus_width = 0; 3381 ppr_options = 0; 3382 syncrate = NULL; 3383 } 3384 } else { 3385 if (devinfo->role != ROLE_TARGET) 3386 printf("(%s:%c:%d:%d): Target " 3387 "Initiated PPR\n", 3388 ahc_name(ahc), devinfo->channel, 3389 devinfo->target, devinfo->lun); 3390 else 3391 printf("(%s:%c:%d:%d): Initiator " 3392 "Initiated PPR\n", 3393 ahc_name(ahc), devinfo->channel, 3394 devinfo->target, devinfo->lun); 3395 ahc->msgout_index = 0; 3396 ahc->msgout_len = 0; 3397 ahc_construct_ppr(ahc, devinfo, period, offset, 3398 bus_width, ppr_options); 3399 ahc->msgout_index = 0; 3400 response = TRUE; 3401 } 3402 if (bootverbose) { 3403 printf("(%s:%c:%d:%d): Received PPR width %x, " 3404 "period %x, offset %x,options %x\n" 3405 "\tFiltered to width %x, period %x, " 3406 "offset %x, options %x\n", 3407 ahc_name(ahc), devinfo->channel, 3408 devinfo->target, devinfo->lun, 3409 saved_width, ahc->msgin_buf[3], 3410 saved_offset, saved_ppr_options, 3411 bus_width, period, offset, ppr_options); 3412 } 3413 ahc_set_width(ahc, devinfo, bus_width, 3414 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3415 /*paused*/TRUE); 3416 ahc_set_syncrate(ahc, devinfo, 3417 syncrate, period, 3418 offset, ppr_options, 3419 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3420 /*paused*/TRUE); 3421 done = MSGLOOP_MSGCOMPLETE; 3422 break; 3423 } 3424 default: 3425 /* Unknown extended message. Reject it. */ 3426 reject = TRUE; 3427 break; 3428 } 3429 break; 3430 } 3431#ifdef AHC_TARGET_MODE 3432 case MSG_BUS_DEV_RESET: 3433 ahc_handle_devreset(ahc, devinfo, 3434 CAM_BDR_SENT, 3435 "Bus Device Reset Received", 3436 /*verbose_level*/0); 3437 ahc_restart(ahc); 3438 done = MSGLOOP_TERMINATED; 3439 break; 3440 case MSG_ABORT_TAG: 3441 case MSG_ABORT: 3442 case MSG_CLEAR_QUEUE: 3443 { 3444 int tag; 3445 3446 /* Target mode messages */ 3447 if (devinfo->role != ROLE_TARGET) { 3448 reject = TRUE; 3449 break; 3450 } 3451 tag = SCB_LIST_NULL; 3452 if (ahc->msgin_buf[0] == MSG_ABORT_TAG) 3453 tag = ahc_inb(ahc, INITIATOR_TAG); 3454 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3455 devinfo->lun, tag, ROLE_TARGET, 3456 CAM_REQ_ABORTED); 3457 3458 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3459 if (tstate != NULL) { 3460 struct ahc_tmode_lstate* lstate; 3461 3462 lstate = tstate->enabled_luns[devinfo->lun]; 3463 if (lstate != NULL) { 3464 ahc_queue_lstate_event(ahc, lstate, 3465 devinfo->our_scsiid, 3466 ahc->msgin_buf[0], 3467 /*arg*/tag); 3468 ahc_send_lstate_events(ahc, lstate); 3469 } 3470 } 3471 ahc_restart(ahc); 3472 done = MSGLOOP_TERMINATED; 3473 break; 3474 } 3475#endif 3476 case MSG_TERM_IO_PROC: 3477 default: 3478 reject = TRUE; 3479 break; 3480 } 3481 3482 if (reject) { 3483 /* 3484 * Setup to reject the message. 3485 */ 3486 ahc->msgout_index = 0; 3487 ahc->msgout_len = 1; 3488 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3489 done = MSGLOOP_MSGCOMPLETE; 3490 response = TRUE; 3491 } 3492 3493 if (done != MSGLOOP_IN_PROG && !response) 3494 /* Clear the outgoing message buffer */ 3495 ahc->msgout_len = 0; 3496 3497 return (done); 3498} 3499 3500/* 3501 * Process a message reject message. 3502 */ 3503static int 3504ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3505{ 3506 /* 3507 * What we care about here is if we had an 3508 * outstanding SDTR or WDTR message for this 3509 * target. If we did, this is a signal that 3510 * the target is refusing negotiation. 3511 */ 3512 struct scb *scb; 3513 struct ahc_initiator_tinfo *tinfo; 3514 struct ahc_tmode_tstate *tstate; 3515 u_int scb_index; 3516 u_int last_msg; 3517 int response = 0; 3518 3519 scb_index = ahc_inb(ahc, SCB_TAG); 3520 scb = ahc_lookup_scb(ahc, scb_index); 3521 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 3522 devinfo->our_scsiid, 3523 devinfo->target, &tstate); 3524 /* Might be necessary */ 3525 last_msg = ahc_inb(ahc, LAST_MSG); 3526 3527 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 3528 /* 3529 * Target does not support the PPR message. 3530 * Attempt to negotiate SPI-2 style. 3531 */ 3532 if (bootverbose) { 3533 printf("(%s:%c:%d:%d): PPR Rejected. " 3534 "Trying WDTR/SDTR\n", 3535 ahc_name(ahc), devinfo->channel, 3536 devinfo->target, devinfo->lun); 3537 } 3538 tinfo->goal.ppr_options = 0; 3539 tinfo->curr.transport_version = 2; 3540 tinfo->goal.transport_version = 2; 3541 ahc->msgout_index = 0; 3542 ahc->msgout_len = 0; 3543 ahc_build_transfer_msg(ahc, devinfo); 3544 ahc->msgout_index = 0; 3545 response = 1; 3546 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 3547 3548 /* note 8bit xfers */ 3549 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 3550 "8bit transfers\n", ahc_name(ahc), 3551 devinfo->channel, devinfo->target, devinfo->lun); 3552 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3553 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3554 /*paused*/TRUE); 3555 /* 3556 * No need to clear the sync rate. If the target 3557 * did not accept the command, our syncrate is 3558 * unaffected. If the target started the negotiation, 3559 * but rejected our response, we already cleared the 3560 * sync rate before sending our WDTR. 3561 */ 3562 if (tinfo->goal.offset != tinfo->curr.offset) { 3563 3564 /* Start the sync negotiation */ 3565 ahc->msgout_index = 0; 3566 ahc->msgout_len = 0; 3567 ahc_build_transfer_msg(ahc, devinfo); 3568 ahc->msgout_index = 0; 3569 response = 1; 3570 } 3571 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 3572 /* note asynch xfers and clear flag */ 3573 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 3574 /*offset*/0, /*ppr_options*/0, 3575 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3576 /*paused*/TRUE); 3577 printf("(%s:%c:%d:%d): refuses synchronous negotiation. " 3578 "Using asynchronous transfers\n", 3579 ahc_name(ahc), devinfo->channel, 3580 devinfo->target, devinfo->lun); 3581 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 3582 int tag_type; 3583 int mask; 3584 3585 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 3586 3587 if (tag_type == MSG_SIMPLE_TASK) { 3588 printf("(%s:%c:%d:%d): refuses tagged commands. " 3589 "Performing non-tagged I/O\n", ahc_name(ahc), 3590 devinfo->channel, devinfo->target, devinfo->lun); 3591 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE); 3592 mask = ~0x23; 3593 } else { 3594 printf("(%s:%c:%d:%d): refuses %s tagged commands. " 3595 "Performing simple queue tagged I/O only\n", 3596 ahc_name(ahc), devinfo->channel, devinfo->target, 3597 devinfo->lun, tag_type == MSG_ORDERED_TASK 3598 ? "ordered" : "head of queue"); 3599 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC); 3600 mask = ~0x03; 3601 } 3602 3603 /* 3604 * Resend the identify for this CCB as the target 3605 * may believe that the selection is invalid otherwise. 3606 */ 3607 ahc_outb(ahc, SCB_CONTROL, 3608 ahc_inb(ahc, SCB_CONTROL) & mask); 3609 scb->hscb->control &= mask; 3610 aic_set_transaction_tag(scb, /*enabled*/FALSE, 3611 /*type*/MSG_SIMPLE_TASK); 3612 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 3613 ahc_assert_atn(ahc); 3614 3615 /* 3616 * This transaction is now at the head of 3617 * the untagged queue for this target. 3618 */ 3619 if ((ahc->flags & AHC_SCB_BTT) == 0) { 3620 struct scb_tailq *untagged_q; 3621 3622 untagged_q = 3623 &(ahc->untagged_queues[devinfo->target_offset]); 3624 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe); 3625 scb->flags |= SCB_UNTAGGEDQ; 3626 } 3627 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 3628 scb->hscb->tag); 3629 3630 /* 3631 * Requeue all tagged commands for this target 3632 * currently in our possession so they can be 3633 * converted to untagged commands. 3634 */ 3635 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 3636 SCB_GET_CHANNEL(ahc, scb), 3637 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 3638 ROLE_INITIATOR, CAM_REQUEUE_REQ, 3639 SEARCH_COMPLETE); 3640 } else { 3641 /* 3642 * Otherwise, we ignore it. 3643 */ 3644 printf("%s:%c:%d: Message reject for %x -- ignored\n", 3645 ahc_name(ahc), devinfo->channel, devinfo->target, 3646 last_msg); 3647 } 3648 return (response); 3649} 3650 3651/* 3652 * Process an ingnore wide residue message. 3653 */ 3654static void 3655ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3656{ 3657 u_int scb_index; 3658 struct scb *scb; 3659 3660 scb_index = ahc_inb(ahc, SCB_TAG); 3661 scb = ahc_lookup_scb(ahc, scb_index); 3662 /* 3663 * XXX Actually check data direction in the sequencer? 3664 * Perhaps add datadir to some spare bits in the hscb? 3665 */ 3666 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3667 || aic_get_transfer_dir(scb) != CAM_DIR_IN) { 3668 /* 3669 * Ignore the message if we haven't 3670 * seen an appropriate data phase yet. 3671 */ 3672 } else { 3673 /* 3674 * If the residual occurred on the last 3675 * transfer and the transfer request was 3676 * expected to end on an odd count, do 3677 * nothing. Otherwise, subtract a byte 3678 * and update the residual count accordingly. 3679 */ 3680 uint32_t sgptr; 3681 3682 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3683 if ((sgptr & SG_LIST_NULL) != 0 3684 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) { 3685 /* 3686 * If the residual occurred on the last 3687 * transfer and the transfer request was 3688 * expected to end on an odd count, do 3689 * nothing. 3690 */ 3691 } else { 3692 struct ahc_dma_seg *sg; 3693 uint32_t data_cnt; 3694 uint32_t data_addr; 3695 uint32_t sglen; 3696 3697 /* Pull in all of the sgptr */ 3698 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR); 3699 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT); 3700 3701 if ((sgptr & SG_LIST_NULL) != 0) { 3702 /* 3703 * The residual data count is not updated 3704 * for the command run to completion case. 3705 * Explicitly zero the count. 3706 */ 3707 data_cnt &= ~AHC_SG_LEN_MASK; 3708 } 3709 3710 data_addr = ahc_inl(ahc, SHADDR); 3711 3712 data_cnt += 1; 3713 data_addr -= 1; 3714 sgptr &= SG_PTR_MASK; 3715 3716 sg = ahc_sg_bus_to_virt(scb, sgptr); 3717 3718 /* 3719 * The residual sg ptr points to the next S/G 3720 * to load so we must go back one. 3721 */ 3722 sg--; 3723 sglen = aic_le32toh(sg->len) & AHC_SG_LEN_MASK; 3724 if (sg != scb->sg_list 3725 && sglen < (data_cnt & AHC_SG_LEN_MASK)) { 3726 3727 sg--; 3728 sglen = aic_le32toh(sg->len); 3729 /* 3730 * Preserve High Address and SG_LIST bits 3731 * while setting the count to 1. 3732 */ 3733 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK)); 3734 data_addr = aic_le32toh(sg->addr) 3735 + (sglen & AHC_SG_LEN_MASK) - 1; 3736 3737 /* 3738 * Increment sg so it points to the 3739 * "next" sg. 3740 */ 3741 sg++; 3742 sgptr = ahc_sg_virt_to_bus(scb, sg); 3743 } 3744 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr); 3745 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt); 3746 /* 3747 * Toggle the "oddness" of the transfer length 3748 * to handle this mid-transfer ignore wide 3749 * residue. This ensures that the oddness is 3750 * correct for subsequent data transfers. 3751 */ 3752 ahc_outb(ahc, SCB_LUN, 3753 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD); 3754 } 3755 } 3756} 3757 3758 3759/* 3760 * Reinitialize the data pointers for the active transfer 3761 * based on its current residual. 3762 */ 3763static void 3764ahc_reinitialize_dataptrs(struct ahc_softc *ahc) 3765{ 3766 struct scb *scb; 3767 struct ahc_dma_seg *sg; 3768 u_int scb_index; 3769 uint32_t sgptr; 3770 uint32_t resid; 3771 uint32_t dataptr; 3772 3773 scb_index = ahc_inb(ahc, SCB_TAG); 3774 scb = ahc_lookup_scb(ahc, scb_index); 3775 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) 3776 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) 3777 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8) 3778 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3779 3780 sgptr &= SG_PTR_MASK; 3781 sg = ahc_sg_bus_to_virt(scb, sgptr); 3782 3783 /* The residual sg_ptr always points to the next sg */ 3784 sg--; 3785 3786 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16) 3787 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8) 3788 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT); 3789 3790 dataptr = aic_le32toh(sg->addr) 3791 + (aic_le32toh(sg->len) & AHC_SG_LEN_MASK) 3792 - resid; 3793 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 3794 u_int dscommand1; 3795 3796 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 3797 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 3798 ahc_outb(ahc, HADDR, 3799 (aic_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS); 3800 ahc_outb(ahc, DSCOMMAND1, dscommand1); 3801 } 3802 ahc_outb(ahc, HADDR + 3, dataptr >> 24); 3803 ahc_outb(ahc, HADDR + 2, dataptr >> 16); 3804 ahc_outb(ahc, HADDR + 1, dataptr >> 8); 3805 ahc_outb(ahc, HADDR, dataptr); 3806 ahc_outb(ahc, HCNT + 2, resid >> 16); 3807 ahc_outb(ahc, HCNT + 1, resid >> 8); 3808 ahc_outb(ahc, HCNT, resid); 3809 if ((ahc->features & AHC_ULTRA2) == 0) { 3810 ahc_outb(ahc, STCNT + 2, resid >> 16); 3811 ahc_outb(ahc, STCNT + 1, resid >> 8); 3812 ahc_outb(ahc, STCNT, resid); 3813 } 3814} 3815 3816/* 3817 * Handle the effects of issuing a bus device reset message. 3818 */ 3819static void 3820ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3821 cam_status status, char *message, int verbose_level) 3822{ 3823#ifdef AHC_TARGET_MODE 3824 struct ahc_tmode_tstate* tstate; 3825 u_int lun; 3826#endif 3827 int found; 3828 3829 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3830 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3831 status); 3832 3833#ifdef AHC_TARGET_MODE 3834 /* 3835 * Send an immediate notify ccb to all target mord peripheral 3836 * drivers affected by this action. 3837 */ 3838 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3839 if (tstate != NULL) { 3840 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 3841 struct ahc_tmode_lstate* lstate; 3842 3843 lstate = tstate->enabled_luns[lun]; 3844 if (lstate == NULL) 3845 continue; 3846 3847 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid, 3848 MSG_BUS_DEV_RESET, /*arg*/0); 3849 ahc_send_lstate_events(ahc, lstate); 3850 } 3851 } 3852#endif 3853 3854 /* 3855 * Go back to async/narrow transfers and renegotiate. 3856 */ 3857 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3858 AHC_TRANS_CUR, /*paused*/TRUE); 3859 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3860 /*period*/0, /*offset*/0, /*ppr_options*/0, 3861 AHC_TRANS_CUR, /*paused*/TRUE); 3862 3863 if (status != CAM_SEL_TIMEOUT) 3864 ahc_send_async(ahc, devinfo->channel, devinfo->target, 3865 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL); 3866 3867 if (message != NULL 3868 && (verbose_level <= bootverbose)) 3869 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3870 message, devinfo->channel, devinfo->target, found); 3871} 3872 3873#ifdef AHC_TARGET_MODE 3874static void 3875ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3876 struct scb *scb) 3877{ 3878 3879 /* 3880 * To facilitate adding multiple messages together, 3881 * each routine should increment the index and len 3882 * variables instead of setting them explicitly. 3883 */ 3884 ahc->msgout_index = 0; 3885 ahc->msgout_len = 0; 3886 3887 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 3888 ahc_build_transfer_msg(ahc, devinfo); 3889 else 3890 panic("ahc_intr: AWAITING target message with no message"); 3891 3892 ahc->msgout_index = 0; 3893 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 3894} 3895#endif 3896/**************************** Initialization **********************************/ 3897/* 3898 * Allocate a controller structure for a new device 3899 * and perform initial initializion. 3900 */ 3901struct ahc_softc * 3902ahc_alloc(void *platform_arg, char *name) 3903{ 3904 struct ahc_softc *ahc; 3905 int i; 3906 3907#ifndef __FreeBSD__ 3908 ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT); 3909 if (!ahc) { 3910 printf("aic7xxx: cannot malloc softc!\n"); 3911 free(name, M_DEVBUF); 3912 return NULL; 3913 } 3914#else 3915 ahc = device_get_softc((device_t)platform_arg); 3916#endif 3917 memset(ahc, 0, sizeof(*ahc)); 3918 ahc->seep_config = malloc(sizeof(*ahc->seep_config), 3919 M_DEVBUF, M_NOWAIT); 3920 if (ahc->seep_config == NULL) { 3921#ifndef __FreeBSD__ 3922 free(ahc, M_DEVBUF); 3923#endif 3924 free(name, M_DEVBUF); 3925 return (NULL); 3926 } 3927 LIST_INIT(&ahc->pending_scbs); 3928 LIST_INIT(&ahc->timedout_scbs); 3929 /* We don't know our unit number until the OSM sets it */ 3930 ahc->name = name; 3931 ahc->unit = -1; 3932 ahc->description = NULL; 3933 ahc->channel = 'A'; 3934 ahc->channel_b = 'B'; 3935 ahc->chip = AHC_NONE; 3936 ahc->features = AHC_FENONE; 3937 ahc->bugs = AHC_BUGNONE; 3938 ahc->flags = AHC_FNONE; 3939 /* 3940 * Default to all error reporting enabled with the 3941 * sequencer operating at its fastest speed. 3942 * The bus attach code may modify this. 3943 */ 3944 ahc->seqctl = FASTMODE; 3945 3946 for (i = 0; i < AHC_NUM_TARGETS; i++) 3947 TAILQ_INIT(&ahc->untagged_queues[i]); 3948 if (ahc_platform_alloc(ahc, platform_arg) != 0) { 3949 ahc_free(ahc); 3950 ahc = NULL; 3951 } 3952 ahc_lockinit(ahc); 3953 return (ahc); 3954} 3955 3956int 3957ahc_softc_init(struct ahc_softc *ahc) 3958{ 3959 3960 /* The IRQMS bit is only valid on VL and EISA chips */ 3961 if ((ahc->chip & AHC_PCI) == 0) 3962 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS; 3963 else 3964 ahc->unpause = 0; 3965 ahc->pause = ahc->unpause | PAUSE; 3966 /* XXX The shared scb data stuff should be deprecated */ 3967 if (ahc->scb_data == NULL) { 3968 ahc->scb_data = malloc(sizeof(*ahc->scb_data), 3969 M_DEVBUF, M_NOWAIT); 3970 if (ahc->scb_data == NULL) 3971 return (ENOMEM); 3972 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data)); 3973 } 3974 3975 return (0); 3976} 3977 3978void 3979ahc_softc_insert(struct ahc_softc *ahc) 3980{ 3981 struct ahc_softc *list_ahc; 3982 3983#if AIC_PCI_CONFIG > 0 3984 /* 3985 * Second Function PCI devices need to inherit some 3986 * settings from function 0. 3987 */ 3988 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI 3989 && (ahc->features & AHC_MULTI_FUNC) != 0) { 3990 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { 3991 aic_dev_softc_t list_pci; 3992 aic_dev_softc_t pci; 3993 3994 list_pci = list_ahc->dev_softc; 3995 pci = ahc->dev_softc; 3996 if (aic_get_pci_slot(list_pci) == aic_get_pci_slot(pci) 3997 && aic_get_pci_bus(list_pci) == aic_get_pci_bus(pci)) { 3998 struct ahc_softc *master; 3999 struct ahc_softc *slave; 4000 4001 if (aic_get_pci_function(list_pci) == 0) { 4002 master = list_ahc; 4003 slave = ahc; 4004 } else { 4005 master = ahc; 4006 slave = list_ahc; 4007 } 4008 slave->flags &= ~AHC_BIOS_ENABLED; 4009 slave->flags |= 4010 master->flags & AHC_BIOS_ENABLED; 4011 slave->flags &= ~AHC_PRIMARY_CHANNEL; 4012 slave->flags |= 4013 master->flags & AHC_PRIMARY_CHANNEL; 4014 break; 4015 } 4016 } 4017 } 4018#endif 4019 4020 /* 4021 * Insertion sort into our list of softcs. 4022 */ 4023 list_ahc = TAILQ_FIRST(&ahc_tailq); 4024 while (list_ahc != NULL 4025 && ahc_softc_comp(ahc, list_ahc) <= 0) 4026 list_ahc = TAILQ_NEXT(list_ahc, links); 4027 if (list_ahc != NULL) 4028 TAILQ_INSERT_BEFORE(list_ahc, ahc, links); 4029 else 4030 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links); 4031 ahc->init_level++; 4032} 4033 4034void 4035ahc_set_unit(struct ahc_softc *ahc, int unit) 4036{ 4037 ahc->unit = unit; 4038} 4039 4040void 4041ahc_set_name(struct ahc_softc *ahc, char *name) 4042{ 4043 if (ahc->name != NULL) 4044 free(ahc->name, M_DEVBUF); 4045 ahc->name = name; 4046} 4047 4048void 4049ahc_free(struct ahc_softc *ahc) 4050{ 4051 int i; 4052 4053 ahc_terminate_recovery_thread(ahc); 4054 switch (ahc->init_level) { 4055 default: 4056 case 5: 4057 ahc_shutdown(ahc); 4058 /* FALLTHROUGH */ 4059 case 4: 4060 aic_dmamap_unload(ahc, ahc->shared_data_dmat, 4061 ahc->shared_data_dmamap); 4062 /* FALLTHROUGH */ 4063 case 3: 4064 aic_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo, 4065 ahc->shared_data_dmamap); 4066 /* FALLTHROUGH */ 4067 case 2: 4068 aic_dma_tag_destroy(ahc, ahc->shared_data_dmat); 4069 case 1: 4070#ifndef __linux__ 4071 aic_dma_tag_destroy(ahc, ahc->buffer_dmat); 4072#endif 4073 break; 4074 case 0: 4075 break; 4076 } 4077 4078#ifndef __linux__ 4079 aic_dma_tag_destroy(ahc, ahc->parent_dmat); 4080#endif 4081 ahc_platform_free(ahc); 4082 ahc_fini_scbdata(ahc); 4083 for (i = 0; i < AHC_NUM_TARGETS; i++) { 4084 struct ahc_tmode_tstate *tstate; 4085 4086 tstate = ahc->enabled_targets[i]; 4087 if (tstate != NULL) { 4088#ifdef AHC_TARGET_MODE 4089 int j; 4090 4091 for (j = 0; j < AHC_NUM_LUNS; j++) { 4092 struct ahc_tmode_lstate *lstate; 4093 4094 lstate = tstate->enabled_luns[j]; 4095 if (lstate != NULL) { 4096 xpt_free_path(lstate->path); 4097 free(lstate, M_DEVBUF); 4098 } 4099 } 4100#endif 4101 free(tstate, M_DEVBUF); 4102 } 4103 } 4104#ifdef AHC_TARGET_MODE 4105 if (ahc->black_hole != NULL) { 4106 xpt_free_path(ahc->black_hole->path); 4107 free(ahc->black_hole, M_DEVBUF); 4108 } 4109#endif 4110 if (ahc->name != NULL) 4111 free(ahc->name, M_DEVBUF); 4112 if (ahc->seep_config != NULL) 4113 free(ahc->seep_config, M_DEVBUF); 4114#ifndef __FreeBSD__ 4115 free(ahc, M_DEVBUF); 4116#endif 4117 return; 4118} 4119 4120void 4121ahc_shutdown(void *arg) 4122{ 4123 struct ahc_softc *ahc; 4124 int i; 4125 4126 ahc = (struct ahc_softc *)arg; 4127 4128 /* This will reset most registers to 0, but not all */ 4129 ahc_reset(ahc, /*reinit*/FALSE); 4130 ahc_outb(ahc, SCSISEQ, 0); 4131 ahc_outb(ahc, SXFRCTL0, 0); 4132 ahc_outb(ahc, DSPCISTATUS, 0); 4133 4134 for (i = TARG_SCSIRATE; i < SCSICONF; i++) 4135 ahc_outb(ahc, i, 0); 4136} 4137 4138/* 4139 * Reset the controller and record some information about it 4140 * that is only available just after a reset. If "reinit" is 4141 * non-zero, this reset occurred after initial configuration 4142 * and the caller requests that the chip be fully reinitialized 4143 * to a runable state. Chip interrupts are *not* enabled after 4144 * a reinitialization. The caller must enable interrupts via 4145 * ahc_intr_enable(). 4146 */ 4147int 4148ahc_reset(struct ahc_softc *ahc, int reinit) 4149{ 4150 u_int sblkctl; 4151 u_int sxfrctl1_a, sxfrctl1_b; 4152 int error; 4153 int wait; 4154 4155 /* 4156 * Preserve the value of the SXFRCTL1 register for all channels. 4157 * It contains settings that affect termination and we don't want 4158 * to disturb the integrity of the bus. 4159 */ 4160 ahc_pause(ahc); 4161 sxfrctl1_b = 0; 4162 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) { 4163 u_int sblkctl; 4164 4165 /* 4166 * Save channel B's settings in case this chip 4167 * is setup for TWIN channel operation. 4168 */ 4169 sblkctl = ahc_inb(ahc, SBLKCTL); 4170 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4171 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 4172 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4173 } 4174 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 4175 4176 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 4177 4178 /* 4179 * Ensure that the reset has finished. We delay 1000us 4180 * prior to reading the register to make sure the chip 4181 * has sufficiently completed its reset to handle register 4182 * accesses. 4183 */ 4184 wait = 1000; 4185 do { 4186 aic_delay(1000); 4187 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 4188 4189 if (wait == 0) { 4190 printf("%s: WARNING - Failed chip reset! " 4191 "Trying to initialize anyway.\n", ahc_name(ahc)); 4192 } 4193 ahc_outb(ahc, HCNTRL, ahc->pause); 4194 4195 /* Determine channel configuration */ 4196 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 4197 /* No Twin Channel PCI cards */ 4198 if ((ahc->chip & AHC_PCI) != 0) 4199 sblkctl &= ~SELBUSB; 4200 switch (sblkctl) { 4201 case 0: 4202 /* Single Narrow Channel */ 4203 break; 4204 case 2: 4205 /* Wide Channel */ 4206 ahc->features |= AHC_WIDE; 4207 break; 4208 case 8: 4209 /* Twin Channel */ 4210 ahc->features |= AHC_TWIN; 4211 break; 4212 default: 4213 printf(" Unsupported adapter type. Ignoring\n"); 4214 return(-1); 4215 } 4216 4217 /* 4218 * Reload sxfrctl1. 4219 * 4220 * We must always initialize STPWEN to 1 before we 4221 * restore the saved values. STPWEN is initialized 4222 * to a tri-state condition which can only be cleared 4223 * by turning it on. 4224 */ 4225 if ((ahc->features & AHC_TWIN) != 0) { 4226 u_int sblkctl; 4227 4228 sblkctl = ahc_inb(ahc, SBLKCTL); 4229 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4230 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 4231 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4232 } 4233 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 4234 4235 error = 0; 4236 if (reinit != 0) 4237 /* 4238 * If a recovery action has forced a chip reset, 4239 * re-initialize the chip to our liking. 4240 */ 4241 error = ahc->bus_chip_init(ahc); 4242#ifdef AHC_DUMP_SEQ 4243 else 4244 ahc_dumpseq(ahc); 4245#endif 4246 4247 return (error); 4248} 4249 4250/* 4251 * Determine the number of SCBs available on the controller 4252 */ 4253int 4254ahc_probe_scbs(struct ahc_softc *ahc) { 4255 int i; 4256 4257 for (i = 0; i < AHC_SCB_MAX; i++) { 4258 4259 ahc_outb(ahc, SCBPTR, i); 4260 ahc_outb(ahc, SCB_BASE, i); 4261 if (ahc_inb(ahc, SCB_BASE) != i) 4262 break; 4263 ahc_outb(ahc, SCBPTR, 0); 4264 if (ahc_inb(ahc, SCB_BASE) != 0) 4265 break; 4266 } 4267 return (i); 4268} 4269 4270static void 4271ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4272{ 4273 bus_addr_t *baddr; 4274 4275 baddr = (bus_addr_t *)arg; 4276 *baddr = segs->ds_addr; 4277} 4278 4279static void 4280ahc_build_free_scb_list(struct ahc_softc *ahc) 4281{ 4282 int scbsize; 4283 int i; 4284 4285 scbsize = 32; 4286 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0) 4287 scbsize = 64; 4288 4289 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 4290 int j; 4291 4292 ahc_outb(ahc, SCBPTR, i); 4293 4294 /* 4295 * Touch all SCB bytes to avoid parity errors 4296 * should one of our debugging routines read 4297 * an otherwise uninitiatlized byte. 4298 */ 4299 for (j = 0; j < scbsize; j++) 4300 ahc_outb(ahc, SCB_BASE+j, 0xFF); 4301 4302 /* Clear the control byte. */ 4303 ahc_outb(ahc, SCB_CONTROL, 0); 4304 4305 /* Set the next pointer */ 4306 if ((ahc->flags & AHC_PAGESCBS) != 0) 4307 ahc_outb(ahc, SCB_NEXT, i+1); 4308 else 4309 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4310 4311 /* Make the tag number, SCSIID, and lun invalid */ 4312 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 4313 ahc_outb(ahc, SCB_SCSIID, 0xFF); 4314 ahc_outb(ahc, SCB_LUN, 0xFF); 4315 } 4316 4317 if ((ahc->flags & AHC_PAGESCBS) != 0) { 4318 /* SCB 0 heads the free list. */ 4319 ahc_outb(ahc, FREE_SCBH, 0); 4320 } else { 4321 /* No free list. */ 4322 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 4323 } 4324 4325 /* Make sure that the last SCB terminates the free list */ 4326 ahc_outb(ahc, SCBPTR, i-1); 4327 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4328} 4329 4330static int 4331ahc_init_scbdata(struct ahc_softc *ahc) 4332{ 4333 struct scb_data *scb_data; 4334 4335 scb_data = ahc->scb_data; 4336 SLIST_INIT(&scb_data->free_scbs); 4337 SLIST_INIT(&scb_data->sg_maps); 4338 4339 /* Allocate SCB resources */ 4340 scb_data->scbarray = 4341 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC, 4342 M_DEVBUF, M_NOWAIT); 4343 if (scb_data->scbarray == NULL) 4344 return (ENOMEM); 4345 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC); 4346 4347 /* Determine the number of hardware SCBs and initialize them */ 4348 4349 scb_data->maxhscbs = ahc_probe_scbs(ahc); 4350 if (ahc->scb_data->maxhscbs == 0) { 4351 printf("%s: No SCB space found\n", ahc_name(ahc)); 4352 return (ENXIO); 4353 } 4354 4355 /* 4356 * Create our DMA tags. These tags define the kinds of device 4357 * accessible memory allocations and memory mappings we will 4358 * need to perform during normal operation. 4359 * 4360 * Unless we need to further restrict the allocation, we rely 4361 * on the restrictions of the parent dmat, hence the common 4362 * use of MAXADDR and MAXSIZE. 4363 */ 4364 4365 /* DMA tag for our hardware scb structures */ 4366 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4367 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4368 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4369 /*highaddr*/BUS_SPACE_MAXADDR, 4370 /*filter*/NULL, /*filterarg*/NULL, 4371 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb), 4372 /*nsegments*/1, 4373 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4374 /*flags*/0, &scb_data->hscb_dmat) != 0) { 4375 goto error_exit; 4376 } 4377 4378 scb_data->init_level++; 4379 4380 /* Allocation for our hscbs */ 4381 if (aic_dmamem_alloc(ahc, scb_data->hscb_dmat, 4382 (void **)&scb_data->hscbs, 4383 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 4384 &scb_data->hscb_dmamap) != 0) { 4385 goto error_exit; 4386 } 4387 4388 scb_data->init_level++; 4389 4390 /* And permanently map them */ 4391 aic_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap, 4392 scb_data->hscbs, 4393 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb), 4394 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0); 4395 4396 scb_data->init_level++; 4397 4398 /* DMA tag for our sense buffers */ 4399 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4400 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4401 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4402 /*highaddr*/BUS_SPACE_MAXADDR, 4403 /*filter*/NULL, /*filterarg*/NULL, 4404 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data), 4405 /*nsegments*/1, 4406 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4407 /*flags*/0, &scb_data->sense_dmat) != 0) { 4408 goto error_exit; 4409 } 4410 4411 scb_data->init_level++; 4412 4413 /* Allocate them */ 4414 if (aic_dmamem_alloc(ahc, scb_data->sense_dmat, 4415 (void **)&scb_data->sense, 4416 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) { 4417 goto error_exit; 4418 } 4419 4420 scb_data->init_level++; 4421 4422 /* And permanently map them */ 4423 aic_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap, 4424 scb_data->sense, 4425 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data), 4426 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0); 4427 4428 scb_data->init_level++; 4429 4430 /* DMA tag for our S/G structures. We allocate in page sized chunks */ 4431 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8, 4432 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4433 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4434 /*highaddr*/BUS_SPACE_MAXADDR, 4435 /*filter*/NULL, /*filterarg*/NULL, 4436 PAGE_SIZE, /*nsegments*/1, 4437 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4438 /*flags*/0, &scb_data->sg_dmat) != 0) { 4439 goto error_exit; 4440 } 4441 4442 scb_data->init_level++; 4443 4444 /* Perform initial CCB allocation */ 4445 memset(scb_data->hscbs, 0, 4446 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb)); 4447 while (ahc_alloc_scbs(ahc) != 0) 4448 ; 4449 4450 if (scb_data->numscbs == 0) { 4451 printf("%s: ahc_init_scbdata - " 4452 "Unable to allocate initial scbs\n", 4453 ahc_name(ahc)); 4454 goto error_exit; 4455 } 4456 4457 /* 4458 * Reserve the next queued SCB. 4459 */ 4460 ahc->next_queued_scb = ahc_get_scb(ahc); 4461 4462 /* 4463 * Note that we were successful 4464 */ 4465 return (0); 4466 4467error_exit: 4468 4469 return (ENOMEM); 4470} 4471 4472static void 4473ahc_fini_scbdata(struct ahc_softc *ahc) 4474{ 4475 struct scb_data *scb_data; 4476 4477 scb_data = ahc->scb_data; 4478 if (scb_data == NULL) 4479 return; 4480 4481 switch (scb_data->init_level) { 4482 default: 4483 case 7: 4484 { 4485 struct sg_map_node *sg_map; 4486 4487 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 4488 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 4489 aic_dmamap_unload(ahc, scb_data->sg_dmat, 4490 sg_map->sg_dmamap); 4491 aic_dmamem_free(ahc, scb_data->sg_dmat, 4492 sg_map->sg_vaddr, 4493 sg_map->sg_dmamap); 4494 free(sg_map, M_DEVBUF); 4495 } 4496 aic_dma_tag_destroy(ahc, scb_data->sg_dmat); 4497 } 4498 case 6: 4499 aic_dmamap_unload(ahc, scb_data->sense_dmat, 4500 scb_data->sense_dmamap); 4501 case 5: 4502 aic_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense, 4503 scb_data->sense_dmamap); 4504 case 4: 4505 aic_dma_tag_destroy(ahc, scb_data->sense_dmat); 4506 case 3: 4507 aic_dmamap_unload(ahc, scb_data->hscb_dmat, 4508 scb_data->hscb_dmamap); 4509 case 2: 4510 aic_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs, 4511 scb_data->hscb_dmamap); 4512 case 1: 4513 aic_dma_tag_destroy(ahc, scb_data->hscb_dmat); 4514 break; 4515 case 0: 4516 break; 4517 } 4518 if (scb_data->scbarray != NULL) 4519 free(scb_data->scbarray, M_DEVBUF); 4520} 4521 4522int 4523ahc_alloc_scbs(struct ahc_softc *ahc) 4524{ 4525 struct scb_data *scb_data; 4526 struct scb *next_scb; 4527 struct sg_map_node *sg_map; 4528 bus_addr_t physaddr; 4529 struct ahc_dma_seg *segs; 4530 int newcount; 4531 int i; 4532 4533 scb_data = ahc->scb_data; 4534 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC) 4535 /* Can't allocate any more */ 4536 return (0); 4537 4538 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4539 4540 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4541 4542 if (sg_map == NULL) 4543 return (0); 4544 4545 /* Allocate S/G space for the next batch of SCBS */ 4546 if (aic_dmamem_alloc(ahc, scb_data->sg_dmat, 4547 (void **)&sg_map->sg_vaddr, 4548 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 4549 &sg_map->sg_dmamap) != 0) { 4550 free(sg_map, M_DEVBUF); 4551 return (0); 4552 } 4553 4554 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4555 4556 aic_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap, 4557 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb, 4558 &sg_map->sg_physaddr, /*flags*/0); 4559 4560 segs = sg_map->sg_vaddr; 4561 physaddr = sg_map->sg_physaddr; 4562 4563 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4564 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs)); 4565 for (i = 0; i < newcount; i++) { 4566 struct scb_platform_data *pdata; 4567#ifndef __linux__ 4568 int error; 4569#endif 4570 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 4571 M_DEVBUF, M_NOWAIT); 4572 if (pdata == NULL) 4573 break; 4574 next_scb->platform_data = pdata; 4575 next_scb->sg_map = sg_map; 4576 next_scb->sg_list = segs; 4577 /* 4578 * The sequencer always starts with the second entry. 4579 * The first entry is embedded in the scb. 4580 */ 4581 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4582 next_scb->ahc_softc = ahc; 4583 next_scb->flags = SCB_FLAG_NONE; 4584#ifndef __linux__ 4585 error = aic_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0, 4586 &next_scb->dmamap); 4587 if (error != 0) 4588 break; 4589#endif 4590 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4591 next_scb->hscb->tag = ahc->scb_data->numscbs; 4592 aic_timer_init(&next_scb->io_timer); 4593 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, 4594 next_scb, links.sle); 4595 segs += AHC_NSEG; 4596 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4597 next_scb++; 4598 ahc->scb_data->numscbs++; 4599 } 4600 return (i); 4601} 4602 4603void 4604ahc_controller_info(struct ahc_softc *ahc, char *buf) 4605{ 4606 int len; 4607 4608 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 4609 buf += len; 4610 if ((ahc->features & AHC_TWIN) != 0) 4611 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, " 4612 "B SCSI Id=%d, primary %c, ", 4613 ahc->our_id, ahc->our_id_b, 4614 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A'); 4615 else { 4616 const char *speed; 4617 const char *type; 4618 4619 speed = ""; 4620 if ((ahc->features & AHC_ULTRA) != 0) { 4621 speed = "Ultra "; 4622 } else if ((ahc->features & AHC_DT) != 0) { 4623 speed = "Ultra160 "; 4624 } else if ((ahc->features & AHC_ULTRA2) != 0) { 4625 speed = "Ultra2 "; 4626 } 4627 if ((ahc->features & AHC_WIDE) != 0) { 4628 type = "Wide"; 4629 } else { 4630 type = "Single"; 4631 } 4632 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ", 4633 speed, type, ahc->channel, ahc->our_id); 4634 } 4635 buf += len; 4636 4637 if ((ahc->flags & AHC_PAGESCBS) != 0) 4638 sprintf(buf, "%d/%d SCBs", 4639 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE); 4640 else 4641 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs); 4642} 4643 4644int 4645ahc_chip_init(struct ahc_softc *ahc) 4646{ 4647 int term; 4648 int error; 4649 u_int i; 4650 u_int scsi_conf; 4651 u_int scsiseq_template; 4652 uint32_t physaddr; 4653 4654 ahc_outb(ahc, SEQ_FLAGS, 0); 4655 ahc_outb(ahc, SEQ_FLAGS2, 0); 4656 4657 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 4658 if (ahc->features & AHC_TWIN) { 4659 4660 /* 4661 * Setup Channel B first. 4662 */ 4663 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 4664 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 4665 ahc_outb(ahc, SCSIID, ahc->our_id_b); 4666 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 4667 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4668 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN); 4669 if ((ahc->features & AHC_ULTRA2) != 0) 4670 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4671 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4672 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4673 4674 /* Select Channel A */ 4675 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 4676 } 4677 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 4678 if ((ahc->features & AHC_ULTRA2) != 0) 4679 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 4680 else 4681 ahc_outb(ahc, SCSIID, ahc->our_id); 4682 scsi_conf = ahc_inb(ahc, SCSICONF); 4683 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4684 |term|ahc->seltime 4685 |ENSTIMER|ACTNEGEN); 4686 if ((ahc->features & AHC_ULTRA2) != 0) 4687 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4688 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4689 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4690 4691 /* There are no untagged SCBs active yet. */ 4692 for (i = 0; i < 16; i++) { 4693 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0)); 4694 if ((ahc->flags & AHC_SCB_BTT) != 0) { 4695 int lun; 4696 4697 /* 4698 * The SCB based BTT allows an entry per 4699 * target and lun pair. 4700 */ 4701 for (lun = 1; lun < AHC_NUM_LUNS; lun++) 4702 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun)); 4703 } 4704 } 4705 4706 /* All of our queues are empty */ 4707 for (i = 0; i < 256; i++) 4708 ahc->qoutfifo[i] = SCB_LIST_NULL; 4709 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD); 4710 4711 for (i = 0; i < 256; i++) 4712 ahc->qinfifo[i] = SCB_LIST_NULL; 4713 4714 if ((ahc->features & AHC_MULTI_TID) != 0) { 4715 ahc_outb(ahc, TARGID, 0); 4716 ahc_outb(ahc, TARGID + 1, 0); 4717 } 4718 4719 /* 4720 * Tell the sequencer where it can find our arrays in memory. 4721 */ 4722 physaddr = ahc->scb_data->hscb_busaddr; 4723 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 4724 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 4725 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 4726 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 4727 4728 physaddr = ahc->shared_data_busaddr; 4729 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF); 4730 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF); 4731 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF); 4732 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF); 4733 4734 /* 4735 * Initialize the group code to command length table. 4736 * This overrides the values in TARG_SCSIRATE, so only 4737 * setup the table after we have processed that information. 4738 */ 4739 ahc_outb(ahc, CMDSIZE_TABLE, 5); 4740 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 4741 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 4742 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 4743 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 4744 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 4745 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 4746 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 4747 4748 if ((ahc->features & AHC_HS_MAILBOX) != 0) 4749 ahc_outb(ahc, HS_MAILBOX, 0); 4750 4751 /* Tell the sequencer of our initial queue positions */ 4752 if ((ahc->features & AHC_TARGETMODE) != 0) { 4753 ahc->tqinfifonext = 1; 4754 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1); 4755 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 4756 } 4757 ahc->qinfifonext = 0; 4758 ahc->qoutfifonext = 0; 4759 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4760 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 4761 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4762 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext); 4763 ahc_outb(ahc, SDSCB_QOFF, 0); 4764 } else { 4765 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4766 ahc_outb(ahc, QINPOS, ahc->qinfifonext); 4767 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext); 4768 } 4769 4770 /* We don't have any waiting selections */ 4771 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 4772 4773 /* Our disconnection list is empty too */ 4774 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 4775 4776 /* Message out buffer starts empty */ 4777 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 4778 4779 /* 4780 * Setup the allowed SCSI Sequences based on operational mode. 4781 * If we are a target, we'll enalbe select in operations once 4782 * we've had a lun enabled. 4783 */ 4784 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 4785 if ((ahc->flags & AHC_INITIATORROLE) != 0) 4786 scsiseq_template |= ENRSELI; 4787 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 4788 4789 /* Initialize our list of free SCBs. */ 4790 ahc_build_free_scb_list(ahc); 4791 4792 /* 4793 * Tell the sequencer which SCB will be the next one it receives. 4794 */ 4795 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 4796 4797 /* 4798 * Load the Sequencer program and Enable the adapter 4799 * in "fast" mode. 4800 */ 4801 if (bootverbose) 4802 printf("%s: Downloading Sequencer Program...", 4803 ahc_name(ahc)); 4804 4805 error = ahc_loadseq(ahc); 4806 if (error != 0) 4807 return (error); 4808 4809 if ((ahc->features & AHC_ULTRA2) != 0) { 4810 int wait; 4811 4812 /* 4813 * Wait for up to 500ms for our transceivers 4814 * to settle. If the adapter does not have 4815 * a cable attached, the transceivers may 4816 * never settle, so don't complain if we 4817 * fail here. 4818 */ 4819 for (wait = 5000; 4820 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 4821 wait--) 4822 aic_delay(100); 4823 } 4824 ahc_restart(ahc); 4825 return (0); 4826} 4827 4828/* 4829 * Start the board, ready for normal operation 4830 */ 4831int 4832ahc_init(struct ahc_softc *ahc) 4833{ 4834 int max_targ; 4835 int error; 4836 u_int i; 4837 u_int scsi_conf; 4838 u_int ultraenb; 4839 u_int discenable; 4840 u_int tagenable; 4841 size_t driver_data_size; 4842 4843#ifdef AHC_DEBUG 4844 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0) 4845 ahc->flags |= AHC_SEQUENCER_DEBUG; 4846#endif 4847 4848#ifdef AHC_PRINT_SRAM 4849 printf("Scratch Ram:"); 4850 for (i = 0x20; i < 0x5f; i++) { 4851 if (((i % 8) == 0) && (i != 0)) { 4852 printf ("\n "); 4853 } 4854 printf (" 0x%x", ahc_inb(ahc, i)); 4855 } 4856 if ((ahc->features & AHC_MORE_SRAM) != 0) { 4857 for (i = 0x70; i < 0x7f; i++) { 4858 if (((i % 8) == 0) && (i != 0)) { 4859 printf ("\n "); 4860 } 4861 printf (" 0x%x", ahc_inb(ahc, i)); 4862 } 4863 } 4864 printf ("\n"); 4865 /* 4866 * Reading uninitialized scratch ram may 4867 * generate parity errors. 4868 */ 4869 ahc_outb(ahc, CLRINT, CLRPARERR); 4870 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 4871#endif 4872 max_targ = 15; 4873 4874 /* 4875 * Assume we have a board at this stage and it has been reset. 4876 */ 4877 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 4878 ahc->our_id = ahc->our_id_b = 7; 4879 4880 /* 4881 * Default to allowing initiator operations. 4882 */ 4883 ahc->flags |= AHC_INITIATORROLE; 4884 4885 /* 4886 * Only allow target mode features if this unit has them enabled. 4887 */ 4888 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0) 4889 ahc->features &= ~AHC_TARGETMODE; 4890 4891#ifndef __linux__ 4892 /* DMA tag for mapping buffers into device visible space. */ 4893 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4894 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4895 /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING 4896 ? (bus_addr_t)0x7FFFFFFFFFULL 4897 : BUS_SPACE_MAXADDR_32BIT, 4898 /*highaddr*/BUS_SPACE_MAXADDR, 4899 /*filter*/NULL, /*filterarg*/NULL, 4900 /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE, 4901 /*nsegments*/AHC_NSEG, 4902 /*maxsegsz*/AHC_MAXTRANSFER_SIZE, 4903 /*flags*/BUS_DMA_ALLOCNOW, 4904 &ahc->buffer_dmat) != 0) { 4905 return (ENOMEM); 4906 } 4907#endif 4908 4909 ahc->init_level++; 4910 4911 /* 4912 * DMA tag for our command fifos and other data in system memory 4913 * the card's sequencer must be able to access. For initiator 4914 * roles, we need to allocate space for the qinfifo and qoutfifo. 4915 * The qinfifo and qoutfifo are composed of 256 1 byte elements. 4916 * When providing for the target mode role, we must additionally 4917 * provide space for the incoming target command fifo and an extra 4918 * byte to deal with a dma bug in some chip versions. 4919 */ 4920 driver_data_size = 2 * 256 * sizeof(uint8_t); 4921 if ((ahc->features & AHC_TARGETMODE) != 0) 4922 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd) 4923 + /*DMA WideOdd Bug Buffer*/1; 4924 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4925 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4926 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4927 /*highaddr*/BUS_SPACE_MAXADDR, 4928 /*filter*/NULL, /*filterarg*/NULL, 4929 driver_data_size, 4930 /*nsegments*/1, 4931 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4932 /*flags*/0, &ahc->shared_data_dmat) != 0) { 4933 return (ENOMEM); 4934 } 4935 4936 ahc->init_level++; 4937 4938 /* Allocation of driver data */ 4939 if (aic_dmamem_alloc(ahc, ahc->shared_data_dmat, 4940 (void **)&ahc->qoutfifo, 4941 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 4942 &ahc->shared_data_dmamap) != 0) { 4943 return (ENOMEM); 4944 } 4945 4946 ahc->init_level++; 4947 4948 /* And permanently map it in */ 4949 aic_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap, 4950 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb, 4951 &ahc->shared_data_busaddr, /*flags*/0); 4952 4953 if ((ahc->features & AHC_TARGETMODE) != 0) { 4954 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo; 4955 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS]; 4956 ahc->dma_bug_buf = ahc->shared_data_busaddr 4957 + driver_data_size - 1; 4958 /* All target command blocks start out invalid. */ 4959 for (i = 0; i < AHC_TMODE_CMDS; i++) 4960 ahc->targetcmds[i].cmd_valid = 0; 4961 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD); 4962 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256]; 4963 } 4964 ahc->qinfifo = &ahc->qoutfifo[256]; 4965 4966 ahc->init_level++; 4967 4968 /* Allocate SCB data now that buffer_dmat is initialized */ 4969 if (ahc->scb_data->maxhscbs == 0) 4970 if (ahc_init_scbdata(ahc) != 0) 4971 return (ENOMEM); 4972 4973 /* 4974 * Allocate a tstate to house information for our 4975 * initiator presence on the bus as well as the user 4976 * data for any target mode initiator. 4977 */ 4978 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 4979 printf("%s: unable to allocate ahc_tmode_tstate. " 4980 "Failing attach\n", ahc_name(ahc)); 4981 return (ENOMEM); 4982 } 4983 4984 if ((ahc->features & AHC_TWIN) != 0) { 4985 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 4986 printf("%s: unable to allocate ahc_tmode_tstate. " 4987 "Failing attach\n", ahc_name(ahc)); 4988 return (ENOMEM); 4989 } 4990 } 4991 4992 /* 4993 * Fire up a recovery thread for this controller. 4994 */ 4995 error = ahc_spawn_recovery_thread(ahc); 4996 if (error != 0) 4997 return (error); 4998 4999 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) { 5000 ahc->flags |= AHC_PAGESCBS; 5001 } else { 5002 ahc->flags &= ~AHC_PAGESCBS; 5003 } 5004 5005#ifdef AHC_DEBUG 5006 if (ahc_debug & AHC_SHOW_MISC) { 5007 printf("%s: hardware scb %u bytes; kernel scb %u bytes; " 5008 "ahc_dma %u bytes\n", 5009 ahc_name(ahc), 5010 (u_int)sizeof(struct hardware_scb), 5011 (u_int)sizeof(struct scb), 5012 (u_int)sizeof(struct ahc_dma_seg)); 5013 } 5014#endif /* AHC_DEBUG */ 5015 5016 /* 5017 * Look at the information that board initialization or 5018 * the board bios has left us. 5019 */ 5020 if (ahc->features & AHC_TWIN) { 5021 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 5022 if ((scsi_conf & RESET_SCSI) != 0 5023 && (ahc->flags & AHC_INITIATORROLE) != 0) 5024 ahc->flags |= AHC_RESET_BUS_B; 5025 } 5026 5027 scsi_conf = ahc_inb(ahc, SCSICONF); 5028 if ((scsi_conf & RESET_SCSI) != 0 5029 && (ahc->flags & AHC_INITIATORROLE) != 0) 5030 ahc->flags |= AHC_RESET_BUS_A; 5031 5032 ultraenb = 0; 5033 tagenable = ALL_TARGETS_MASK; 5034 5035 /* Grab the disconnection disable table and invert it for our needs */ 5036 if ((ahc->flags & AHC_USEDEFAULTS) != 0) { 5037 printf("%s: Host Adapter Bios disabled. Using default SCSI " 5038 "device parameters\n", ahc_name(ahc)); 5039 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 5040 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 5041 discenable = ALL_TARGETS_MASK; 5042 if ((ahc->features & AHC_ULTRA) != 0) 5043 ultraenb = ALL_TARGETS_MASK; 5044 } else { 5045 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 5046 | ahc_inb(ahc, DISC_DSB)); 5047 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 5048 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 5049 | ahc_inb(ahc, ULTRA_ENB); 5050 } 5051 5052 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 5053 max_targ = 7; 5054 5055 for (i = 0; i <= max_targ; i++) { 5056 struct ahc_initiator_tinfo *tinfo; 5057 struct ahc_tmode_tstate *tstate; 5058 u_int our_id; 5059 u_int target_id; 5060 char channel; 5061 5062 channel = 'A'; 5063 our_id = ahc->our_id; 5064 target_id = i; 5065 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 5066 channel = 'B'; 5067 our_id = ahc->our_id_b; 5068 target_id = i % 8; 5069 } 5070 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 5071 target_id, &tstate); 5072 /* Default to async narrow across the board */ 5073 memset(tinfo, 0, sizeof(*tinfo)); 5074 if (ahc->flags & AHC_USEDEFAULTS) { 5075 if ((ahc->features & AHC_WIDE) != 0) 5076 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 5077 5078 /* 5079 * These will be truncated when we determine the 5080 * connection type we have with the target. 5081 */ 5082 tinfo->user.period = ahc_syncrates->period; 5083 tinfo->user.offset = MAX_OFFSET; 5084 } else { 5085 u_int scsirate; 5086 uint16_t mask; 5087 5088 /* Take the settings leftover in scratch RAM. */ 5089 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 5090 mask = (0x01 << i); 5091 if ((ahc->features & AHC_ULTRA2) != 0) { 5092 u_int offset; 5093 u_int maxsync; 5094 5095 if ((scsirate & SOFS) == 0x0F) { 5096 /* 5097 * Haven't negotiated yet, 5098 * so the format is different. 5099 */ 5100 scsirate = (scsirate & SXFR) >> 4 5101 | (ultraenb & mask) 5102 ? 0x08 : 0x0 5103 | (scsirate & WIDEXFER); 5104 offset = MAX_OFFSET_ULTRA2; 5105 } else 5106 offset = ahc_inb(ahc, TARG_OFFSET + i); 5107 if ((scsirate & ~WIDEXFER) == 0 && offset != 0) 5108 /* Set to the lowest sync rate, 5MHz */ 5109 scsirate |= 0x1c; 5110 maxsync = AHC_SYNCRATE_ULTRA2; 5111 if ((ahc->features & AHC_DT) != 0) 5112 maxsync = AHC_SYNCRATE_DT; 5113 tinfo->user.period = 5114 ahc_find_period(ahc, scsirate, maxsync); 5115 if (offset == 0) 5116 tinfo->user.period = 0; 5117 else 5118 tinfo->user.offset = MAX_OFFSET; 5119 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/ 5120 && (ahc->features & AHC_DT) != 0) 5121 tinfo->user.ppr_options = 5122 MSG_EXT_PPR_DT_REQ; 5123 } else if ((scsirate & SOFS) != 0) { 5124 if ((scsirate & SXFR) == 0x40 5125 && (ultraenb & mask) != 0) { 5126 /* Treat 10MHz as a non-ultra speed */ 5127 scsirate &= ~SXFR; 5128 ultraenb &= ~mask; 5129 } 5130 tinfo->user.period = 5131 ahc_find_period(ahc, scsirate, 5132 (ultraenb & mask) 5133 ? AHC_SYNCRATE_ULTRA 5134 : AHC_SYNCRATE_FAST); 5135 if (tinfo->user.period != 0) 5136 tinfo->user.offset = MAX_OFFSET; 5137 } 5138 if (tinfo->user.period == 0) 5139 tinfo->user.offset = 0; 5140 if ((scsirate & WIDEXFER) != 0 5141 && (ahc->features & AHC_WIDE) != 0) 5142 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 5143 tinfo->user.protocol_version = 4; 5144 if ((ahc->features & AHC_DT) != 0) 5145 tinfo->user.transport_version = 3; 5146 else 5147 tinfo->user.transport_version = 2; 5148 tinfo->goal.protocol_version = 2; 5149 tinfo->goal.transport_version = 2; 5150 tinfo->curr.protocol_version = 2; 5151 tinfo->curr.transport_version = 2; 5152 } 5153 tstate->ultraenb = 0; 5154 } 5155 ahc->user_discenable = discenable; 5156 ahc->user_tagenable = tagenable; 5157 5158 return (ahc->bus_chip_init(ahc)); 5159} 5160 5161void 5162ahc_intr_enable(struct ahc_softc *ahc, int enable) 5163{ 5164 u_int hcntrl; 5165 5166 hcntrl = ahc_inb(ahc, HCNTRL); 5167 hcntrl &= ~INTEN; 5168 ahc->pause &= ~INTEN; 5169 ahc->unpause &= ~INTEN; 5170 if (enable) { 5171 hcntrl |= INTEN; 5172 ahc->pause |= INTEN; 5173 ahc->unpause |= INTEN; 5174 } 5175 ahc_outb(ahc, HCNTRL, hcntrl); 5176} 5177 5178/* 5179 * Ensure that the card is paused in a location 5180 * outside of all critical sections and that all 5181 * pending work is completed prior to returning. 5182 * This routine should only be called from outside 5183 * an interrupt context. 5184 */ 5185void 5186ahc_pause_and_flushwork(struct ahc_softc *ahc) 5187{ 5188 int intstat; 5189 int maxloops; 5190 int paused; 5191 5192 maxloops = 1000; 5193 ahc->flags |= AHC_ALL_INTERRUPTS; 5194 paused = FALSE; 5195 do { 5196 if (paused) { 5197 ahc_unpause(ahc); 5198 /* 5199 * Give the sequencer some time to service 5200 * any active selections. 5201 */ 5202 aic_delay(500); 5203 } 5204 ahc_intr(ahc); 5205 ahc_pause(ahc); 5206 paused = TRUE; 5207 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO); 5208 intstat = ahc_inb(ahc, INTSTAT); 5209 if ((intstat & INT_PEND) == 0) { 5210 ahc_clear_critical_section(ahc); 5211 intstat = ahc_inb(ahc, INTSTAT); 5212 } 5213 } while (--maxloops 5214 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0) 5215 && ((intstat & INT_PEND) != 0 5216 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0)); 5217 if (maxloops == 0) { 5218 printf("Infinite interrupt loop, INTSTAT = %x", 5219 ahc_inb(ahc, INTSTAT)); 5220 } 5221 ahc_platform_flushwork(ahc); 5222 ahc->flags &= ~AHC_ALL_INTERRUPTS; 5223} 5224 5225int 5226ahc_suspend(struct ahc_softc *ahc) 5227{ 5228 5229 ahc_pause_and_flushwork(ahc); 5230 5231 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 5232 ahc_unpause(ahc); 5233 return (EBUSY); 5234 } 5235 5236#ifdef AHC_TARGET_MODE 5237 /* 5238 * XXX What about ATIOs that have not yet been serviced? 5239 * Perhaps we should just refuse to be suspended if we 5240 * are acting in a target role. 5241 */ 5242 if (ahc->pending_device != NULL) { 5243 ahc_unpause(ahc); 5244 return (EBUSY); 5245 } 5246#endif 5247 ahc_shutdown(ahc); 5248 return (0); 5249} 5250 5251int 5252ahc_resume(struct ahc_softc *ahc) 5253{ 5254 5255 ahc_reset(ahc, /*reinit*/TRUE); 5256 ahc_intr_enable(ahc, TRUE); 5257 ahc_restart(ahc); 5258 return (0); 5259} 5260 5261/************************** Busy Target Table *********************************/ 5262/* 5263 * Return the untagged transaction id for a given target/channel lun. 5264 * Optionally, clear the entry. 5265 */ 5266u_int 5267ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl) 5268{ 5269 u_int scbid; 5270 u_int target_offset; 5271 5272 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5273 u_int saved_scbptr; 5274 5275 saved_scbptr = ahc_inb(ahc, SCBPTR); 5276 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5277 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl)); 5278 ahc_outb(ahc, SCBPTR, saved_scbptr); 5279 } else { 5280 target_offset = TCL_TARGET_OFFSET(tcl); 5281 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset); 5282 } 5283 5284 return (scbid); 5285} 5286 5287void 5288ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl) 5289{ 5290 u_int target_offset; 5291 5292 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5293 u_int saved_scbptr; 5294 5295 saved_scbptr = ahc_inb(ahc, SCBPTR); 5296 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5297 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL); 5298 ahc_outb(ahc, SCBPTR, saved_scbptr); 5299 } else { 5300 target_offset = TCL_TARGET_OFFSET(tcl); 5301 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL); 5302 } 5303} 5304 5305void 5306ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid) 5307{ 5308 u_int target_offset; 5309 5310 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5311 u_int saved_scbptr; 5312 5313 saved_scbptr = ahc_inb(ahc, SCBPTR); 5314 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5315 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid); 5316 ahc_outb(ahc, SCBPTR, saved_scbptr); 5317 } else { 5318 target_offset = TCL_TARGET_OFFSET(tcl); 5319 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid); 5320 } 5321} 5322 5323/************************** SCB and SCB queue management **********************/ 5324int 5325ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target, 5326 char channel, int lun, u_int tag, role_t role) 5327{ 5328 int targ = SCB_GET_TARGET(ahc, scb); 5329 char chan = SCB_GET_CHANNEL(ahc, scb); 5330 int slun = SCB_GET_LUN(scb); 5331 int match; 5332 5333 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5334 if (match != 0) 5335 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 5336 if (match != 0) 5337 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 5338 if (match != 0) { 5339#ifdef AHC_TARGET_MODE 5340 int group; 5341 5342 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 5343 if (role == ROLE_INITIATOR) { 5344 match = (group != XPT_FC_GROUP_TMODE) 5345 && ((tag == scb->hscb->tag) 5346 || (tag == SCB_LIST_NULL)); 5347 } else if (role == ROLE_TARGET) { 5348 match = (group == XPT_FC_GROUP_TMODE) 5349 && ((tag == scb->io_ctx->csio.tag_id) 5350 || (tag == SCB_LIST_NULL)); 5351 } 5352#else /* !AHC_TARGET_MODE */ 5353 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL)); 5354#endif /* AHC_TARGET_MODE */ 5355 } 5356 5357 return match; 5358} 5359 5360void 5361ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb) 5362{ 5363 int target; 5364 char channel; 5365 int lun; 5366 5367 target = SCB_GET_TARGET(ahc, scb); 5368 lun = SCB_GET_LUN(scb); 5369 channel = SCB_GET_CHANNEL(ahc, scb); 5370 5371 ahc_search_qinfifo(ahc, target, channel, lun, 5372 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 5373 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5374 5375 ahc_platform_freeze_devq(ahc, scb); 5376} 5377 5378void 5379ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb) 5380{ 5381 struct scb *prev_scb; 5382 5383 prev_scb = NULL; 5384 if (ahc_qinfifo_count(ahc) != 0) { 5385 u_int prev_tag; 5386 uint8_t prev_pos; 5387 5388 prev_pos = ahc->qinfifonext - 1; 5389 prev_tag = ahc->qinfifo[prev_pos]; 5390 prev_scb = ahc_lookup_scb(ahc, prev_tag); 5391 } 5392 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5393 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5394 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5395 } else { 5396 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5397 } 5398} 5399 5400static void 5401ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb, 5402 struct scb *scb) 5403{ 5404 if (prev_scb == NULL) { 5405 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5406 } else { 5407 prev_scb->hscb->next = scb->hscb->tag; 5408 ahc_sync_scb(ahc, prev_scb, 5409 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5410 } 5411 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 5412 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5413 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5414} 5415 5416static int 5417ahc_qinfifo_count(struct ahc_softc *ahc) 5418{ 5419 uint8_t qinpos; 5420 uint8_t diff; 5421 5422 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5423 qinpos = ahc_inb(ahc, SNSCB_QOFF); 5424 ahc_outb(ahc, SNSCB_QOFF, qinpos); 5425 } else 5426 qinpos = ahc_inb(ahc, QINPOS); 5427 diff = ahc->qinfifonext - qinpos; 5428 return (diff); 5429} 5430 5431int 5432ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 5433 int lun, u_int tag, role_t role, uint32_t status, 5434 ahc_search_action action) 5435{ 5436 struct scb *scb; 5437 struct scb *prev_scb; 5438 uint8_t qinstart; 5439 uint8_t qinpos; 5440 uint8_t qintail; 5441 uint8_t next; 5442 uint8_t prev; 5443 uint8_t curscbptr; 5444 int found; 5445 int have_qregs; 5446 5447 qintail = ahc->qinfifonext; 5448 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0; 5449 if (have_qregs) { 5450 qinstart = ahc_inb(ahc, SNSCB_QOFF); 5451 ahc_outb(ahc, SNSCB_QOFF, qinstart); 5452 } else 5453 qinstart = ahc_inb(ahc, QINPOS); 5454 qinpos = qinstart; 5455 found = 0; 5456 prev_scb = NULL; 5457 5458 if (action == SEARCH_COMPLETE) { 5459 /* 5460 * Don't attempt to run any queued untagged transactions 5461 * until we are done with the abort process. 5462 */ 5463 ahc_freeze_untagged_queues(ahc); 5464 } 5465 5466 /* 5467 * Start with an empty queue. Entries that are not chosen 5468 * for removal will be re-added to the queue as we go. 5469 */ 5470 ahc->qinfifonext = qinpos; 5471 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 5472 5473 while (qinpos != qintail) { 5474 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]); 5475 if (scb == NULL) { 5476 printf("qinpos = %d, SCB index = %d\n", 5477 qinpos, ahc->qinfifo[qinpos]); 5478 panic("Loop 1\n"); 5479 } 5480 5481 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) { 5482 /* 5483 * We found an scb that needs to be acted on. 5484 */ 5485 found++; 5486 switch (action) { 5487 case SEARCH_COMPLETE: 5488 { 5489 cam_status ostat; 5490 cam_status cstat; 5491 5492 ostat = aic_get_transaction_status(scb); 5493 if (ostat == CAM_REQ_INPROG) 5494 aic_set_transaction_status(scb, status); 5495 cstat = aic_get_transaction_status(scb); 5496 if (cstat != CAM_REQ_CMP) 5497 aic_freeze_scb(scb); 5498 if ((scb->flags & SCB_ACTIVE) == 0) 5499 printf("Inactive SCB in qinfifo\n"); 5500 ahc_done(ahc, scb); 5501 5502 /* FALLTHROUGH */ 5503 } 5504 case SEARCH_REMOVE: 5505 break; 5506 case SEARCH_COUNT: 5507 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5508 prev_scb = scb; 5509 break; 5510 } 5511 } else { 5512 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5513 prev_scb = scb; 5514 } 5515 qinpos++; 5516 } 5517 5518 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5519 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5520 } else { 5521 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5522 } 5523 5524 if (action != SEARCH_COUNT 5525 && (found != 0) 5526 && (qinstart != ahc->qinfifonext)) { 5527 /* 5528 * The sequencer may be in the process of dmaing 5529 * down the SCB at the beginning of the queue. 5530 * This could be problematic if either the first, 5531 * or the second SCB is removed from the queue 5532 * (the first SCB includes a pointer to the "next" 5533 * SCB to dma). If we have removed any entries, swap 5534 * the first element in the queue with the next HSCB 5535 * so the sequencer will notice that NEXT_QUEUED_SCB 5536 * has changed during its dma attempt and will retry 5537 * the DMA. 5538 */ 5539 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]); 5540 5541 if (scb == NULL) { 5542 printf("found = %d, qinstart = %d, qinfifionext = %d\n", 5543 found, qinstart, ahc->qinfifonext); 5544 panic("First/Second Qinfifo fixup\n"); 5545 } 5546 /* 5547 * ahc_swap_with_next_hscb forces our next pointer to 5548 * point to the reserved SCB for future commands. Save 5549 * and restore our original next pointer to maintain 5550 * queue integrity. 5551 */ 5552 next = scb->hscb->next; 5553 ahc->scb_data->scbindex[scb->hscb->tag] = NULL; 5554 ahc_swap_with_next_hscb(ahc, scb); 5555 scb->hscb->next = next; 5556 ahc->qinfifo[qinstart] = scb->hscb->tag; 5557 5558 /* Tell the card about the new head of the qinfifo. */ 5559 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5560 5561 /* Fixup the tail "next" pointer. */ 5562 qintail = ahc->qinfifonext - 1; 5563 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]); 5564 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5565 } 5566 5567 /* 5568 * Search waiting for selection list. 5569 */ 5570 curscbptr = ahc_inb(ahc, SCBPTR); 5571 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 5572 prev = SCB_LIST_NULL; 5573 5574 while (next != SCB_LIST_NULL) { 5575 uint8_t scb_index; 5576 5577 ahc_outb(ahc, SCBPTR, next); 5578 scb_index = ahc_inb(ahc, SCB_TAG); 5579 if (scb_index >= ahc->scb_data->numscbs) { 5580 printf("Waiting List inconsistency. " 5581 "SCB index == %d, yet numscbs == %d.", 5582 scb_index, ahc->scb_data->numscbs); 5583 ahc_dump_card_state(ahc); 5584 panic("for safety"); 5585 } 5586 scb = ahc_lookup_scb(ahc, scb_index); 5587 if (scb == NULL) { 5588 printf("scb_index = %d, next = %d\n", 5589 scb_index, next); 5590 panic("Waiting List traversal\n"); 5591 } 5592 if (ahc_match_scb(ahc, scb, target, channel, 5593 lun, SCB_LIST_NULL, role)) { 5594 /* 5595 * We found an scb that needs to be acted on. 5596 */ 5597 found++; 5598 switch (action) { 5599 case SEARCH_COMPLETE: 5600 { 5601 cam_status ostat; 5602 cam_status cstat; 5603 5604 ostat = aic_get_transaction_status(scb); 5605 if (ostat == CAM_REQ_INPROG) 5606 aic_set_transaction_status(scb, 5607 status); 5608 cstat = aic_get_transaction_status(scb); 5609 if (cstat != CAM_REQ_CMP) 5610 aic_freeze_scb(scb); 5611 if ((scb->flags & SCB_ACTIVE) == 0) 5612 printf("Inactive SCB in Wait List\n"); 5613 ahc_done(ahc, scb); 5614 /* FALLTHROUGH */ 5615 } 5616 case SEARCH_REMOVE: 5617 next = ahc_rem_wscb(ahc, next, prev); 5618 break; 5619 case SEARCH_COUNT: 5620 prev = next; 5621 next = ahc_inb(ahc, SCB_NEXT); 5622 break; 5623 } 5624 } else { 5625 5626 prev = next; 5627 next = ahc_inb(ahc, SCB_NEXT); 5628 } 5629 } 5630 ahc_outb(ahc, SCBPTR, curscbptr); 5631 5632 found += ahc_search_untagged_queues(ahc, /*aic_io_ctx_t*/NULL, target, 5633 channel, lun, status, action); 5634 5635 if (action == SEARCH_COMPLETE) 5636 ahc_release_untagged_queues(ahc); 5637 return (found); 5638} 5639 5640int 5641ahc_search_untagged_queues(struct ahc_softc *ahc, aic_io_ctx_t ctx, 5642 int target, char channel, int lun, uint32_t status, 5643 ahc_search_action action) 5644{ 5645 struct scb *scb; 5646 int maxtarget; 5647 int found; 5648 int i; 5649 5650 if (action == SEARCH_COMPLETE) { 5651 /* 5652 * Don't attempt to run any queued untagged transactions 5653 * until we are done with the abort process. 5654 */ 5655 ahc_freeze_untagged_queues(ahc); 5656 } 5657 5658 found = 0; 5659 i = 0; 5660 if ((ahc->flags & AHC_SCB_BTT) == 0) { 5661 5662 maxtarget = 16; 5663 if (target != CAM_TARGET_WILDCARD) { 5664 5665 i = target; 5666 if (channel == 'B') 5667 i += 8; 5668 maxtarget = i + 1; 5669 } 5670 } else { 5671 maxtarget = 0; 5672 } 5673 5674 for (; i < maxtarget; i++) { 5675 struct scb_tailq *untagged_q; 5676 struct scb *next_scb; 5677 5678 untagged_q = &(ahc->untagged_queues[i]); 5679 next_scb = TAILQ_FIRST(untagged_q); 5680 while (next_scb != NULL) { 5681 5682 scb = next_scb; 5683 next_scb = TAILQ_NEXT(scb, links.tqe); 5684 5685 /* 5686 * The head of the list may be the currently 5687 * active untagged command for a device. 5688 * We're only searching for commands that 5689 * have not been started. A transaction 5690 * marked active but still in the qinfifo 5691 * is removed by the qinfifo scanning code 5692 * above. 5693 */ 5694 if ((scb->flags & SCB_ACTIVE) != 0) 5695 continue; 5696 5697 if (ahc_match_scb(ahc, scb, target, channel, lun, 5698 SCB_LIST_NULL, ROLE_INITIATOR) == 0 5699 || (ctx != NULL && ctx != scb->io_ctx)) 5700 continue; 5701 5702 /* 5703 * We found an scb that needs to be acted on. 5704 */ 5705 found++; 5706 switch (action) { 5707 case SEARCH_COMPLETE: 5708 { 5709 cam_status ostat; 5710 cam_status cstat; 5711 5712 ostat = aic_get_transaction_status(scb); 5713 if (ostat == CAM_REQ_INPROG) 5714 aic_set_transaction_status(scb, status); 5715 cstat = aic_get_transaction_status(scb); 5716 if (cstat != CAM_REQ_CMP) 5717 aic_freeze_scb(scb); 5718 ahc_done(ahc, scb); 5719 break; 5720 } 5721 case SEARCH_REMOVE: 5722 scb->flags &= ~SCB_UNTAGGEDQ; 5723 TAILQ_REMOVE(untagged_q, scb, links.tqe); 5724 break; 5725 case SEARCH_COUNT: 5726 break; 5727 } 5728 } 5729 } 5730 5731 if (action == SEARCH_COMPLETE) 5732 ahc_release_untagged_queues(ahc); 5733 return (found); 5734} 5735 5736int 5737ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5738 int lun, u_int tag, int stop_on_first, int remove, 5739 int save_state) 5740{ 5741 struct scb *scbp; 5742 u_int next; 5743 u_int prev; 5744 u_int count; 5745 u_int active_scb; 5746 5747 count = 0; 5748 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5749 prev = SCB_LIST_NULL; 5750 5751 if (save_state) { 5752 /* restore this when we're done */ 5753 active_scb = ahc_inb(ahc, SCBPTR); 5754 } else 5755 /* Silence compiler */ 5756 active_scb = SCB_LIST_NULL; 5757 5758 while (next != SCB_LIST_NULL) { 5759 u_int scb_index; 5760 5761 ahc_outb(ahc, SCBPTR, next); 5762 scb_index = ahc_inb(ahc, SCB_TAG); 5763 if (scb_index >= ahc->scb_data->numscbs) { 5764 printf("Disconnected List inconsistency. " 5765 "SCB index == %d, yet numscbs == %d.", 5766 scb_index, ahc->scb_data->numscbs); 5767 ahc_dump_card_state(ahc); 5768 panic("for safety"); 5769 } 5770 5771 if (next == prev) { 5772 panic("Disconnected List Loop. " 5773 "cur SCBPTR == %x, prev SCBPTR == %x.", 5774 next, prev); 5775 } 5776 scbp = ahc_lookup_scb(ahc, scb_index); 5777 if (ahc_match_scb(ahc, scbp, target, channel, lun, 5778 tag, ROLE_INITIATOR)) { 5779 count++; 5780 if (remove) { 5781 next = 5782 ahc_rem_scb_from_disc_list(ahc, prev, next); 5783 } else { 5784 prev = next; 5785 next = ahc_inb(ahc, SCB_NEXT); 5786 } 5787 if (stop_on_first) 5788 break; 5789 } else { 5790 prev = next; 5791 next = ahc_inb(ahc, SCB_NEXT); 5792 } 5793 } 5794 if (save_state) 5795 ahc_outb(ahc, SCBPTR, active_scb); 5796 return (count); 5797} 5798 5799/* 5800 * Remove an SCB from the on chip list of disconnected transactions. 5801 * This is empty/unused if we are not performing SCB paging. 5802 */ 5803static u_int 5804ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5805{ 5806 u_int next; 5807 5808 ahc_outb(ahc, SCBPTR, scbptr); 5809 next = ahc_inb(ahc, SCB_NEXT); 5810 5811 ahc_outb(ahc, SCB_CONTROL, 0); 5812 5813 ahc_add_curscb_to_free_list(ahc); 5814 5815 if (prev != SCB_LIST_NULL) { 5816 ahc_outb(ahc, SCBPTR, prev); 5817 ahc_outb(ahc, SCB_NEXT, next); 5818 } else 5819 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5820 5821 return (next); 5822} 5823 5824/* 5825 * Add the SCB as selected by SCBPTR onto the on chip list of 5826 * free hardware SCBs. This list is empty/unused if we are not 5827 * performing SCB paging. 5828 */ 5829static void 5830ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5831{ 5832 /* 5833 * Invalidate the tag so that our abort 5834 * routines don't think it's active. 5835 */ 5836 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5837 5838 if ((ahc->flags & AHC_PAGESCBS) != 0) { 5839 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5840 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5841 } 5842} 5843 5844/* 5845 * Manipulate the waiting for selection list and return the 5846 * scb that follows the one that we remove. 5847 */ 5848static u_int 5849ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5850{ 5851 u_int curscb, next; 5852 5853 /* 5854 * Select the SCB we want to abort and 5855 * pull the next pointer out of it. 5856 */ 5857 curscb = ahc_inb(ahc, SCBPTR); 5858 ahc_outb(ahc, SCBPTR, scbpos); 5859 next = ahc_inb(ahc, SCB_NEXT); 5860 5861 /* Clear the necessary fields */ 5862 ahc_outb(ahc, SCB_CONTROL, 0); 5863 5864 ahc_add_curscb_to_free_list(ahc); 5865 5866 /* update the waiting list */ 5867 if (prev == SCB_LIST_NULL) { 5868 /* First in the list */ 5869 ahc_outb(ahc, WAITING_SCBH, next); 5870 5871 /* 5872 * Ensure we aren't attempting to perform 5873 * selection for this entry. 5874 */ 5875 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5876 } else { 5877 /* 5878 * Select the scb that pointed to us 5879 * and update its next pointer. 5880 */ 5881 ahc_outb(ahc, SCBPTR, prev); 5882 ahc_outb(ahc, SCB_NEXT, next); 5883 } 5884 5885 /* 5886 * Point us back at the original scb position. 5887 */ 5888 ahc_outb(ahc, SCBPTR, curscb); 5889 return next; 5890} 5891 5892/******************************** Error Handling ******************************/ 5893/* 5894 * Abort all SCBs that match the given description (target/channel/lun/tag), 5895 * setting their status to the passed in status if the status has not already 5896 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 5897 * is paused before it is called. 5898 */ 5899int 5900ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 5901 int lun, u_int tag, role_t role, uint32_t status) 5902{ 5903 struct scb *scbp; 5904 struct scb *scbp_next; 5905 u_int active_scb; 5906 int i, j; 5907 int maxtarget; 5908 int minlun; 5909 int maxlun; 5910 5911 int found; 5912 5913 /* 5914 * Don't attempt to run any queued untagged transactions 5915 * until we are done with the abort process. 5916 */ 5917 ahc_freeze_untagged_queues(ahc); 5918 5919 /* restore this when we're done */ 5920 active_scb = ahc_inb(ahc, SCBPTR); 5921 5922 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 5923 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5924 5925 /* 5926 * Clean out the busy target table for any untagged commands. 5927 */ 5928 i = 0; 5929 maxtarget = 16; 5930 if (target != CAM_TARGET_WILDCARD) { 5931 i = target; 5932 if (channel == 'B') 5933 i += 8; 5934 maxtarget = i + 1; 5935 } 5936 5937 if (lun == CAM_LUN_WILDCARD) { 5938 5939 /* 5940 * Unless we are using an SCB based 5941 * busy targets table, there is only 5942 * one table entry for all luns of 5943 * a target. 5944 */ 5945 minlun = 0; 5946 maxlun = 1; 5947 if ((ahc->flags & AHC_SCB_BTT) != 0) 5948 maxlun = AHC_NUM_LUNS; 5949 } else { 5950 minlun = lun; 5951 maxlun = lun + 1; 5952 } 5953 5954 if (role != ROLE_TARGET) { 5955 for (;i < maxtarget; i++) { 5956 for (j = minlun;j < maxlun; j++) { 5957 u_int scbid; 5958 u_int tcl; 5959 5960 tcl = BUILD_TCL(i << 4, j); 5961 scbid = ahc_index_busy_tcl(ahc, tcl); 5962 scbp = ahc_lookup_scb(ahc, scbid); 5963 if (scbp == NULL 5964 || ahc_match_scb(ahc, scbp, target, channel, 5965 lun, tag, role) == 0) 5966 continue; 5967 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j)); 5968 } 5969 } 5970 5971 /* 5972 * Go through the disconnected list and remove any entries we 5973 * have queued for completion, 0'ing their control byte too. 5974 * We save the active SCB and restore it ourselves, so there 5975 * is no reason for this search to restore it too. 5976 */ 5977 ahc_search_disc_list(ahc, target, channel, lun, tag, 5978 /*stop_on_first*/FALSE, /*remove*/TRUE, 5979 /*save_state*/FALSE); 5980 } 5981 5982 /* 5983 * Go through the hardware SCB array looking for commands that 5984 * were active but not on any list. In some cases, these remnants 5985 * might not still have mappings in the scbindex array (e.g. unexpected 5986 * bus free with the same scb queued for an abort). Don't hold this 5987 * against them. 5988 */ 5989 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5990 u_int scbid; 5991 5992 ahc_outb(ahc, SCBPTR, i); 5993 scbid = ahc_inb(ahc, SCB_TAG); 5994 scbp = ahc_lookup_scb(ahc, scbid); 5995 if ((scbp == NULL && scbid != SCB_LIST_NULL) 5996 || (scbp != NULL 5997 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role))) 5998 ahc_add_curscb_to_free_list(ahc); 5999 } 6000 6001 /* 6002 * Go through the pending CCB list and look for 6003 * commands for this target that are still active. 6004 * These are other tagged commands that were 6005 * disconnected when the reset occurred. 6006 */ 6007 scbp_next = LIST_FIRST(&ahc->pending_scbs); 6008 while (scbp_next != NULL) { 6009 scbp = scbp_next; 6010 scbp_next = LIST_NEXT(scbp, pending_links); 6011 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) { 6012 cam_status ostat; 6013 6014 ostat = aic_get_transaction_status(scbp); 6015 if (ostat == CAM_REQ_INPROG) 6016 aic_set_transaction_status(scbp, status); 6017 if (aic_get_transaction_status(scbp) != CAM_REQ_CMP) 6018 aic_freeze_scb(scbp); 6019 if ((scbp->flags & SCB_ACTIVE) == 0) 6020 printf("Inactive SCB on pending list\n"); 6021 ahc_done(ahc, scbp); 6022 found++; 6023 } 6024 } 6025 ahc_outb(ahc, SCBPTR, active_scb); 6026 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status); 6027 ahc_release_untagged_queues(ahc); 6028 return found; 6029} 6030 6031static void 6032ahc_reset_current_bus(struct ahc_softc *ahc) 6033{ 6034 uint8_t scsiseq; 6035 6036 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 6037 scsiseq = ahc_inb(ahc, SCSISEQ); 6038 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 6039 ahc_flush_device_writes(ahc); 6040 aic_delay(AHC_BUSRESET_DELAY); 6041 /* Turn off the bus reset */ 6042 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 6043 6044 ahc_clear_intstat(ahc); 6045 6046 /* Re-enable reset interrupts */ 6047 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 6048} 6049 6050int 6051ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 6052{ 6053 struct ahc_devinfo devinfo; 6054 u_int initiator, target, max_scsiid; 6055 u_int sblkctl; 6056 u_int scsiseq; 6057 u_int simode1; 6058 int found; 6059 int restart_needed; 6060 char cur_channel; 6061 6062 ahc->pending_device = NULL; 6063 6064 ahc_compile_devinfo(&devinfo, 6065 CAM_TARGET_WILDCARD, 6066 CAM_TARGET_WILDCARD, 6067 CAM_LUN_WILDCARD, 6068 channel, ROLE_UNKNOWN); 6069 ahc_pause(ahc); 6070 6071 /* Make sure the sequencer is in a safe location. */ 6072 ahc_clear_critical_section(ahc); 6073 6074 /* 6075 * Run our command complete fifos to ensure that we perform 6076 * completion processing on any commands that 'completed' 6077 * before the reset occurred. 6078 */ 6079 ahc_run_qoutfifo(ahc); 6080#ifdef AHC_TARGET_MODE 6081 /* 6082 * XXX - In Twin mode, the tqinfifo may have commands 6083 * for an unaffected channel in it. However, if 6084 * we have run out of ATIO resources to drain that 6085 * queue, we may not get them all out here. Further, 6086 * the blocked transactions for the reset channel 6087 * should just be killed off, irrespecitve of whether 6088 * we are blocked on ATIO resources. Write a routine 6089 * to compact the tqinfifo appropriately. 6090 */ 6091 if ((ahc->flags & AHC_TARGETROLE) != 0) { 6092 ahc_run_tqinfifo(ahc, /*paused*/TRUE); 6093 } 6094#endif 6095 6096 /* 6097 * Reset the bus if we are initiating this reset 6098 */ 6099 sblkctl = ahc_inb(ahc, SBLKCTL); 6100 cur_channel = 'A'; 6101 if ((ahc->features & AHC_TWIN) != 0 6102 && ((sblkctl & SELBUSB) != 0)) 6103 cur_channel = 'B'; 6104 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 6105 if (cur_channel != channel) { 6106 /* Case 1: Command for another bus is active 6107 * Stealthily reset the other bus without 6108 * upsetting the current bus. 6109 */ 6110 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 6111 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 6112#ifdef AHC_TARGET_MODE 6113 /* 6114 * Bus resets clear ENSELI, so we cannot 6115 * defer re-enabling bus reset interrupts 6116 * if we are in target mode. 6117 */ 6118 if ((ahc->flags & AHC_TARGETROLE) != 0) 6119 simode1 |= ENSCSIRST; 6120#endif 6121 ahc_outb(ahc, SIMODE1, simode1); 6122 if (initiate_reset) 6123 ahc_reset_current_bus(ahc); 6124 ahc_clear_intstat(ahc); 6125 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 6126 ahc_outb(ahc, SBLKCTL, sblkctl); 6127 restart_needed = FALSE; 6128 } else { 6129 /* Case 2: A command from this bus is active or we're idle */ 6130 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 6131#ifdef AHC_TARGET_MODE 6132 /* 6133 * Bus resets clear ENSELI, so we cannot 6134 * defer re-enabling bus reset interrupts 6135 * if we are in target mode. 6136 */ 6137 if ((ahc->flags & AHC_TARGETROLE) != 0) 6138 simode1 |= ENSCSIRST; 6139#endif 6140 ahc_outb(ahc, SIMODE1, simode1); 6141 if (initiate_reset) 6142 ahc_reset_current_bus(ahc); 6143 ahc_clear_intstat(ahc); 6144 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 6145 restart_needed = TRUE; 6146 } 6147 6148 /* 6149 * Clean up all the state information for the 6150 * pending transactions on this bus. 6151 */ 6152 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel, 6153 CAM_LUN_WILDCARD, SCB_LIST_NULL, 6154 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 6155 6156 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 6157 6158#ifdef AHC_TARGET_MODE 6159 /* 6160 * Send an immediate notify ccb to all target more peripheral 6161 * drivers affected by this action. 6162 */ 6163 for (target = 0; target <= max_scsiid; target++) { 6164 struct ahc_tmode_tstate* tstate; 6165 u_int lun; 6166 6167 tstate = ahc->enabled_targets[target]; 6168 if (tstate == NULL) 6169 continue; 6170 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 6171 struct ahc_tmode_lstate* lstate; 6172 6173 lstate = tstate->enabled_luns[lun]; 6174 if (lstate == NULL) 6175 continue; 6176 6177 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD, 6178 EVENT_TYPE_BUS_RESET, /*arg*/0); 6179 ahc_send_lstate_events(ahc, lstate); 6180 } 6181 } 6182#endif 6183 /* Notify the XPT that a bus reset occurred */ 6184 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD, 6185 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL); 6186 6187 /* 6188 * Revert to async/narrow transfers until we renegotiate. 6189 */ 6190 for (target = 0; target <= max_scsiid; target++) { 6191 6192 if (ahc->enabled_targets[target] == NULL) 6193 continue; 6194 for (initiator = 0; initiator <= max_scsiid; initiator++) { 6195 struct ahc_devinfo devinfo; 6196 6197 ahc_compile_devinfo(&devinfo, target, initiator, 6198 CAM_LUN_WILDCARD, 6199 channel, ROLE_UNKNOWN); 6200 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6201 AHC_TRANS_CUR, /*paused*/TRUE); 6202 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL, 6203 /*period*/0, /*offset*/0, 6204 /*ppr_options*/0, AHC_TRANS_CUR, 6205 /*paused*/TRUE); 6206 } 6207 } 6208 6209 if (restart_needed) 6210 ahc_restart(ahc); 6211 else 6212 ahc_unpause(ahc); 6213 return found; 6214} 6215 6216 6217/***************************** Residual Processing ****************************/ 6218/* 6219 * Calculate the residual for a just completed SCB. 6220 */ 6221void 6222ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb) 6223{ 6224 struct hardware_scb *hscb; 6225 struct status_pkt *spkt; 6226 uint32_t sgptr; 6227 uint32_t resid_sgptr; 6228 uint32_t resid; 6229 6230 /* 6231 * 5 cases. 6232 * 1) No residual. 6233 * SG_RESID_VALID clear in sgptr. 6234 * 2) Transferless command 6235 * 3) Never performed any transfers. 6236 * sgptr has SG_FULL_RESID set. 6237 * 4) No residual but target did not 6238 * save data pointers after the 6239 * last transfer, so sgptr was 6240 * never updated. 6241 * 5) We have a partial residual. 6242 * Use residual_sgptr to determine 6243 * where we are. 6244 */ 6245 6246 hscb = scb->hscb; 6247 sgptr = aic_le32toh(hscb->sgptr); 6248 if ((sgptr & SG_RESID_VALID) == 0) 6249 /* Case 1 */ 6250 return; 6251 sgptr &= ~SG_RESID_VALID; 6252 6253 if ((sgptr & SG_LIST_NULL) != 0) 6254 /* Case 2 */ 6255 return; 6256 6257 spkt = &hscb->shared_data.status; 6258 resid_sgptr = aic_le32toh(spkt->residual_sg_ptr); 6259 if ((sgptr & SG_FULL_RESID) != 0) { 6260 /* Case 3 */ 6261 resid = aic_get_transfer_length(scb); 6262 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 6263 /* Case 4 */ 6264 return; 6265 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 6266 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 6267 /* NOTREACHED */ 6268 return; 6269 } else { 6270 struct ahc_dma_seg *sg; 6271 6272 /* 6273 * Remainder of the SG where the transfer 6274 * stopped. 6275 */ 6276 resid = aic_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK; 6277 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK); 6278 6279 /* The residual sg_ptr always points to the next sg */ 6280 sg--; 6281 6282 /* 6283 * Add up the contents of all residual 6284 * SG segments that are after the SG where 6285 * the transfer stopped. 6286 */ 6287 while ((aic_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) { 6288 sg++; 6289 resid += aic_le32toh(sg->len) & AHC_SG_LEN_MASK; 6290 } 6291 } 6292 if ((scb->flags & SCB_SENSE) == 0) 6293 aic_set_residual(scb, resid); 6294 else 6295 aic_set_sense_residual(scb, resid); 6296 6297#ifdef AHC_DEBUG 6298 if ((ahc_debug & AHC_SHOW_MISC) != 0) { 6299 ahc_print_path(ahc, scb); 6300 printf("Handled %sResidual of %d bytes\n", 6301 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 6302 } 6303#endif 6304} 6305 6306/******************************* Target Mode **********************************/ 6307#ifdef AHC_TARGET_MODE 6308/* 6309 * Add a target mode event to this lun's queue 6310 */ 6311static void 6312ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate, 6313 u_int initiator_id, u_int event_type, u_int event_arg) 6314{ 6315 struct ahc_tmode_event *event; 6316 int pending; 6317 6318 xpt_freeze_devq(lstate->path, /*count*/1); 6319 if (lstate->event_w_idx >= lstate->event_r_idx) 6320 pending = lstate->event_w_idx - lstate->event_r_idx; 6321 else 6322 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1 6323 - (lstate->event_r_idx - lstate->event_w_idx); 6324 6325 if (event_type == EVENT_TYPE_BUS_RESET 6326 || event_type == MSG_BUS_DEV_RESET) { 6327 /* 6328 * Any earlier events are irrelevant, so reset our buffer. 6329 * This has the effect of allowing us to deal with reset 6330 * floods (an external device holding down the reset line) 6331 * without losing the event that is really interesting. 6332 */ 6333 lstate->event_r_idx = 0; 6334 lstate->event_w_idx = 0; 6335 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 6336 } 6337 6338 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) { 6339 xpt_print_path(lstate->path); 6340 printf("immediate event %x:%x lost\n", 6341 lstate->event_buffer[lstate->event_r_idx].event_type, 6342 lstate->event_buffer[lstate->event_r_idx].event_arg); 6343 lstate->event_r_idx++; 6344 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6345 lstate->event_r_idx = 0; 6346 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 6347 } 6348 6349 event = &lstate->event_buffer[lstate->event_w_idx]; 6350 event->initiator_id = initiator_id; 6351 event->event_type = event_type; 6352 event->event_arg = event_arg; 6353 lstate->event_w_idx++; 6354 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6355 lstate->event_w_idx = 0; 6356} 6357 6358/* 6359 * Send any target mode events queued up waiting 6360 * for immediate notify resources. 6361 */ 6362void 6363ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate) 6364{ 6365 struct ccb_hdr *ccbh; 6366 struct ccb_immediate_notify *inot; 6367 6368 while (lstate->event_r_idx != lstate->event_w_idx 6369 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 6370 struct ahc_tmode_event *event; 6371 6372 event = &lstate->event_buffer[lstate->event_r_idx]; 6373 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 6374 inot = (struct ccb_immediate_notify *)ccbh; 6375 switch (event->event_type) { 6376 case EVENT_TYPE_BUS_RESET: 6377 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 6378 break; 6379 default: 6380 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 6381 inot->arg = event->event_type; 6382 inot->seq_id = event->event_arg; 6383 break; 6384 } 6385 inot->initiator_id = event->initiator_id; 6386 xpt_done((union ccb *)inot); 6387 lstate->event_r_idx++; 6388 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6389 lstate->event_r_idx = 0; 6390 } 6391} 6392#endif 6393 6394/******************** Sequencer Program Patching/Download *********************/ 6395 6396#ifdef AHC_DUMP_SEQ 6397void 6398ahc_dumpseq(struct ahc_softc* ahc) 6399{ 6400 int i; 6401 6402 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6403 ahc_outb(ahc, SEQADDR0, 0); 6404 ahc_outb(ahc, SEQADDR1, 0); 6405 for (i = 0; i < ahc->instruction_ram_size; i++) { 6406 uint8_t ins_bytes[4]; 6407 6408 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 6409 printf("0x%08x\n", ins_bytes[0] << 24 6410 | ins_bytes[1] << 16 6411 | ins_bytes[2] << 8 6412 | ins_bytes[3]); 6413 } 6414} 6415#endif 6416 6417static int 6418ahc_loadseq(struct ahc_softc *ahc) 6419{ 6420 struct cs cs_table[num_critical_sections]; 6421 u_int begin_set[num_critical_sections]; 6422 u_int end_set[num_critical_sections]; 6423 struct patch *cur_patch; 6424 u_int cs_count; 6425 u_int cur_cs; 6426 u_int i; 6427 u_int skip_addr; 6428 u_int sg_prefetch_cnt; 6429 int downloaded; 6430 uint8_t download_consts[7]; 6431 6432 /* 6433 * Start out with 0 critical sections 6434 * that apply to this firmware load. 6435 */ 6436 cs_count = 0; 6437 cur_cs = 0; 6438 memset(begin_set, 0, sizeof(begin_set)); 6439 memset(end_set, 0, sizeof(end_set)); 6440 6441 /* Setup downloadable constant table */ 6442 download_consts[QOUTFIFO_OFFSET] = 0; 6443 if (ahc->targetcmds != NULL) 6444 download_consts[QOUTFIFO_OFFSET] += 32; 6445 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1; 6446 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1; 6447 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1); 6448 sg_prefetch_cnt = ahc->pci_cachesize; 6449 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg))) 6450 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg); 6451 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 6452 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1); 6453 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1); 6454 6455 cur_patch = patches; 6456 downloaded = 0; 6457 skip_addr = 0; 6458 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6459 ahc_outb(ahc, SEQADDR0, 0); 6460 ahc_outb(ahc, SEQADDR1, 0); 6461 6462 for (i = 0; i < sizeof(seqprog)/4; i++) { 6463 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 6464 /* 6465 * Don't download this instruction as it 6466 * is in a patch that was removed. 6467 */ 6468 continue; 6469 } 6470 6471 if (downloaded == ahc->instruction_ram_size) { 6472 /* 6473 * We're about to exceed the instruction 6474 * storage capacity for this chip. Fail 6475 * the load. 6476 */ 6477 printf("\n%s: Program too large for instruction memory " 6478 "size of %d!\n", ahc_name(ahc), 6479 ahc->instruction_ram_size); 6480 return (ENOMEM); 6481 } 6482 6483 /* 6484 * Move through the CS table until we find a CS 6485 * that might apply to this instruction. 6486 */ 6487 for (; cur_cs < num_critical_sections; cur_cs++) { 6488 if (critical_sections[cur_cs].end <= i) { 6489 if (begin_set[cs_count] == TRUE 6490 && end_set[cs_count] == FALSE) { 6491 cs_table[cs_count].end = downloaded; 6492 end_set[cs_count] = TRUE; 6493 cs_count++; 6494 } 6495 continue; 6496 } 6497 if (critical_sections[cur_cs].begin <= i 6498 && begin_set[cs_count] == FALSE) { 6499 cs_table[cs_count].begin = downloaded; 6500 begin_set[cs_count] = TRUE; 6501 } 6502 break; 6503 } 6504 ahc_download_instr(ahc, i, download_consts); 6505 downloaded++; 6506 } 6507 6508 ahc->num_critical_sections = cs_count; 6509 if (cs_count != 0) { 6510 6511 cs_count *= sizeof(struct cs); 6512 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 6513 if (ahc->critical_sections == NULL) 6514 panic("ahc_loadseq: Could not malloc"); 6515 memcpy(ahc->critical_sections, cs_table, cs_count); 6516 } 6517 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 6518 6519 if (bootverbose) { 6520 printf(" %d instructions downloaded\n", downloaded); 6521 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 6522 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags); 6523 } 6524 return (0); 6525} 6526 6527static int 6528ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 6529 u_int start_instr, u_int *skip_addr) 6530{ 6531 struct patch *cur_patch; 6532 struct patch *last_patch; 6533 u_int num_patches; 6534 6535 num_patches = sizeof(patches)/sizeof(struct patch); 6536 last_patch = &patches[num_patches]; 6537 cur_patch = *start_patch; 6538 6539 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 6540 6541 if (cur_patch->patch_func(ahc) == 0) { 6542 6543 /* Start rejecting code */ 6544 *skip_addr = start_instr + cur_patch->skip_instr; 6545 cur_patch += cur_patch->skip_patch; 6546 } else { 6547 /* Accepted this patch. Advance to the next 6548 * one and wait for our instruction pointer to 6549 * hit this point. 6550 */ 6551 cur_patch++; 6552 } 6553 } 6554 6555 *start_patch = cur_patch; 6556 if (start_instr < *skip_addr) 6557 /* Still skipping */ 6558 return (0); 6559 6560 return (1); 6561} 6562 6563static void 6564ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts) 6565{ 6566 union ins_formats instr; 6567 struct ins_format1 *fmt1_ins; 6568 struct ins_format3 *fmt3_ins; 6569 u_int opcode; 6570 6571 /* 6572 * The firmware is always compiled into a little endian format. 6573 */ 6574 instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 6575 6576 fmt1_ins = &instr.format1; 6577 fmt3_ins = NULL; 6578 6579 /* Pull the opcode */ 6580 opcode = instr.format1.opcode; 6581 switch (opcode) { 6582 case AIC_OP_JMP: 6583 case AIC_OP_JC: 6584 case AIC_OP_JNC: 6585 case AIC_OP_CALL: 6586 case AIC_OP_JNE: 6587 case AIC_OP_JNZ: 6588 case AIC_OP_JE: 6589 case AIC_OP_JZ: 6590 { 6591 struct patch *cur_patch; 6592 int address_offset; 6593 u_int address; 6594 u_int skip_addr; 6595 u_int i; 6596 6597 fmt3_ins = &instr.format3; 6598 address_offset = 0; 6599 address = fmt3_ins->address; 6600 cur_patch = patches; 6601 skip_addr = 0; 6602 6603 for (i = 0; i < address;) { 6604 6605 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 6606 6607 if (skip_addr > i) { 6608 int end_addr; 6609 6610 end_addr = MIN(address, skip_addr); 6611 address_offset += end_addr - i; 6612 i = skip_addr; 6613 } else { 6614 i++; 6615 } 6616 } 6617 address -= address_offset; 6618 fmt3_ins->address = address; 6619 /* FALLTHROUGH */ 6620 } 6621 case AIC_OP_OR: 6622 case AIC_OP_AND: 6623 case AIC_OP_XOR: 6624 case AIC_OP_ADD: 6625 case AIC_OP_ADC: 6626 case AIC_OP_BMOV: 6627 if (fmt1_ins->parity != 0) { 6628 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 6629 } 6630 fmt1_ins->parity = 0; 6631 if ((ahc->features & AHC_CMD_CHAN) == 0 6632 && opcode == AIC_OP_BMOV) { 6633 /* 6634 * Block move was added at the same time 6635 * as the command channel. Verify that 6636 * this is only a move of a single element 6637 * and convert the BMOV to a MOV 6638 * (AND with an immediate of FF). 6639 */ 6640 if (fmt1_ins->immediate != 1) 6641 panic("%s: BMOV not supported\n", 6642 ahc_name(ahc)); 6643 fmt1_ins->opcode = AIC_OP_AND; 6644 fmt1_ins->immediate = 0xff; 6645 } 6646 /* FALLTHROUGH */ 6647 case AIC_OP_ROL: 6648 if ((ahc->features & AHC_ULTRA2) != 0) { 6649 int i, count; 6650 6651 /* Calculate odd parity for the instruction */ 6652 for (i = 0, count = 0; i < 31; i++) { 6653 uint32_t mask; 6654 6655 mask = 0x01 << i; 6656 if ((instr.integer & mask) != 0) 6657 count++; 6658 } 6659 if ((count & 0x01) == 0) 6660 instr.format1.parity = 1; 6661 } else { 6662 /* Compress the instruction for older sequencers */ 6663 if (fmt3_ins != NULL) { 6664 instr.integer = 6665 fmt3_ins->immediate 6666 | (fmt3_ins->source << 8) 6667 | (fmt3_ins->address << 16) 6668 | (fmt3_ins->opcode << 25); 6669 } else { 6670 instr.integer = 6671 fmt1_ins->immediate 6672 | (fmt1_ins->source << 8) 6673 | (fmt1_ins->destination << 16) 6674 | (fmt1_ins->ret << 24) 6675 | (fmt1_ins->opcode << 25); 6676 } 6677 } 6678 /* The sequencer is a little endian cpu */ 6679 instr.integer = aic_htole32(instr.integer); 6680 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 6681 break; 6682 default: 6683 panic("Unknown opcode encountered in seq program"); 6684 break; 6685 } 6686} 6687 6688int 6689ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries, 6690 const char *name, u_int address, u_int value, 6691 u_int *cur_column, u_int wrap_point) 6692{ 6693 int printed; 6694 u_int printed_mask; 6695 u_int dummy_column; 6696 6697 if (cur_column == NULL) { 6698 dummy_column = 0; 6699 cur_column = &dummy_column; 6700 } 6701 6702 if (*cur_column >= wrap_point) { 6703 printf("\n"); 6704 *cur_column = 0; 6705 } 6706 printed = printf("%s[0x%x]", name, value); 6707 if (table == NULL) { 6708 printed += printf(" "); 6709 *cur_column += printed; 6710 return (printed); 6711 } 6712 printed_mask = 0; 6713 while (printed_mask != 0xFF) { 6714 int entry; 6715 6716 for (entry = 0; entry < num_entries; entry++) { 6717 if (((value & table[entry].mask) 6718 != table[entry].value) 6719 || ((printed_mask & table[entry].mask) 6720 == table[entry].mask)) 6721 continue; 6722 6723 printed += printf("%s%s", 6724 printed_mask == 0 ? ":(" : "|", 6725 table[entry].name); 6726 printed_mask |= table[entry].mask; 6727 6728 break; 6729 } 6730 if (entry >= num_entries) 6731 break; 6732 } 6733 if (printed_mask != 0) 6734 printed += printf(") "); 6735 else 6736 printed += printf(" "); 6737 if (cur_column != NULL) 6738 *cur_column += printed; 6739 return (printed); 6740} 6741 6742void 6743ahc_dump_card_state(struct ahc_softc *ahc) 6744{ 6745 struct scb *scb; 6746 struct scb_tailq *untagged_q; 6747 u_int cur_col; 6748 int paused; 6749 int target; 6750 int maxtarget; 6751 int i; 6752 uint8_t last_phase; 6753 uint8_t qinpos; 6754 uint8_t qintail; 6755 uint8_t qoutpos; 6756 uint8_t scb_index; 6757 uint8_t saved_scbptr; 6758 6759 if (ahc_is_paused(ahc)) { 6760 paused = 1; 6761 } else { 6762 paused = 0; 6763 ahc_pause(ahc); 6764 } 6765 6766 saved_scbptr = ahc_inb(ahc, SCBPTR); 6767 last_phase = ahc_inb(ahc, LASTPHASE); 6768 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 6769 "%s: Dumping Card State %s, at SEQADDR 0x%x\n", 6770 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg, 6771 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 6772 if (paused) 6773 printf("Card was paused\n"); 6774 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n", 6775 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX), 6776 ahc_inb(ahc, ARG_2)); 6777 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT), 6778 ahc_inb(ahc, SCBPTR)); 6779 cur_col = 0; 6780 if ((ahc->features & AHC_DT) != 0) 6781 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50); 6782 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50); 6783 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50); 6784 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50); 6785 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50); 6786 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50); 6787 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50); 6788 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50); 6789 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50); 6790 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50); 6791 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50); 6792 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50); 6793 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50); 6794 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50); 6795 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50); 6796 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50); 6797 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50); 6798 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50); 6799 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50); 6800 if (cur_col != 0) 6801 printf("\n"); 6802 printf("STACK:"); 6803 for (i = 0; i < STACK_SIZE; i++) 6804 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8)); 6805 printf("\nSCB count = %d\n", ahc->scb_data->numscbs); 6806 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag); 6807 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB)); 6808 /* QINFIFO */ 6809 printf("QINFIFO entries: "); 6810 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 6811 qinpos = ahc_inb(ahc, SNSCB_QOFF); 6812 ahc_outb(ahc, SNSCB_QOFF, qinpos); 6813 } else 6814 qinpos = ahc_inb(ahc, QINPOS); 6815 qintail = ahc->qinfifonext; 6816 while (qinpos != qintail) { 6817 printf("%d ", ahc->qinfifo[qinpos]); 6818 qinpos++; 6819 } 6820 printf("\n"); 6821 6822 printf("Waiting Queue entries: "); 6823 scb_index = ahc_inb(ahc, WAITING_SCBH); 6824 i = 0; 6825 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6826 ahc_outb(ahc, SCBPTR, scb_index); 6827 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6828 scb_index = ahc_inb(ahc, SCB_NEXT); 6829 } 6830 printf("\n"); 6831 6832 printf("Disconnected Queue entries: "); 6833 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH); 6834 i = 0; 6835 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6836 ahc_outb(ahc, SCBPTR, scb_index); 6837 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6838 scb_index = ahc_inb(ahc, SCB_NEXT); 6839 } 6840 printf("\n"); 6841 6842 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 6843 printf("QOUTFIFO entries: "); 6844 qoutpos = ahc->qoutfifonext; 6845 i = 0; 6846 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) { 6847 printf("%d ", ahc->qoutfifo[qoutpos]); 6848 qoutpos++; 6849 } 6850 printf("\n"); 6851 6852 printf("Sequencer Free SCB List: "); 6853 scb_index = ahc_inb(ahc, FREE_SCBH); 6854 i = 0; 6855 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6856 ahc_outb(ahc, SCBPTR, scb_index); 6857 printf("%d ", scb_index); 6858 scb_index = ahc_inb(ahc, SCB_NEXT); 6859 } 6860 printf("\n"); 6861 6862 printf("Sequencer SCB Info: "); 6863 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 6864 ahc_outb(ahc, SCBPTR, i); 6865 cur_col = printf("\n%3d ", i); 6866 6867 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60); 6868 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60); 6869 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60); 6870 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6871 } 6872 printf("\n"); 6873 6874 printf("Pending list: "); 6875 i = 0; 6876 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 6877 if (i++ > 256) 6878 break; 6879 cur_col = printf("\n%3d ", scb->hscb->tag); 6880 ahc_scb_control_print(scb->hscb->control, &cur_col, 60); 6881 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60); 6882 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60); 6883 if ((ahc->flags & AHC_PAGESCBS) == 0) { 6884 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 6885 printf("("); 6886 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), 6887 &cur_col, 60); 6888 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6889 printf(")"); 6890 } 6891 } 6892 printf("\n"); 6893 6894 printf("Kernel Free SCB list: "); 6895 i = 0; 6896 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) { 6897 if (i++ > 256) 6898 break; 6899 printf("%d ", scb->hscb->tag); 6900 } 6901 printf("\n"); 6902 6903 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7; 6904 for (target = 0; target <= maxtarget; target++) { 6905 untagged_q = &ahc->untagged_queues[target]; 6906 if (TAILQ_FIRST(untagged_q) == NULL) 6907 continue; 6908 printf("Untagged Q(%d): ", target); 6909 i = 0; 6910 TAILQ_FOREACH(scb, untagged_q, links.tqe) { 6911 if (i++ > 256) 6912 break; 6913 printf("%d ", scb->hscb->tag); 6914 } 6915 printf("\n"); 6916 } 6917 6918 ahc_platform_dump_card_state(ahc); 6919 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 6920 ahc_outb(ahc, SCBPTR, saved_scbptr); 6921 if (paused == 0) 6922 ahc_unpause(ahc); 6923} 6924 6925/*************************** Timeout Handling *********************************/ 6926void 6927ahc_timeout(struct scb *scb) 6928{ 6929 struct ahc_softc *ahc; 6930 6931 ahc = scb->ahc_softc; 6932 if ((scb->flags & SCB_ACTIVE) != 0) { 6933 if ((scb->flags & SCB_TIMEDOUT) == 0) { 6934 LIST_INSERT_HEAD(&ahc->timedout_scbs, scb, 6935 timedout_links); 6936 scb->flags |= SCB_TIMEDOUT; 6937 } 6938 ahc_wakeup_recovery_thread(ahc); 6939 } 6940} 6941 6942/* 6943 * Re-schedule a timeout for the passed in SCB if we determine that some 6944 * other SCB is in the process of recovery or an SCB with a longer 6945 * timeout is still pending. Limit our search to just "other_scb" 6946 * if it is non-NULL. 6947 */ 6948static int 6949ahc_other_scb_timeout(struct ahc_softc *ahc, struct scb *scb, 6950 struct scb *other_scb) 6951{ 6952 u_int newtimeout; 6953 int found; 6954 6955 ahc_print_path(ahc, scb); 6956 printf("Other SCB Timeout%s", 6957 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 6958 ? " again\n" : "\n"); 6959 6960 newtimeout = aic_get_timeout(scb); 6961 scb->flags |= SCB_OTHERTCL_TIMEOUT; 6962 found = 0; 6963 if (other_scb != NULL) { 6964 if ((other_scb->flags 6965 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0 6966 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) { 6967 found++; 6968 newtimeout = MAX(aic_get_timeout(other_scb), 6969 newtimeout); 6970 } 6971 } else { 6972 LIST_FOREACH(other_scb, &ahc->pending_scbs, pending_links) { 6973 if ((other_scb->flags 6974 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0 6975 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) { 6976 found++; 6977 newtimeout = 6978 MAX(aic_get_timeout(other_scb), 6979 newtimeout); 6980 } 6981 } 6982 } 6983 6984 if (found != 0) 6985 aic_scb_timer_reset(scb, newtimeout); 6986 else { 6987 ahc_print_path(ahc, scb); 6988 printf("No other SCB worth waiting for...\n"); 6989 } 6990 6991 return (found != 0); 6992} 6993 6994/* 6995 * ahc_recover_commands determines if any of the commands that have currently 6996 * timedout are the root cause for this timeout. Innocent commands are given 6997 * a new timeout while we wait for the command executing on the bus to timeout. 6998 * This routine is invoked from a thread context so we are allowed to sleep. 6999 * Our lock is not held on entry. 7000 */ 7001void 7002ahc_recover_commands(struct ahc_softc *ahc) 7003{ 7004 struct scb *scb; 7005 int found; 7006 int restart_needed; 7007 u_int last_phase; 7008 7009 /* 7010 * Pause the controller and manually flush any 7011 * commands that have just completed but that our 7012 * interrupt handler has yet to see. 7013 */ 7014 ahc_pause_and_flushwork(ahc); 7015 7016 if (LIST_EMPTY(&ahc->timedout_scbs) != 0) { 7017 /* 7018 * The timedout commands have already 7019 * completed. This typically means 7020 * that either the timeout value was on 7021 * the hairy edge of what the device 7022 * requires or - more likely - interrupts 7023 * are not happening. 7024 */ 7025 printf("%s: Timedout SCBs already complete. " 7026 "Interrupts may not be functioning.\n", ahc_name(ahc)); 7027 ahc_unpause(ahc); 7028 return; 7029 } 7030 7031 restart_needed = 0; 7032 printf("%s: Recovery Initiated\n", ahc_name(ahc)); 7033 ahc_dump_card_state(ahc); 7034 7035 last_phase = ahc_inb(ahc, LASTPHASE); 7036 while ((scb = LIST_FIRST(&ahc->timedout_scbs)) != NULL) { 7037 u_int active_scb_index; 7038 u_int saved_scbptr; 7039 int target; 7040 int lun; 7041 int i; 7042 char channel; 7043 7044 target = SCB_GET_TARGET(ahc, scb); 7045 channel = SCB_GET_CHANNEL(ahc, scb); 7046 lun = SCB_GET_LUN(scb); 7047 7048 ahc_print_path(ahc, scb); 7049 printf("SCB 0x%x - timed out\n", scb->hscb->tag); 7050 if (scb->sg_count > 0) { 7051 for (i = 0; i < scb->sg_count; i++) { 7052 printf("sg[%d] - Addr 0x%x : Length %d\n", 7053 i, 7054 scb->sg_list[i].addr, 7055 scb->sg_list[i].len & AHC_SG_LEN_MASK); 7056 } 7057 } 7058 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 7059 /* 7060 * Been down this road before. 7061 * Do a full bus reset. 7062 */ 7063 aic_set_transaction_status(scb, CAM_CMD_TIMEOUT); 7064bus_reset: 7065 found = ahc_reset_channel(ahc, channel, 7066 /*Initiate Reset*/TRUE); 7067 printf("%s: Issued Channel %c Bus Reset. " 7068 "%d SCBs aborted\n", ahc_name(ahc), channel, 7069 found); 7070 continue; 7071 } 7072 7073 /* 7074 * Remove the command from the timedout list in 7075 * preparation for requeing it. 7076 */ 7077 LIST_REMOVE(scb, timedout_links); 7078 scb->flags &= ~SCB_TIMEDOUT; 7079 7080 /* 7081 * If we are a target, transition to bus free and report 7082 * the timeout. 7083 * 7084 * The target/initiator that is holding up the bus may not 7085 * be the same as the one that triggered this timeout 7086 * (different commands have different timeout lengths). 7087 * If the bus is idle and we are actiing as the initiator 7088 * for this request, queue a BDR message to the timed out 7089 * target. Otherwise, if the timed out transaction is 7090 * active: 7091 * Initiator transaction: 7092 * Stuff the message buffer with a BDR message and assert 7093 * ATN in the hopes that the target will let go of the bus 7094 * and go to the mesgout phase. If this fails, we'll 7095 * get another timeout 2 seconds later which will attempt 7096 * a bus reset. 7097 * 7098 * Target transaction: 7099 * Transition to BUS FREE and report the error. 7100 * It's good to be the target! 7101 */ 7102 saved_scbptr = ahc_inb(ahc, SCBPTR); 7103 active_scb_index = ahc_inb(ahc, SCB_TAG); 7104 7105 if ((ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) == 0 7106 && (active_scb_index < ahc->scb_data->numscbs)) { 7107 struct scb *active_scb; 7108 7109 /* 7110 * If the active SCB is not us, assume that 7111 * the active SCB has a longer timeout than 7112 * the timedout SCB, and wait for the active 7113 * SCB to timeout. 7114 */ 7115 active_scb = ahc_lookup_scb(ahc, active_scb_index); 7116 if (active_scb != scb) { 7117 if (ahc_other_scb_timeout(ahc, scb, 7118 active_scb) == 0) 7119 goto bus_reset; 7120 continue; 7121 } 7122 7123 /* It's us */ 7124 if ((scb->flags & SCB_TARGET_SCB) != 0) { 7125 7126 /* 7127 * Send back any queued up transactions 7128 * and properly record the error condition. 7129 */ 7130 ahc_abort_scbs(ahc, SCB_GET_TARGET(ahc, scb), 7131 SCB_GET_CHANNEL(ahc, scb), 7132 SCB_GET_LUN(scb), 7133 scb->hscb->tag, 7134 ROLE_TARGET, 7135 CAM_CMD_TIMEOUT); 7136 7137 /* Will clear us from the bus */ 7138 restart_needed = 1; 7139 break; 7140 } 7141 7142 ahc_set_recoveryscb(ahc, active_scb); 7143 ahc_outb(ahc, MSG_OUT, HOST_MSG); 7144 ahc_outb(ahc, SCSISIGO, last_phase|ATNO); 7145 ahc_print_path(ahc, active_scb); 7146 printf("BDR message in message buffer\n"); 7147 active_scb->flags |= SCB_DEVICE_RESET; 7148 aic_scb_timer_reset(scb, 2 * 1000); 7149 } else if (last_phase != P_BUSFREE 7150 && (ahc_inb(ahc, SSTAT1) & REQINIT) == 0) { 7151 /* 7152 * SCB is not identified, there 7153 * is no pending REQ, and the sequencer 7154 * has not seen a busfree. Looks like 7155 * a stuck connection waiting to 7156 * go busfree. Reset the bus. 7157 */ 7158 printf("%s: Connection stuck awaiting busfree or " 7159 "Identify Msg.\n", ahc_name(ahc)); 7160 goto bus_reset; 7161 } else { 7162 int disconnected; 7163 7164 if (last_phase != P_BUSFREE 7165 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { 7166 /* Hung target selection. Goto busfree */ 7167 printf("%s: Hung target selection\n", 7168 ahc_name(ahc)); 7169 restart_needed = 1; 7170 break; 7171 } 7172 7173 /* XXX Shouldn't panic. Just punt instead? */ 7174 if ((scb->flags & SCB_TARGET_SCB) != 0) 7175 panic("Timed-out target SCB but bus idle"); 7176 7177 if (ahc_search_qinfifo(ahc, target, channel, lun, 7178 scb->hscb->tag, ROLE_INITIATOR, 7179 /*status*/0, SEARCH_COUNT) > 0) { 7180 disconnected = FALSE; 7181 } else { 7182 disconnected = TRUE; 7183 } 7184 7185 if (disconnected) { 7186 7187 ahc_set_recoveryscb(ahc, scb); 7188 /* 7189 * Actually re-queue this SCB in an attempt 7190 * to select the device before it reconnects. 7191 * In either case (selection or reselection), 7192 * we will now issue a target reset to the 7193 * timed-out device. 7194 * 7195 * Set the MK_MESSAGE control bit indicating 7196 * that we desire to send a message. We 7197 * also set the disconnected flag since 7198 * in the paging case there is no guarantee 7199 * that our SCB control byte matches the 7200 * version on the card. We don't want the 7201 * sequencer to abort the command thinking 7202 * an unsolicited reselection occurred. 7203 */ 7204 scb->hscb->control |= MK_MESSAGE|DISCONNECTED; 7205 scb->flags |= SCB_DEVICE_RESET; 7206 7207 /* 7208 * Remove any cached copy of this SCB in the 7209 * disconnected list in preparation for the 7210 * queuing of our abort SCB. We use the 7211 * same element in the SCB, SCB_NEXT, for 7212 * both the qinfifo and the disconnected list. 7213 */ 7214 ahc_search_disc_list(ahc, target, channel, 7215 lun, scb->hscb->tag, 7216 /*stop_on_first*/TRUE, 7217 /*remove*/TRUE, 7218 /*save_state*/FALSE); 7219 7220 /* 7221 * In the non-paging case, the sequencer will 7222 * never re-reference the in-core SCB. 7223 * To make sure we are notified during 7224 * reslection, set the MK_MESSAGE flag in 7225 * the card's copy of the SCB. 7226 */ 7227 if ((ahc->flags & AHC_PAGESCBS) == 0) { 7228 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 7229 ahc_outb(ahc, SCB_CONTROL, 7230 ahc_inb(ahc, SCB_CONTROL) 7231 | MK_MESSAGE); 7232 } 7233 7234 /* 7235 * Clear out any entries in the QINFIFO first 7236 * so we are the next SCB for this target 7237 * to run. 7238 */ 7239 ahc_search_qinfifo(ahc, 7240 SCB_GET_TARGET(ahc, scb), 7241 channel, SCB_GET_LUN(scb), 7242 SCB_LIST_NULL, 7243 ROLE_INITIATOR, 7244 CAM_REQUEUE_REQ, 7245 SEARCH_COMPLETE); 7246 ahc_print_path(ahc, scb); 7247 printf("Queuing a BDR SCB\n"); 7248 ahc_qinfifo_requeue_tail(ahc, scb); 7249 ahc_outb(ahc, SCBPTR, saved_scbptr); 7250 aic_scb_timer_reset(scb, 2 * 1000); 7251 } else { 7252 /* Go "immediately" to the bus reset */ 7253 /* This shouldn't happen */ 7254 ahc_set_recoveryscb(ahc, scb); 7255 ahc_print_path(ahc, scb); 7256 printf("SCB %d: Immediate reset. " 7257 "Flags = 0x%x\n", scb->hscb->tag, 7258 scb->flags); 7259 goto bus_reset; 7260 } 7261 } 7262 break; 7263 } 7264 7265 /* 7266 * Any remaining SCBs were not the "culprit", so remove 7267 * them from the timeout list. The timer for these commands 7268 * will be reset once the recovery SCB completes. 7269 */ 7270 while ((scb = LIST_FIRST(&ahc->timedout_scbs)) != NULL) { 7271 7272 LIST_REMOVE(scb, timedout_links); 7273 scb->flags &= ~SCB_TIMEDOUT; 7274 } 7275 7276 if (restart_needed) 7277 ahc_restart(ahc); 7278 else 7279 ahc_unpause(ahc); 7280} 7281 7282/************************* Target Mode ****************************************/ 7283#ifdef AHC_TARGET_MODE 7284cam_status 7285ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb, 7286 struct ahc_tmode_tstate **tstate, 7287 struct ahc_tmode_lstate **lstate, 7288 int notfound_failure) 7289{ 7290 7291 if ((ahc->features & AHC_TARGETMODE) == 0) 7292 return (CAM_REQ_INVALID); 7293 7294 /* 7295 * Handle the 'black hole' device that sucks up 7296 * requests to unattached luns on enabled targets. 7297 */ 7298 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 7299 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 7300 *tstate = NULL; 7301 *lstate = ahc->black_hole; 7302 } else { 7303 u_int max_id; 7304 7305 max_id = (ahc->features & AHC_WIDE) ? 15 : 7; 7306 if (ccb->ccb_h.target_id > max_id) 7307 return (CAM_TID_INVALID); 7308 7309 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS) 7310 return (CAM_LUN_INVALID); 7311 7312 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id]; 7313 *lstate = NULL; 7314 if (*tstate != NULL) 7315 *lstate = 7316 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 7317 } 7318 7319 if (notfound_failure != 0 && *lstate == NULL) 7320 return (CAM_PATH_INVALID); 7321 7322 return (CAM_REQ_CMP); 7323} 7324 7325void 7326ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) 7327{ 7328 struct ahc_tmode_tstate *tstate; 7329 struct ahc_tmode_lstate *lstate; 7330 struct ccb_en_lun *cel; 7331 cam_status status; 7332 u_int target; 7333 u_int lun; 7334 u_int target_mask; 7335 u_int our_id; 7336 int error; 7337 char channel; 7338 7339 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate, 7340 /*notfound_failure*/FALSE); 7341 7342 if (status != CAM_REQ_CMP) { 7343 ccb->ccb_h.status = status; 7344 return; 7345 } 7346 7347 if (cam_sim_bus(sim) == 0) 7348 our_id = ahc->our_id; 7349 else 7350 our_id = ahc->our_id_b; 7351 7352 if (ccb->ccb_h.target_id != our_id 7353 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 7354 /* 7355 * our_id represents our initiator ID, or 7356 * the ID of the first target to have an 7357 * enabled lun in target mode. There are 7358 * two cases that may preclude enabling a 7359 * target id other than our_id. 7360 * 7361 * o our_id is for an active initiator role. 7362 * Since the hardware does not support 7363 * reselections to the initiator role at 7364 * anything other than our_id, and our_id 7365 * is used by the hardware to indicate the 7366 * ID to use for both select-out and 7367 * reselect-out operations, the only target 7368 * ID we can support in this mode is our_id. 7369 * 7370 * o The MULTARGID feature is not available and 7371 * a previous target mode ID has been enabled. 7372 */ 7373 if ((ahc->features & AHC_MULTIROLE) != 0) { 7374 7375 if ((ahc->features & AHC_MULTI_TID) != 0 7376 && (ahc->flags & AHC_INITIATORROLE) != 0) { 7377 /* 7378 * Only allow additional targets if 7379 * the initiator role is disabled. 7380 * The hardware cannot handle a re-select-in 7381 * on the initiator id during a re-select-out 7382 * on a different target id. 7383 */ 7384 status = CAM_TID_INVALID; 7385 } else if ((ahc->flags & AHC_INITIATORROLE) != 0 7386 || ahc->enabled_luns > 0) { 7387 /* 7388 * Only allow our target id to change 7389 * if the initiator role is not configured 7390 * and there are no enabled luns which 7391 * are attached to the currently registered 7392 * scsi id. 7393 */ 7394 status = CAM_TID_INVALID; 7395 } 7396 } else if ((ahc->features & AHC_MULTI_TID) == 0 7397 && ahc->enabled_luns > 0) { 7398 7399 status = CAM_TID_INVALID; 7400 } 7401 } 7402 7403 if (status != CAM_REQ_CMP) { 7404 ccb->ccb_h.status = status; 7405 return; 7406 } 7407 7408 /* 7409 * We now have an id that is valid. 7410 * If we aren't in target mode, switch modes. 7411 */ 7412 if ((ahc->flags & AHC_TARGETROLE) == 0 7413 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 7414 ahc_flag saved_flags; 7415 7416 printf("Configuring Target Mode\n"); 7417 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 7418 ccb->ccb_h.status = CAM_BUSY; 7419 return; 7420 } 7421 saved_flags = ahc->flags; 7422 ahc->flags |= AHC_TARGETROLE; 7423 if ((ahc->features & AHC_MULTIROLE) == 0) 7424 ahc->flags &= ~AHC_INITIATORROLE; 7425 ahc_pause(ahc); 7426 error = ahc_loadseq(ahc); 7427 if (error != 0) { 7428 /* 7429 * Restore original configuration and notify 7430 * the caller that we cannot support target mode. 7431 * Since the adapter started out in this 7432 * configuration, the firmware load will succeed, 7433 * so there is no point in checking ahc_loadseq's 7434 * return value. 7435 */ 7436 ahc->flags = saved_flags; 7437 (void)ahc_loadseq(ahc); 7438 ahc_restart(ahc); 7439 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 7440 return; 7441 } 7442 ahc_restart(ahc); 7443 } 7444 cel = &ccb->cel; 7445 target = ccb->ccb_h.target_id; 7446 lun = ccb->ccb_h.target_lun; 7447 channel = SIM_CHANNEL(ahc, sim); 7448 target_mask = 0x01 << target; 7449 if (channel == 'B') 7450 target_mask <<= 8; 7451 7452 if (cel->enable != 0) { 7453 u_int scsiseq; 7454 7455 /* Are we already enabled?? */ 7456 if (lstate != NULL) { 7457 xpt_print_path(ccb->ccb_h.path); 7458 printf("Lun already enabled\n"); 7459 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 7460 return; 7461 } 7462 7463 if (cel->grp6_len != 0 7464 || cel->grp7_len != 0) { 7465 /* 7466 * Don't (yet?) support vendor 7467 * specific commands. 7468 */ 7469 ccb->ccb_h.status = CAM_REQ_INVALID; 7470 printf("Non-zero Group Codes\n"); 7471 return; 7472 } 7473 7474 /* 7475 * Seems to be okay. 7476 * Setup our data structures. 7477 */ 7478 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 7479 tstate = ahc_alloc_tstate(ahc, target, channel); 7480 if (tstate == NULL) { 7481 xpt_print_path(ccb->ccb_h.path); 7482 printf("Couldn't allocate tstate\n"); 7483 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 7484 return; 7485 } 7486 } 7487 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 7488 if (lstate == NULL) { 7489 xpt_print_path(ccb->ccb_h.path); 7490 printf("Couldn't allocate lstate\n"); 7491 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 7492 return; 7493 } 7494 memset(lstate, 0, sizeof(*lstate)); 7495 status = xpt_create_path(&lstate->path, /*periph*/NULL, 7496 xpt_path_path_id(ccb->ccb_h.path), 7497 xpt_path_target_id(ccb->ccb_h.path), 7498 xpt_path_lun_id(ccb->ccb_h.path)); 7499 if (status != CAM_REQ_CMP) { 7500 free(lstate, M_DEVBUF); 7501 xpt_print_path(ccb->ccb_h.path); 7502 printf("Couldn't allocate path\n"); 7503 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 7504 return; 7505 } 7506 SLIST_INIT(&lstate->accept_tios); 7507 SLIST_INIT(&lstate->immed_notifies); 7508 ahc_pause(ahc); 7509 if (target != CAM_TARGET_WILDCARD) { 7510 tstate->enabled_luns[lun] = lstate; 7511 ahc->enabled_luns++; 7512 7513 if ((ahc->features & AHC_MULTI_TID) != 0) { 7514 u_int targid_mask; 7515 7516 targid_mask = ahc_inb(ahc, TARGID) 7517 | (ahc_inb(ahc, TARGID + 1) << 8); 7518 7519 targid_mask |= target_mask; 7520 ahc_outb(ahc, TARGID, targid_mask); 7521 ahc_outb(ahc, TARGID+1, (targid_mask >> 8)); 7522 7523 ahc_update_scsiid(ahc, targid_mask); 7524 } else { 7525 u_int our_id; 7526 char channel; 7527 7528 channel = SIM_CHANNEL(ahc, sim); 7529 our_id = SIM_SCSI_ID(ahc, sim); 7530 7531 /* 7532 * This can only happen if selections 7533 * are not enabled 7534 */ 7535 if (target != our_id) { 7536 u_int sblkctl; 7537 char cur_channel; 7538 int swap; 7539 7540 sblkctl = ahc_inb(ahc, SBLKCTL); 7541 cur_channel = (sblkctl & SELBUSB) 7542 ? 'B' : 'A'; 7543 if ((ahc->features & AHC_TWIN) == 0) 7544 cur_channel = 'A'; 7545 swap = cur_channel != channel; 7546 if (channel == 'A') 7547 ahc->our_id = target; 7548 else 7549 ahc->our_id_b = target; 7550 7551 if (swap) 7552 ahc_outb(ahc, SBLKCTL, 7553 sblkctl ^ SELBUSB); 7554 7555 ahc_outb(ahc, SCSIID, target); 7556 7557 if (swap) 7558 ahc_outb(ahc, SBLKCTL, sblkctl); 7559 } 7560 } 7561 } else 7562 ahc->black_hole = lstate; 7563 /* Allow select-in operations */ 7564 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) { 7565 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7566 scsiseq |= ENSELI; 7567 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7568 scsiseq = ahc_inb(ahc, SCSISEQ); 7569 scsiseq |= ENSELI; 7570 ahc_outb(ahc, SCSISEQ, scsiseq); 7571 } 7572 ahc_unpause(ahc); 7573 ccb->ccb_h.status = CAM_REQ_CMP; 7574 xpt_print_path(ccb->ccb_h.path); 7575 printf("Lun now enabled for target mode\n"); 7576 } else { 7577 struct scb *scb; 7578 int i, empty; 7579 7580 if (lstate == NULL) { 7581 ccb->ccb_h.status = CAM_LUN_INVALID; 7582 return; 7583 } 7584 7585 ccb->ccb_h.status = CAM_REQ_CMP; 7586 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 7587 struct ccb_hdr *ccbh; 7588 7589 ccbh = &scb->io_ctx->ccb_h; 7590 if (ccbh->func_code == XPT_CONT_TARGET_IO 7591 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 7592 printf("CTIO pending\n"); 7593 ccb->ccb_h.status = CAM_REQ_INVALID; 7594 return; 7595 } 7596 } 7597 7598 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 7599 printf("ATIOs pending\n"); 7600 ccb->ccb_h.status = CAM_REQ_INVALID; 7601 } 7602 7603 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 7604 printf("INOTs pending\n"); 7605 ccb->ccb_h.status = CAM_REQ_INVALID; 7606 } 7607 7608 if (ccb->ccb_h.status != CAM_REQ_CMP) { 7609 return; 7610 } 7611 7612 xpt_print_path(ccb->ccb_h.path); 7613 printf("Target mode disabled\n"); 7614 xpt_free_path(lstate->path); 7615 free(lstate, M_DEVBUF); 7616 7617 ahc_pause(ahc); 7618 /* Can we clean up the target too? */ 7619 if (target != CAM_TARGET_WILDCARD) { 7620 tstate->enabled_luns[lun] = NULL; 7621 ahc->enabled_luns--; 7622 for (empty = 1, i = 0; i < 8; i++) 7623 if (tstate->enabled_luns[i] != NULL) { 7624 empty = 0; 7625 break; 7626 } 7627 7628 if (empty) { 7629 ahc_free_tstate(ahc, target, channel, 7630 /*force*/FALSE); 7631 if (ahc->features & AHC_MULTI_TID) { 7632 u_int targid_mask; 7633 7634 targid_mask = ahc_inb(ahc, TARGID) 7635 | (ahc_inb(ahc, TARGID + 1) 7636 << 8); 7637 7638 targid_mask &= ~target_mask; 7639 ahc_outb(ahc, TARGID, targid_mask); 7640 ahc_outb(ahc, TARGID+1, 7641 (targid_mask >> 8)); 7642 ahc_update_scsiid(ahc, targid_mask); 7643 } 7644 } 7645 } else { 7646 7647 ahc->black_hole = NULL; 7648 7649 /* 7650 * We can't allow selections without 7651 * our black hole device. 7652 */ 7653 empty = TRUE; 7654 } 7655 if (ahc->enabled_luns == 0) { 7656 /* Disallow select-in */ 7657 u_int scsiseq; 7658 7659 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7660 scsiseq &= ~ENSELI; 7661 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7662 scsiseq = ahc_inb(ahc, SCSISEQ); 7663 scsiseq &= ~ENSELI; 7664 ahc_outb(ahc, SCSISEQ, scsiseq); 7665 7666 if ((ahc->features & AHC_MULTIROLE) == 0) { 7667 printf("Configuring Initiator Mode\n"); 7668 ahc->flags &= ~AHC_TARGETROLE; 7669 ahc->flags |= AHC_INITIATORROLE; 7670 /* 7671 * Returning to a configuration that 7672 * fit previously will always succeed. 7673 */ 7674 (void)ahc_loadseq(ahc); 7675 ahc_restart(ahc); 7676 /* 7677 * Unpaused. The extra unpause 7678 * that follows is harmless. 7679 */ 7680 } 7681 } 7682 ahc_unpause(ahc); 7683 } 7684} 7685 7686static void 7687ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask) 7688{ 7689 u_int scsiid_mask; 7690 u_int scsiid; 7691 7692 if ((ahc->features & AHC_MULTI_TID) == 0) 7693 panic("ahc_update_scsiid called on non-multitid unit\n"); 7694 7695 /* 7696 * Since we will rely on the TARGID mask 7697 * for selection enables, ensure that OID 7698 * in SCSIID is not set to some other ID 7699 * that we don't want to allow selections on. 7700 */ 7701 if ((ahc->features & AHC_ULTRA2) != 0) 7702 scsiid = ahc_inb(ahc, SCSIID_ULTRA2); 7703 else 7704 scsiid = ahc_inb(ahc, SCSIID); 7705 scsiid_mask = 0x1 << (scsiid & OID); 7706 if ((targid_mask & scsiid_mask) == 0) { 7707 u_int our_id; 7708 7709 /* ffs counts from 1 */ 7710 our_id = ffs(targid_mask); 7711 if (our_id == 0) 7712 our_id = ahc->our_id; 7713 else 7714 our_id--; 7715 scsiid &= TID; 7716 scsiid |= our_id; 7717 } 7718 if ((ahc->features & AHC_ULTRA2) != 0) 7719 ahc_outb(ahc, SCSIID_ULTRA2, scsiid); 7720 else 7721 ahc_outb(ahc, SCSIID, scsiid); 7722} 7723 7724void 7725ahc_run_tqinfifo(struct ahc_softc *ahc, int paused) 7726{ 7727 struct target_cmd *cmd; 7728 7729 /* 7730 * If the card supports auto-access pause, 7731 * we can access the card directly regardless 7732 * of whether it is paused or not. 7733 */ 7734 if ((ahc->features & AHC_AUTOPAUSE) != 0) 7735 paused = TRUE; 7736 7737 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD); 7738 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) { 7739 7740 /* 7741 * Only advance through the queue if we 7742 * have the resources to process the command. 7743 */ 7744 if (ahc_handle_target_cmd(ahc, cmd) != 0) 7745 break; 7746 7747 cmd->cmd_valid = 0; 7748 aic_dmamap_sync(ahc, ahc->shared_data_dmat, 7749 ahc->shared_data_dmamap, 7750 ahc_targetcmd_offset(ahc, ahc->tqinfifonext), 7751 sizeof(struct target_cmd), 7752 BUS_DMASYNC_PREREAD); 7753 ahc->tqinfifonext++; 7754 7755 /* 7756 * Lazily update our position in the target mode incoming 7757 * command queue as seen by the sequencer. 7758 */ 7759 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 7760 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 7761 u_int hs_mailbox; 7762 7763 hs_mailbox = ahc_inb(ahc, HS_MAILBOX); 7764 hs_mailbox &= ~HOST_TQINPOS; 7765 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS; 7766 ahc_outb(ahc, HS_MAILBOX, hs_mailbox); 7767 } else { 7768 if (!paused) 7769 ahc_pause(ahc); 7770 ahc_outb(ahc, KERNEL_TQINPOS, 7771 ahc->tqinfifonext & HOST_TQINPOS); 7772 if (!paused) 7773 ahc_unpause(ahc); 7774 } 7775 } 7776 } 7777} 7778 7779static int 7780ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd) 7781{ 7782 struct ahc_tmode_tstate *tstate; 7783 struct ahc_tmode_lstate *lstate; 7784 struct ccb_accept_tio *atio; 7785 uint8_t *byte; 7786 int initiator; 7787 int target; 7788 int lun; 7789 7790 initiator = SCSIID_TARGET(ahc, cmd->scsiid); 7791 target = SCSIID_OUR_ID(cmd->scsiid); 7792 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 7793 7794 byte = cmd->bytes; 7795 tstate = ahc->enabled_targets[target]; 7796 lstate = NULL; 7797 if (tstate != NULL) 7798 lstate = tstate->enabled_luns[lun]; 7799 7800 /* 7801 * Commands for disabled luns go to the black hole driver. 7802 */ 7803 if (lstate == NULL) 7804 lstate = ahc->black_hole; 7805 7806 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 7807 if (atio == NULL) { 7808 ahc->flags |= AHC_TQINFIFO_BLOCKED; 7809 /* 7810 * Wait for more ATIOs from the peripheral driver for this lun. 7811 */ 7812 if (bootverbose) 7813 printf("%s: ATIOs exhausted\n", ahc_name(ahc)); 7814 return (1); 7815 } else 7816 ahc->flags &= ~AHC_TQINFIFO_BLOCKED; 7817#ifdef AHC_DEBUG 7818 if (ahc_debug & AHC_SHOW_TQIN) { 7819 printf("Incoming command from %d for %d:%d%s\n", 7820 initiator, target, lun, 7821 lstate == ahc->black_hole ? "(Black Holed)" : ""); 7822 } 7823#endif 7824 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 7825 7826 if (lstate == ahc->black_hole) { 7827 /* Fill in the wildcards */ 7828 atio->ccb_h.target_id = target; 7829 atio->ccb_h.target_lun = lun; 7830 } 7831 7832 /* 7833 * Package it up and send it off to 7834 * whomever has this lun enabled. 7835 */ 7836 atio->sense_len = 0; 7837 atio->init_id = initiator; 7838 if (byte[0] != 0xFF) { 7839 /* Tag was included */ 7840 atio->tag_action = *byte++; 7841 atio->tag_id = *byte++; 7842 atio->ccb_h.flags |= CAM_TAG_ACTION_VALID; 7843 } else { 7844 atio->ccb_h.flags &= ~CAM_TAG_ACTION_VALID; 7845 } 7846 byte++; 7847 7848 /* Okay. Now determine the cdb size based on the command code */ 7849 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 7850 case 0: 7851 atio->cdb_len = 6; 7852 break; 7853 case 1: 7854 case 2: 7855 atio->cdb_len = 10; 7856 break; 7857 case 4: 7858 atio->cdb_len = 16; 7859 break; 7860 case 5: 7861 atio->cdb_len = 12; 7862 break; 7863 case 3: 7864 default: 7865 /* Only copy the opcode. */ 7866 atio->cdb_len = 1; 7867 printf("Reserved or VU command code type encountered\n"); 7868 break; 7869 } 7870 7871 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 7872 7873 atio->ccb_h.status |= CAM_CDB_RECVD; 7874 7875 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 7876 /* 7877 * We weren't allowed to disconnect. 7878 * We're hanging on the bus until a 7879 * continue target I/O comes in response 7880 * to this accept tio. 7881 */ 7882#ifdef AHC_DEBUG 7883 if (ahc_debug & AHC_SHOW_TQIN) { 7884 printf("Received Immediate Command %d:%d:%d - %p\n", 7885 initiator, target, lun, ahc->pending_device); 7886 } 7887#endif 7888 ahc->pending_device = lstate; 7889 aic_freeze_ccb((union ccb *)atio); 7890 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 7891 } 7892 xpt_done((union ccb*)atio); 7893 return (0); 7894} 7895 7896#endif 7897