1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41 42 43 44 45 46/** 47 * @file 48 * 49 * Functions and typedefs for using Octeon in HiGig/HiGig+/HiGig2 mode over 50 * XAUI. 51 * 52 * <hr>$Revision: 70030 $<hr> 53 */ 54 55#ifndef __CVMX_HIGIG_H__ 56#define __CVMX_HIGIG_H__ 57#include "cvmx-wqe.h" 58#include "cvmx-helper.h" 59#include "cvmx-helper-util.h" 60 61#ifdef __cplusplus 62extern "C" { 63#endif 64 65typedef struct 66{ 67 union 68 { 69 uint32_t u32; 70 struct 71 { 72 uint32_t start : 8; /**< 8-bits of Preamble indicating start of frame */ 73 uint32_t hgi : 2; /**< HiGig interface format indicator 74 00 = Reserved 75 01 = Pure preamble - IEEE standard framing of 10GE 76 10 = XGS header - framing based on XGS family definition In this 77 format, the default length of the header is 12 bytes and additional 78 bytes are indicated by the HDR_EXT_LEN field 79 11 = Reserved */ 80 uint32_t cng_high : 1; /**< Congestion Bit High flag */ 81 uint32_t hdr_ext_len : 3; /**< This field is valid only if the HGI field is a b'10' and it indicates the extension 82 to the standard 12-bytes of XGS HiGig header. Each unit represents 4 83 bytes, giving a total of 16 additional extension bytes. Value of b'101', b'110' 84 and b'111' are reserved. For HGI field value of b'01' this field should be 85 b'01'. For all other values of HGI it is don't care. */ 86 uint32_t src_modid_6 : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of 87 SRC_MODID (bits 4:0 are in Byte 4 and bit 5 is in Byte 9). For HGI field 88 value of b'01' this field should be b'0'. For all other values of HGI it is don't 89 care. */ 90 uint32_t dst_modid_6 : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of 91 DST_MODID (bits 4:0 are in Byte 7 and bit 5 is in Byte 9). ). For HGI field 92 value of b'01' this field should be b'1'. For all other values of HGI it is don't 93 care. */ 94 uint32_t vid_high : 8; /**< 8-bits of the VLAN tag information */ 95 uint32_t vid_low : 8; /**< 8 bits LSB of the VLAN tag information */ 96 } s; 97 } dw0; 98 union 99 { 100 uint32_t u32; 101 struct 102 { 103 uint32_t src_modid_low : 5; /**< Bits 4:0 of Module ID of the source module on which the packet ingress (bit 104 5 is in Byte 9 and bit 6 Is in Byte 1) */ 105 uint32_t opcode : 3; /**< XGS HiGig op-code, indicating the type of packet 106 000 = Control frames used for CPU to CPU communications 107 001 = Unicast packet with destination resolved; The packet can be 108 either Layer 2 unicast packet or L3 unicast packet that was 109 routed in the ingress chip. 110 010 = Broadcast or unknown Unicast packet or unknown multicast, 111 destined to all members of the VLAN 112 011 = L2 Multicast packet, destined to all ports of the group indicated 113 in the L2MC_INDEX which is overlayed on DST_PORT/DST_MODID fields 114 100 = IP Multicast packet, destined to all ports of the group indicated 115 in the IPMC_INDEX which is overlayed on DST_PORT/DST_MODID fields 116 101 = Reserved 117 110 = Reserved 118 111 = Reserved */ 119 uint32_t pfm : 2; /**< Three Port Filtering Modes (0, 1, 2) used in handling registed/unregistered 120 multicast (unknown L2 multicast and IPMC) packets. This field is used 121 when OPCODE is 011 or 100 Semantics of PFM bits are as follows; 122 For registered L2 multicast packets: 123 PFM= 0 - Flood to VLAN 124 PFM= 1 or 2 - Send to group members in the L2MC table 125 For unregistered L2 multicast packets: 126 PFM= 0 or 1 - Flood to VLAN 127 PFM= 2 - Drop the packet */ 128 uint32_t src_port_tgid : 6; /**< If the MSB of this field is set, then it indicates the LAG the packet ingressed 129 on, else it represents the physical port the packet ingressed on. */ 130 uint32_t dst_port : 5; /**< Port number of destination port on which the packet needs to egress. */ 131 uint32_t priority : 3; /**< This is the internal priority of the packet. This internal priority will go through 132 COS_SEL mapping registers to map to the actual MMU queues. */ 133 uint32_t header_type : 2; /**< Indicates the format of the next 4 bytes of the XGS HiGig header 134 00 = Overlay 1 (default) 135 01 = Overlay 2 (Classification Tag) 136 10 = Reserved 137 11 = Reserved */ 138 uint32_t cng_low : 1; /**< Semantics of CNG_HIGH and CNG_LOW are as follows: The following 139 encodings are to make it backward compatible: 140 [CNG_HIGH, CNG_LOW] - COLOR 141 [0, 0] - Packet is green 142 [0, 1] - Packet is red 143 [1, 1] - Packet is yellow 144 [1, 0] - Undefined */ 145 uint32_t dst_modid_low : 5; /**< Bits [4-: 0] of Module ID of the destination port on which the packet needs to egress. */ 146 } s; 147 } dw1; 148 union 149 { 150 uint32_t u32; 151 struct 152 { 153 uint32_t dst_t : 1; /**< Destination Trunk: Indicates that the destination port is a member of a trunk 154 group. */ 155 uint32_t dst_tgid : 3; /**< Destination Trunk Group ID: Trunk group ID of the destination port. The 156 DO_NOT_LEARN bit is overlaid on the second bit of this field. */ 157 uint32_t ingress_tagged : 1; /**< Ingress Tagged: Indicates whether the packet was tagged when it originally 158 ingressed the system. */ 159 uint32_t mirror_only : 1; /**< Mirror Only: XGS 1/2 mode: Indicates that the packet was switched and only 160 needs to be mirrored. */ 161 uint32_t mirror_done : 1; /**< Mirroring Done: XGS1/2 mode: Indicates that the packet was mirrored and 162 may still need to be switched. */ 163 uint32_t mirror : 1; /**< Mirror: XGS3 mode: a mirror copy packet. XGS1/2 mode: Indicates that the 164 packet was switched and only needs to be mirrored. */ 165 166 uint32_t src_modid_5 : 1; /**< Source Module ID: Bit 5 of Src_ModID (bits 4:0 are in byte 4 and bit 6 is in 167 byte 1) */ 168 uint32_t dst_modid_5 : 1; /**< Destination Module ID: Bit 5 of Dst_ModID (bits 4:0 are in byte 7 and bit 6 169 is in byte 1) */ 170 uint32_t l3 : 1; /**< L3: Indicates that the packet is L3 switched */ 171 uint32_t label_present : 1; /**< Label Present: Indicates that header contains a 20-bit VC label: HiGig+ 172 added field. */ 173 uint32_t vc_label_16_19 : 4; /**< VC Label: Bits 19:16 of VC label: HiGig+ added field */ 174 uint32_t vc_label_0_15 : 16;/**< VC Label: Bits 15:0 of VC label: HiGig+ added field */ 175 } o1; 176 struct 177 { 178 uint32_t classification : 16; /**< Classification tag information from the HiGig device FFP */ 179 uint32_t reserved_0_15 : 16; 180 181 } o2; 182 } dw2; 183} cvmx_higig_header_t; 184 185typedef struct 186{ 187 union 188 { 189 uint32_t u32; 190 struct 191 { 192 uint32_t k_sop : 8; /**< The delimiter indicating the start of a packet transmission */ 193 uint32_t reserved_21_23 : 3; 194 uint32_t mcst : 1; /**< MCST indicates whether the packet should be unicast or 195 multicast forwarded through the XGS switching fabric 196 - 0: Unicast 197 - 1: Mulitcast */ 198 uint32_t tc : 4; /**< Traffic Class [3:0] indicates the distinctive Quality of Service (QoS) 199 the switching fabric will provide when forwarding the packet 200 through the fabric */ 201 uint32_t dst_modid_mgid : 8; /**< When MCST=0, this field indicates the destination XGS module to 202 which the packet will be delivered. When MCST=1, this field indicates 203 higher order bits of the Multicast Group ID. */ 204 uint32_t dst_pid_mgid : 8; /**< When MCST=0, this field indicates a port associated with the 205 module indicated by the DST_MODID, through which the packet 206 will exit the system. When MCST=1, this field indicates lower order 207 bits of the Multicast Group ID */ 208 } s; 209 } dw0; 210 union 211 { 212 uint32_t u32; 213 struct 214 { 215 uint32_t src_modid : 8; /**< Source Module ID indicates the source XGS module from which 216 the packet is originated. (It can also be used for the fabric multicast 217 load balancing purpose.) */ 218 uint32_t src_pid : 8; /**< Source Port ID indicates a port associated with the module 219 indicated by the SRC_MODID, through which the packet has 220 entered the system */ 221 uint32_t lbid : 8; /**< Load Balancing ID indicates a packet flow hashing index 222 computed by the ingress XGS module for statistical distribution of 223 packet flows through a multipath fabric */ 224 uint32_t dp : 2; /**< Drop Precedence indicates the traffic rate violation status of the 225 packet measured by the ingress module. 226 - 00: GREEN 227 - 01: RED 228 - 10: Reserved 229 - 11: Yellow */ 230 uint32_t reserved_3_5 : 3; 231 uint32_t ppd_type : 3; /**< Packet Processing Descriptor Type 232 - 000: PPD Overlay1 233 - 001: PPD Overlay2 234 - 010~111: Reserved */ 235 } s; 236 } dw1; 237 union 238 { 239 uint32_t u32; 240 struct 241 { 242 uint32_t dst_t : 1; /**< Destination Trunk: Indicates that the destination port is a member of a trunk 243 group. */ 244 uint32_t dst_tgid : 3; /**< Destination Trunk Group ID: Trunk group ID of the destination port. The 245 DO_NOT_LEARN bit is overlaid on the second bit of this field. */ 246 uint32_t ingress_tagged : 1; /**< Ingress Tagged: Indicates whether the packet was tagged when it originally 247 ingressed the system. */ 248 uint32_t mirror_only : 1; /**< Mirror Only: XGS 1/2 mode: Indicates that the packet was switched and only 249 needs to be mirrored. */ 250 uint32_t mirror_done : 1; /**< Mirroring Done: XGS1/2 mode: Indicates that the packet was mirrored and 251 may still need to be switched. */ 252 uint32_t mirror : 1; /**< Mirror: XGS3 mode: a mirror copy packet. XGS1/2 mode: Indicates that the 253 packet was switched and only needs to be mirrored. */ 254 uint32_t reserved_22_23 : 2; 255 uint32_t l3 : 1; /**< L3: Indicates that the packet is L3 switched */ 256 uint32_t label_present : 1; /**< Label Present: Indicates that header contains a 20-bit VC label: HiGig+ 257 added field. */ 258 uint32_t vc_label : 20; /**< Refer to the HiGig+ Architecture Specification */ 259 } o1; 260 struct 261 { 262 uint32_t classification : 16; /**< Classification tag information from the HiGig device FFP */ 263 uint32_t reserved_0_15 : 16; 264 } o2; 265 } dw2; 266 union 267 { 268 uint32_t u32; 269 struct 270 { 271 uint32_t vid : 16; /**< VLAN tag information */ 272 uint32_t pfm : 2; /**< Three Port Filtering Modes (0, 1, 2) used in handling registed/unregistered 273 multicast (unknown L2 multicast and IPMC) packets. This field is used 274 when OPCODE is 011 or 100 Semantics of PFM bits are as follows; 275 For registered L2 multicast packets: 276 PFM= 0 - Flood to VLAN 277 PFM= 1 or 2 - Send to group members in the L2MC table 278 For unregistered L2 multicast packets: 279 PFM= 0 or 1 - Flood to VLAN 280 PFM= 2 - Drop the packet */ 281 uint32_t src_t : 1; /**< If the MSB of this field is set, then it indicates the LAG the packet ingressed 282 on, else it represents the physical port the packet ingressed on. */ 283 uint32_t reserved_11_12 : 2; 284 uint32_t opcode : 3; /**< XGS HiGig op-code, indicating the type of packet 285 000 = Control frames used for CPU to CPU communications 286 001 = Unicast packet with destination resolved; The packet can be 287 either Layer 2 unicast packet or L3 unicast packet that was 288 routed in the ingress chip. 289 010 = Broadcast or unknown Unicast packet or unknown multicast, 290 destined to all members of the VLAN 291 011 = L2 Multicast packet, destined to all ports of the group indicated 292 in the L2MC_INDEX which is overlayed on DST_PORT/DST_MODID fields 293 100 = IP Multicast packet, destined to all ports of the group indicated 294 in the IPMC_INDEX which is overlayed on DST_PORT/DST_MODID fields 295 101 = Reserved 296 110 = Reserved 297 111 = Reserved */ 298 uint32_t hdr_ext_len : 3; /**< This field is valid only if the HGI field is a b'10' and it indicates the extension 299 to the standard 12-bytes of XGS HiGig header. Each unit represents 4 300 bytes, giving a total of 16 additional extension bytes. Value of b'101', b'110' 301 and b'111' are reserved. For HGI field value of b'01' this field should be 302 b'01'. For all other values of HGI it is don't care. */ 303 uint32_t reserved_0_4 : 5; 304 } s; 305 } dw3; 306} cvmx_higig2_header_t; 307 308 309/** 310 * Initialize the HiGig aspects of a XAUI interface. This function 311 * should be called before the cvmx-helper generic init. 312 * 313 * @param interface Interface to initialize HiGig on (0-1) 314 * @param enable_higig2 315 * Non zero to enable HiGig2 support. Zero to support HiGig 316 * and HiGig+. 317 * 318 * @return Zero on success, negative on failure 319 */ 320static inline int cvmx_higig_initialize(int interface, int enable_higig2) 321{ 322 cvmx_pip_prt_cfgx_t pip_prt_cfg; 323 cvmx_gmxx_rxx_udd_skp_t gmx_rx_udd_skp; 324 cvmx_gmxx_txx_min_pkt_t gmx_tx_min_pkt; 325 cvmx_gmxx_txx_append_t gmx_tx_append; 326 cvmx_gmxx_tx_ifg_t gmx_tx_ifg; 327 cvmx_gmxx_tx_ovr_bp_t gmx_tx_ovr_bp; 328 cvmx_gmxx_rxx_frm_ctl_t gmx_rx_frm_ctl; 329 cvmx_gmxx_tx_xaui_ctl_t gmx_tx_xaui_ctl; 330 int i, pknd; 331 int header_size = (enable_higig2) ? 16 : 12; 332 333 /* Setup PIP to handle HiGig */ 334 if (octeon_has_feature(OCTEON_FEATURE_PKND)) 335 pknd = cvmx_helper_get_pknd(interface, 0); 336 else 337 pknd = interface*16; 338 pip_prt_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(pknd)); 339 pip_prt_cfg.s.dsa_en = 0; 340 pip_prt_cfg.s.higig_en = 1; 341 pip_prt_cfg.s.hg_qos = 1; 342 pip_prt_cfg.s.skip = header_size; 343 cvmx_write_csr(CVMX_PIP_PRT_CFGX(pknd), pip_prt_cfg.u64); 344 345 /* Setup some sample QoS defaults. These can be changed later */ 346 if (!OCTEON_IS_MODEL(OCTEON_CN68XX)) 347 { 348 for (i=0; i<64; i++) 349 { 350 cvmx_pip_hg_pri_qos_t pip_hg_pri_qos; 351 pip_hg_pri_qos.u64 = 0; 352 pip_hg_pri_qos.s.up_qos = 1; 353 pip_hg_pri_qos.s.pri = i; 354 pip_hg_pri_qos.s.qos = i&7; 355 cvmx_write_csr(CVMX_PIP_HG_PRI_QOS, pip_hg_pri_qos.u64); 356 } 357 } 358 359 /* Setup GMX RX to treat the HiGig header as user data to ignore */ 360 gmx_rx_udd_skp.u64 = cvmx_read_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface)); 361 gmx_rx_udd_skp.s.len = header_size; 362 gmx_rx_udd_skp.s.fcssel = 0; 363 cvmx_write_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface), gmx_rx_udd_skp.u64); 364 365 /* Disable GMX preamble checking */ 366 gmx_rx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface)); 367 gmx_rx_frm_ctl.s.pre_chk = 0; 368 cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface), gmx_rx_frm_ctl.u64); 369 370 /* Setup GMX TX to pad properly min sized packets */ 371 gmx_tx_min_pkt.u64 = cvmx_read_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface)); 372 gmx_tx_min_pkt.s.min_size = 59 + header_size; 373 cvmx_write_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface), gmx_tx_min_pkt.u64); 374 375 /* Setup GMX TX to not add a preamble */ 376 gmx_tx_append.u64 = cvmx_read_csr(CVMX_GMXX_TXX_APPEND(0, interface)); 377 gmx_tx_append.s.preamble = 0; 378 cvmx_write_csr(CVMX_GMXX_TXX_APPEND(0, interface), gmx_tx_append.u64); 379 380 /* Reduce the inter frame gap to 8 bytes */ 381 gmx_tx_ifg.u64 = cvmx_read_csr(CVMX_GMXX_TX_IFG(interface)); 382 gmx_tx_ifg.s.ifg1 = 4; 383 gmx_tx_ifg.s.ifg2 = 4; 384 cvmx_write_csr(CVMX_GMXX_TX_IFG(interface), gmx_tx_ifg.u64); 385 386 /* Disable GMX backpressure */ 387 gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface)); 388 gmx_tx_ovr_bp.s.bp = 0; 389 gmx_tx_ovr_bp.s.en = 0xf; 390 gmx_tx_ovr_bp.s.ign_full = 0xf; 391 cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64); 392 393 if (enable_higig2) 394 { 395 /* Enable HiGig2 support and forwarding of virtual port backpressure 396 to PKO */ 397 cvmx_gmxx_hg2_control_t gmx_hg2_control; 398 gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface)); 399 gmx_hg2_control.s.hg2rx_en = 1; 400 gmx_hg2_control.s.hg2tx_en = 1; 401 gmx_hg2_control.s.logl_en = 0xffff; 402 gmx_hg2_control.s.phys_en = 1; 403 cvmx_write_csr(CVMX_GMXX_HG2_CONTROL(interface), gmx_hg2_control.u64); 404 } 405 406 /* Enable HiGig */ 407 gmx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); 408 gmx_tx_xaui_ctl.s.hg_en = 1; 409 cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmx_tx_xaui_ctl.u64); 410 411 return 0; 412} 413 414#ifdef __cplusplus 415} 416#endif 417 418#endif // __CVMX_HIGIG_H__ 419